Break up vl.h.

[qemu] / hw / sparc32_dma.c

diff --git a/hw/sparc32_dma.c b/hw/sparc32_dma.c
index de14998..742f2d8 100644 (file)
--- a/hw/sparc32_dma.c
+++ b/hw/sparc32_dma.c
@@ -21,7 +21,9 @@
  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  * THE SOFTWARE.
  */
-#include "vl.h"
+#include "hw.h"
+#include "sparc32_dma.h"
+#include "sun4m.h"
 
 /* debug DMA */
 //#define DEBUG_DMA
@@ -58,13 +60,12 @@ typedef struct DMAState DMAState;
 struct DMAState {
     uint32_t dmaregs[DMA_REGS];
     qemu_irq irq;
-    void *iommu, *dev_opaque;
-    void (*dev_reset)(void *dev_opaque);
-    qemu_irq *pic;
+    void *iommu;
+    qemu_irq dev_reset;
 };
 
 /* Note: on sparc, the lance 16 bit bus is swapped */
-void ledma_memory_read(void *opaque, target_phys_addr_t addr, 
+void ledma_memory_read(void *opaque, target_phys_addr_t addr,
                        uint8_t *buf, int len, int do_bswap)
 {
     DMAState *s = opaque;
@@ -85,7 +86,7 @@ void ledma_memory_read(void *opaque, target_phys_addr_t addr,
     }
 }
 
-void ledma_memory_write(void *opaque, target_phys_addr_t addr, 
+void ledma_memory_write(void *opaque, target_phys_addr_t addr,
                         uint8_t *buf, int len, int do_bswap)
 {
     DMAState *s = opaque;
@@ -115,22 +116,18 @@ void ledma_memory_write(void *opaque, target_phys_addr_t addr,
     }
 }
 
-void espdma_raise_irq(void *opaque)
+static void dma_set_irq(void *opaque, int irq, int level)
 {
     DMAState *s = opaque;
-
-    DPRINTF("Raise ESP IRQ\n");
-    s->dmaregs[0] |= DMA_INTR;
-    qemu_irq_raise(s->irq);
-}
-
-void espdma_clear_irq(void *opaque)
-{
-    DMAState *s = opaque;
-
-    s->dmaregs[0] &= ~DMA_INTR;
-    DPRINTF("Lower ESP IRQ\n");
-    qemu_irq_lower(s->irq);
+    if (level) {
+        DPRINTF("Raise IRQ\n");
+        s->dmaregs[0] |= DMA_INTR;
+        qemu_irq_raise(s->irq);
+    } else {
+        s->dmaregs[0] &= ~DMA_INTR;
+        DPRINTF("Lower IRQ\n");
+        qemu_irq_lower(s->irq);
+    }
 }
 
 void espdma_memory_read(void *opaque, uint8_t *buf, int len)
@@ -182,7 +179,8 @@ static void dma_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
             qemu_irq_lower(s->irq);
         }
         if (val & DMA_RESET) {
-            s->dev_reset(s->dev_opaque);
+            qemu_irq_raise(s->dev_reset);
+            qemu_irq_lower(s->dev_reset);
         } else if (val & DMA_DRAIN_FIFO) {
             val &= ~DMA_DRAIN_FIFO;
         } else if (val == 0)
@@ -241,7 +239,8 @@ static int dma_load(QEMUFile *f, void *opaque, int version_id)
     return 0;
 }
 
-void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq irq, void *iommu)
+void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq parent_irq,
+                       void *iommu, qemu_irq **dev_irq, qemu_irq **reset)
 {
     DMAState *s;
     int dma_io_memory;
@@ -250,7 +249,7 @@ void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq irq, void *iommu)
     if (!s)
         return NULL;
 
-    s->irq = irq;
+    s->irq = parent_irq;
     s->iommu = iommu;
 
     dma_io_memory = cpu_register_io_memory(0, dma_mem_read, dma_mem_write, s);
@@ -258,15 +257,9 @@ void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq irq, void *iommu)
 
     register_savevm("sparc32_dma", daddr, 2, dma_save, dma_load, s);
     qemu_register_reset(dma_reset, s);
+    *dev_irq = qemu_allocate_irqs(dma_set_irq, s, 1);
 
-    return s;
-}
+    *reset = &s->dev_reset;
 
-void sparc32_dma_set_reset_data(void *opaque, void (*dev_reset)(void *opaque),
-                                void *dev_opaque)
-{
-    DMAState *s = opaque;
-
-    s->dev_reset = dev_reset;
-    s->dev_opaque = dev_opaque;
+    return s;
 }