struct vmsvga_state_s {
#ifdef EMBED_STDVGA
- VGA_STATE_COMMON
+ VGACommonState vga;
#endif
int width;
DisplayState *ds;
int vram_size;
ram_addr_t vram_offset;
+ uint8_t *vram_ptr;
#endif
- uint8_t *vram;
target_phys_addr_t vram_base;
int index;
#ifdef VERBOSE
# define GUEST_OS_BASE 0x5001
static const char *vmsvga_guest_id[] = {
- [0x00 ... 0x15] = "an unknown OS",
[0x00] = "Dos",
[0x01] = "Windows 3.1",
[0x02] = "Windows 95",
[0x06] = "Windows 2000",
[0x07] = "Linux",
[0x08] = "OS/2",
+ [0x09] = "an unknown OS",
[0x0a] = "BSD",
[0x0b] = "Whistler",
+ [0x0c] = "an unknown OS",
+ [0x0d] = "an unknown OS",
+ [0x0e] = "an unknown OS",
+ [0x0f] = "an unknown OS",
+ [0x10] = "an unknown OS",
+ [0x11] = "an unknown OS",
+ [0x12] = "an unknown OS",
+ [0x13] = "an unknown OS",
+ [0x14] = "an unknown OS",
[0x15] = "Windows 2003",
};
#endif
bypl = s->bypp * s->width;
width = s->bypp * w;
start = s->bypp * x + bypl * y;
- src = s->vram + start;
- dst = ds_get_data(s->ds) + start;
+ src = s->vga.vram_ptr + start;
+ dst = ds_get_data(s->vga.ds) + start;
for (; line > 0; line --, src += bypl, dst += bypl)
memcpy(dst, src, width);
#endif
- dpy_update(s->ds, x, y, w, h);
+ dpy_update(s->vga.ds, x, y, w, h);
}
static inline void vmsvga_update_screen(struct vmsvga_state_s *s)
{
#ifndef DIRECT_VRAM
- memcpy(ds_get_data(s->ds), s->vram, s->bypp * s->width * s->height);
+ memcpy(ds_get_data(s->vga.ds), s->vga.vram_ptr, s->bypp * s->width * s->height);
#endif
- dpy_update(s->ds, 0, 0, s->width, s->height);
+ dpy_update(s->vga.ds, 0, 0, s->width, s->height);
}
#ifdef DIRECT_VRAM
# ifdef DIRECT_VRAM
uint8_t *vram = ds_get_data(s->ds);
# else
- uint8_t *vram = s->vram;
+ uint8_t *vram = s->vga.vram_ptr;
# endif
int bypl = s->bypp * s->width;
int width = s->bypp * w;
# ifdef DIRECT_VRAM
uint8_t *vram = ds_get_data(s->ds);
# else
- uint8_t *vram = s->vram;
+ uint8_t *vram = s->vga.vram_ptr;
# endif
int bypp = s->bypp;
int bypl = bypp * s->width;
for (i = SVGA_BITMAP_SIZE(c->width, c->height) - 1; i >= 0; i --)
c->mask[i] = ~c->mask[i];
- if (s->ds->cursor_define)
- s->ds->cursor_define(c->width, c->height, c->bpp, c->hot_x, c->hot_y,
+ if (s->vga.ds->cursor_define)
+ s->vga.ds->cursor_define(c->width, c->height, c->bpp, c->hot_x, c->hot_y,
(uint8_t *) c->image, (uint8_t *) c->mask);
}
#endif
return 0x0;
case SVGA_REG_VRAM_SIZE:
- return s->vram_size - SVGA_FIFO_SIZE;
+ return s->vga.vram_size - SVGA_FIFO_SIZE;
case SVGA_REG_FB_SIZE:
return s->fb_size;
caps |= SVGA_CAP_RECT_FILL;
#endif
#ifdef HW_MOUSE_ACCEL
- if (s->ds->mouse_set)
+ if (s->vga.ds->mouse_set)
caps |= SVGA_CAP_CURSOR | SVGA_CAP_CURSOR_BYPASS_2 |
SVGA_CAP_CURSOR_BYPASS;
#endif
return caps;
case SVGA_REG_MEM_START:
- return s->vram_base + s->vram_size - SVGA_FIFO_SIZE;
+ return s->vram_base + s->vga.vram_size - SVGA_FIFO_SIZE;
case SVGA_REG_MEM_SIZE:
return SVGA_FIFO_SIZE;
s->height = -1;
s->invalidated = 1;
#ifdef EMBED_STDVGA
- s->invalidate(opaque);
+ s->vga.invalidate(&s->vga);
#endif
if (s->enable)
s->fb_size = ((s->depth + 7) >> 3) * s->new_width * s->new_height;
case SVGA_REG_CONFIG_DONE:
if (value) {
- s->fifo = (uint32_t *) &s->vram[s->vram_size - SVGA_FIFO_SIZE];
+ s->fifo = (uint32_t *) &s->vga.vram_ptr[s->vga.vram_size - SVGA_FIFO_SIZE];
/* Check range and alignment. */
if ((CMD(min) | CMD(max) |
CMD(next_cmd) | CMD(stop)) & 3)
s->cursor.on |= (value == SVGA_CURSOR_ON_SHOW);
s->cursor.on &= (value != SVGA_CURSOR_ON_HIDE);
#ifdef HW_MOUSE_ACCEL
- if (s->ds->mouse_set && value <= SVGA_CURSOR_ON_SHOW)
- s->ds->mouse_set(s->cursor.x, s->cursor.y, s->cursor.on);
+ if (s->vga.ds->mouse_set && value <= SVGA_CURSOR_ON_SHOW)
+ s->vga.ds->mouse_set(s->cursor.x, s->cursor.y, s->cursor.on);
#endif
break;
if (s->new_width != s->width || s->new_height != s->height) {
s->width = s->new_width;
s->height = s->new_height;
- qemu_console_resize(s->ds, s->width, s->height);
+ qemu_console_resize(s->vga.ds, s->width, s->height);
s->invalidated = 1;
}
}
struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
if (!s->enable) {
#ifdef EMBED_STDVGA
- s->update(opaque);
+ s->vga.update(&s->vga);
#endif
return;
}
struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
if (!s->enable) {
#ifdef EMBED_STDVGA
- s->invalidate(opaque);
+ s->vga.invalidate(&s->vga);
#endif
return;
}
struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
if (!s->enable) {
#ifdef EMBED_STDVGA
- s->screen_dump(opaque, filename);
+ s->vga.screen_dump(&s->vga, filename);
#endif
return;
}
if (s->depth == 32) {
DisplaySurface *ds = qemu_create_displaysurface_from(s->width,
- s->height, 32, ds_get_linesize(s->ds), s->vram);
+ s->height, 32, ds_get_linesize(s->vga.ds), s->vga.vram_ptr);
ppm_save(filename, ds);
qemu_free(ds);
}
{
struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
- if (s->text_update)
- s->text_update(opaque, chardata);
+ if (s->vga.text_update)
+ s->vga.text_update(&s->vga, chardata);
}
#ifdef DIRECT_VRAM
if (addr < s->fb_size)
return *(uint8_t *) (ds_get_data(s->ds) + addr);
else
- return *(uint8_t *) (s->vram + addr);
+ return *(uint8_t *) (s->vram_ptr + addr);
}
static uint32_t vmsvga_vram_readw(void *opaque, target_phys_addr_t addr)
if (addr < s->fb_size)
return *(uint16_t *) (ds_get_data(s->ds) + addr);
else
- return *(uint16_t *) (s->vram + addr);
+ return *(uint16_t *) (s->vram_ptr + addr);
}
static uint32_t vmsvga_vram_readl(void *opaque, target_phys_addr_t addr)
if (addr < s->fb_size)
return *(uint32_t *) (ds_get_data(s->ds) + addr);
else
- return *(uint32_t *) (s->vram + addr);
+ return *(uint32_t *) (s->vram_ptr + addr);
}
static void vmsvga_vram_writeb(void *opaque, target_phys_addr_t addr,
if (addr < s->fb_size)
*(uint8_t *) (ds_get_data(s->ds) + addr) = value;
else
- *(uint8_t *) (s->vram + addr) = value;
+ *(uint8_t *) (s->vram_ptr + addr) = value;
}
static void vmsvga_vram_writew(void *opaque, target_phys_addr_t addr,
if (addr < s->fb_size)
*(uint16_t *) (ds_get_data(s->ds) + addr) = value;
else
- *(uint16_t *) (s->vram + addr) = value;
+ *(uint16_t *) (s->vram_ptr + addr) = value;
}
static void vmsvga_vram_writel(void *opaque, target_phys_addr_t addr,
if (addr < s->fb_size)
*(uint32_t *) (ds_get_data(s->ds) + addr) = value;
else
- *(uint32_t *) (s->vram + addr) = value;
+ *(uint32_t *) (s->vram_ptr + addr) = value;
}
static CPUReadMemoryFunc *vmsvga_vram_read[] = {
s->invalidated = 1;
if (s->config)
- s->fifo = (uint32_t *) &s->vram[s->vram_size - SVGA_FIFO_SIZE];
+ s->fifo = (uint32_t *) &s->vga.vram_ptr[s->vga.vram_size - SVGA_FIFO_SIZE];
return 0;
}
-static void vmsvga_init(struct vmsvga_state_s *s,
- uint8_t *vga_ram_base, unsigned long vga_ram_offset,
- int vga_ram_size)
+static void vmsvga_init(struct vmsvga_state_s *s, int vga_ram_size)
{
- s->vram = vga_ram_base;
- s->vram_size = vga_ram_size;
- s->vram_offset = vga_ram_offset;
-
s->scratch_size = SVGA_SCRATCH_SIZE;
s->scratch = (uint32_t *) qemu_malloc(s->scratch_size * 4);
vmsvga_reset(s);
#ifdef EMBED_STDVGA
- vga_common_init((VGAState *) s,
- vga_ram_base, vga_ram_offset, vga_ram_size);
+ vga_common_init((VGAState *) s, vga_ram_size);
vga_init((VGAState *) s);
+#else
+ s->vram_size = vga_ram_size;
+ s->vram_offset = qemu_ram_alloc(vga_ram_size);
+ s->vram_ptr = qemu_get_ram_ptr(s->vram_offset);
#endif
- s->ds = graphic_console_init(vmsvga_update_display,
- vmsvga_invalidate_display,
- vmsvga_screen_dump,
- vmsvga_text_update, s);
+ s->vga.ds = graphic_console_init(vmsvga_update_display,
+ vmsvga_invalidate_display,
+ vmsvga_screen_dump,
+ vmsvga_text_update, &s->vga);
#ifdef CONFIG_BOCHS_VBE
/* XXX: use optimized standard vga accesses */
cpu_register_physical_memory(VBE_DISPI_LFB_PHYSICAL_ADDRESS,
- vga_ram_size, vga_ram_offset);
+ vga_ram_size, s->vga.vram_offset);
#endif
}
iomemtype = cpu_register_io_memory(0, vmsvga_vram_read,
vmsvga_vram_write, s);
#else
- iomemtype = s->vram_offset | IO_MEM_RAM;
+ iomemtype = s->vga.vram_offset | IO_MEM_RAM;
#endif
- cpu_register_physical_memory(s->vram_base, s->vram_size,
+ cpu_register_physical_memory(s->vram_base, s->vga.vram_size,
iomemtype);
}
-#define PCI_VENDOR_ID_VMWARE 0x15ad
-#define PCI_DEVICE_ID_VMWARE_SVGA2 0x0405
-#define PCI_DEVICE_ID_VMWARE_SVGA 0x0710
-#define PCI_DEVICE_ID_VMWARE_NET 0x0720
-#define PCI_DEVICE_ID_VMWARE_SCSI 0x0730
-#define PCI_DEVICE_ID_VMWARE_IDE 0x1729
-#define PCI_CLASS_BASE_DISPLAY 0x03
-#define PCI_CLASS_SUB_VGA 0x00
-#define PCI_CLASS_HEADERTYPE_00h 0x00
-
-void pci_vmsvga_init(PCIBus *bus, uint8_t *vga_ram_base,
- unsigned long vga_ram_offset, int vga_ram_size)
+void pci_vmsvga_init(PCIBus *bus)
{
struct pci_vmsvga_state_s *s;
s = (struct pci_vmsvga_state_s *)
pci_register_device(bus, "QEMUware SVGA",
sizeof(struct pci_vmsvga_state_s), -1, 0, 0);
- s->card.config[PCI_VENDOR_ID] = PCI_VENDOR_ID_VMWARE & 0xff;
- s->card.config[PCI_VENDOR_ID + 1] = PCI_VENDOR_ID_VMWARE >> 8;
- s->card.config[PCI_DEVICE_ID] = SVGA_PCI_DEVICE_ID & 0xff;
- s->card.config[PCI_DEVICE_ID + 1] = SVGA_PCI_DEVICE_ID >> 8;
+ pci_config_set_vendor_id(s->card.config, PCI_VENDOR_ID_VMWARE);
+ pci_config_set_device_id(s->card.config, SVGA_PCI_DEVICE_ID);
s->card.config[PCI_COMMAND] = 0x07; /* I/O + Memory */
- s->card.config[PCI_CLASS_DEVICE] = PCI_CLASS_SUB_VGA;
- s->card.config[0x0b] = PCI_CLASS_BASE_DISPLAY;
+ pci_config_set_class(s->card.config, PCI_CLASS_DISPLAY_VGA);
s->card.config[0x0c] = 0x08; /* Cache line size */
s->card.config[0x0d] = 0x40; /* Latency timer */
- s->card.config[0x0e] = PCI_CLASS_HEADERTYPE_00h;
+ s->card.config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL;
s->card.config[0x2c] = PCI_VENDOR_ID_VMWARE & 0xff;
s->card.config[0x2d] = PCI_VENDOR_ID_VMWARE >> 8;
s->card.config[0x2e] = SVGA_PCI_DEVICE_ID & 0xff;
pci_register_io_region(&s->card, 0, 0x10,
PCI_ADDRESS_SPACE_IO, pci_vmsvga_map_ioport);
- pci_register_io_region(&s->card, 1, vga_ram_size,
+ pci_register_io_region(&s->card, 1, VGA_RAM_SIZE,
PCI_ADDRESS_SPACE_MEM_PREFETCH, pci_vmsvga_map_mem);
- vmsvga_init(&s->chip, vga_ram_base, vga_ram_offset, vga_ram_size);
+ vmsvga_init(&s->chip, VGA_RAM_SIZE);
register_savevm("vmware_vga", 0, 0, pci_vmsvga_save, pci_vmsvga_load, s);
}
projects / qemu / blobdiff