Handle cpu_model in copy_cpu(), by Kirill A. Shutemov.

[qemu] / target-arm / helper.c

diff --git a/target-arm/helper.c b/target-arm/helper.c
index 038025d..86470db 100644 (file)
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -182,6 +182,7 @@ CPUARMState *cpu_arm_init(const char *cpu_model)
     if (!env)
         return NULL;
     cpu_exec_init(env);
+    env->cpu_model_str = cpu_model;
     env->cp15.c0_cpuid = id;
     cpu_reset(env);
     return env;
@@ -602,6 +603,15 @@ void do_interrupt_v7m(CPUARMState *env)
         armv7m_nvic_set_pending(env->v7m.nvic, ARMV7M_EXCP_MEM);
         return;
     case EXCP_BKPT:
+        if (semihosting_enabled) {
+            int nr;
+            nr = lduw_code(env->regs[15]) & 0xff;
+            if (nr == 0xab) {
+                env->regs[15] += 2;
+                env->regs[0] = do_arm_semihosting(env);
+                return;
+            }
+        }
         armv7m_nvic_set_pending(env->v7m.nvic, ARMV7M_EXCP_DEBUG);
         return;
     case EXCP_IRQ:
@@ -687,7 +697,7 @@ void do_interrupt(CPUARMState *env)
         break;
     case EXCP_BKPT:
         /* See if this is a semihosting syscall.  */
-        if (env->thumb) {
+        if (env->thumb && semihosting_enabled) {
             mask = lduw_code(env->regs[15]) & 0xff;
             if (mask == 0xab
                   && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {