* ARM micro operations
*
* Copyright (c) 2003 Fabrice Bellard
+ * Copyright (c) 2005 CodeSourcery, LLC
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
#define REGNAME r15
#define REG (env->regs[15])
+#define SET_REG(x) REG = x & ~(uint32_t)1
#include "op_template.h"
+void OPPROTO op_bx_T0(void)
+{
+ env->regs[15] = T0 & ~(uint32_t)1;
+ env->thumb = (T0 & 1) != 0;
+}
+
void OPPROTO op_movl_T0_0(void)
{
T0 = 0;
T1 = PARAM1;
}
+void OPPROTO op_mov_CF_T1(void)
+{
+ env->CF = ((uint32_t)T1) >> 31;
+}
+
void OPPROTO op_movl_T2_im(void)
{
T2 = PARAM1;
src1 = T0; \
if (!env->CF) { \
T0 = T0 - T1 - 1; \
- env->CF = src1 >= T1; \
+ env->CF = src1 > T1; \
} else { \
T0 = T0 - T1; \
- env->CF = src1 > T1; \
+ env->CF = src1 >= T1; \
} \
env->VF = (src1 ^ T1) & (src1 ^ T0); \
env->NZF = T0; \
void OPPROTO op_mull_T0_T1(void)
{
uint64_t res;
- res = T0 * T1;
+ res = (uint64_t)T0 * (uint64_t)T1;
T1 = res >> 32;
T0 = res;
}
void OPPROTO op_imull_T0_T1(void)
{
uint64_t res;
- res = (int32_t)T0 * (int32_t)T1;
+ res = (int64_t)((int32_t)T0) * (int64_t)((int32_t)T1);
T1 = res >> 32;
T0 = res;
}
+/* 48 bit signed mul, top 32 bits */
+void OPPROTO op_imulw_T0_T1(void)
+{
+ uint64_t res;
+ res = (int64_t)((int32_t)T0) * (int64_t)((int32_t)T1);
+ T0 = res >> 16;
+}
+
void OPPROTO op_addq_T0_T1(void)
{
uint64_t res;
T0 = res;
}
+void OPPROTO op_addq_lo_T0_T1(void)
+{
+ uint64_t res;
+ res = ((uint64_t)T1 << 32) | T0;
+ res += (uint64_t)(env->regs[PARAM1]);
+ T1 = res >> 32;
+ T0 = res;
+}
+
void OPPROTO op_logicq_cc(void)
{
env->NZF = (T1 & 0x80000000) | ((T0 | T1) != 0);
/* shifts */
/* T1 based */
+
void OPPROTO op_shll_T1_im(void)
{
T1 = T1 << PARAM1;
T1 = (uint32_t)T1 >> PARAM1;
}
+void OPPROTO op_shrl_T1_0(void)
+{
+ T1 = 0;
+}
+
void OPPROTO op_sarl_T1_im(void)
{
T1 = (int32_t)T1 >> PARAM1;
}
+void OPPROTO op_sarl_T1_0(void)
+{
+ T1 = (int32_t)T1 >> 31;
+}
+
void OPPROTO op_rorl_T1_im(void)
{
int shift;
T1 = ((uint32_t)T1 >> shift) | (T1 << (32 - shift));
}
+void OPPROTO op_rrxl_T1(void)
+{
+ T1 = ((uint32_t)T1 >> 1) | ((uint32_t)env->CF << 31);
+}
+
/* T1 based, set C flag */
void OPPROTO op_shll_T1_im_cc(void)
{
T1 = (uint32_t)T1 >> PARAM1;
}
+void OPPROTO op_shrl_T1_0_cc(void)
+{
+ env->CF = (T1 >> 31) & 1;
+ T1 = 0;
+}
+
void OPPROTO op_sarl_T1_im_cc(void)
{
env->CF = (T1 >> (PARAM1 - 1)) & 1;
T1 = (int32_t)T1 >> PARAM1;
}
+void OPPROTO op_sarl_T1_0_cc(void)
+{
+ env->CF = (T1 >> 31) & 1;
+ T1 = (int32_t)T1 >> 31;
+}
+
void OPPROTO op_rorl_T1_im_cc(void)
{
int shift;
T1 = ((uint32_t)T1 >> shift) | (T1 << (32 - shift));
}
+void OPPROTO op_rrxl_T1_cc(void)
+{
+ uint32_t c;
+ c = T1 & 1;
+ T1 = ((uint32_t)T1 >> 1) | ((uint32_t)env->CF << 31);
+ env->CF = c;
+}
+
/* T2 based */
void OPPROTO op_shll_T2_im(void)
{
T2 = (uint32_t)T2 >> PARAM1;
}
+void OPPROTO op_shrl_T2_0(void)
+{
+ T2 = 0;
+}
+
void OPPROTO op_sarl_T2_im(void)
{
T2 = (int32_t)T2 >> PARAM1;
}
+void OPPROTO op_sarl_T2_0(void)
+{
+ T2 = (int32_t)T2 >> 31;
+}
+
void OPPROTO op_rorl_T2_im(void)
{
int shift;
T2 = ((uint32_t)T2 >> shift) | (T2 << (32 - shift));
}
+void OPPROTO op_rrxl_T2(void)
+{
+ T2 = ((uint32_t)T2 >> 1) | ((uint32_t)env->CF << 31);
+}
+
/* T1 based, use T0 as shift count */
void OPPROTO op_shll_T1_T0(void)
FORCE_RET();
}
+/* misc */
+void OPPROTO op_clz_T0(void)
+{
+ int count;
+ for (count = 32; T0 > 0; count--)
+ T0 = T0 >> 1;
+ T0 = count;
+ FORCE_RET();
+}
+
+void OPPROTO op_sarl_T0_im(void)
+{
+ T0 = (int32_t)T0 >> PARAM1;
+}
+
+/* 16->32 Sign extend */
+void OPPROTO op_sxl_T0(void)
+{
+ T0 = (int16_t)T0;
+}
+
+void OPPROTO op_sxl_T1(void)
+{
+ T1 = (int16_t)T1;
+}
+
+#define SIGNBIT (uint32_t)0x80000000
+/* saturating arithmetic */
+void OPPROTO op_addl_T0_T1_setq(void)
+{
+ uint32_t res;
+
+ res = T0 + T1;
+ if (((res ^ T0) & SIGNBIT) && !((T0 ^ T1) & SIGNBIT))
+ env->QF = 1;
+
+ T0 = res;
+ FORCE_RET();
+}
+
+void OPPROTO op_addl_T0_T1_saturate(void)
+{
+ uint32_t res;
+
+ res = T0 + T1;
+ if (((res ^ T0) & SIGNBIT) && !((T0 ^ T1) & SIGNBIT)) {
+ env->QF = 1;
+ if (T0 & SIGNBIT)
+ T0 = 0x80000000;
+ else
+ T0 = 0x7fffffff;
+ }
+ else
+ T0 = res;
+
+ FORCE_RET();
+}
+
+void OPPROTO op_subl_T0_T1_saturate(void)
+{
+ uint32_t res;
+
+ res = T0 - T1;
+ if (((res ^ T0) & SIGNBIT) && ((T0 ^ T1) & SIGNBIT)) {
+ env->QF = 1;
+ if (T0 & SIGNBIT)
+ T0 = 0x8000000;
+ else
+ T0 = 0x7fffffff;
+ }
+ else
+ T0 = res;
+
+ FORCE_RET();
+}
+
+/* thumb shift by immediate */
+void OPPROTO op_shll_T0_im_thumb(void)
+{
+ int shift;
+ shift = PARAM1;
+ if (shift != 0) {
+ env->CF = (T1 >> (32 - shift)) & 1;
+ T0 = T0 << shift;
+ }
+ env->NZF = T0;
+ FORCE_RET();
+}
+
+void OPPROTO op_shrl_T0_im_thumb(void)
+{
+ int shift;
+
+ shift = PARAM1;
+ if (shift == 0) {
+ env->CF = 0;
+ T0 = 0;
+ } else {
+ env->CF = (T0 >> (shift - 1)) & 1;
+ T0 = T0 >> shift;
+ }
+ FORCE_RET();
+}
+
+void OPPROTO op_sarl_T0_im_thumb(void)
+{
+ int shift;
+
+ shift = PARAM1;
+ if (shift == 0) {
+ T0 = ((int32_t)T0) >> 31;
+ env->CF = T0 & 1;
+ } else {
+ env->CF = (T0 >> (shift - 1)) & 1;
+ T0 = ((int32_t)T0) >> shift;
+ }
+ env->NZF = T0;
+ FORCE_RET();
+}
+
/* exceptions */
void OPPROTO op_swi(void)
cpu_loop_exit();
}
-/* thread support */
+void OPPROTO op_debug(void)
+{
+ env->exception_index = EXCP_DEBUG;
+ cpu_loop_exit();
+}
+
+/* VFP support. We follow the convention used for VFP instrunctions:
+ Single precition routines have a "s" suffix, double precision a
+ "d" suffix. */
-spinlock_t global_cpu_lock = SPIN_LOCK_UNLOCKED;
+#define VFP_OP(name, p) void OPPROTO op_vfp_##name##p(void)
-void cpu_lock(void)
+#define VFP_BINOP(name) \
+VFP_OP(name, s) \
+{ \
+ FT0s = float32_ ## name (FT0s, FT1s, &env->vfp.fp_status); \
+} \
+VFP_OP(name, d) \
+{ \
+ FT0d = float64_ ## name (FT0d, FT1d, &env->vfp.fp_status); \
+}
+VFP_BINOP(add)
+VFP_BINOP(sub)
+VFP_BINOP(mul)
+VFP_BINOP(div)
+#undef VFP_BINOP
+
+#define VFP_HELPER(name) \
+VFP_OP(name, s) \
+{ \
+ do_vfp_##name##s(); \
+} \
+VFP_OP(name, d) \
+{ \
+ do_vfp_##name##d(); \
+}
+VFP_HELPER(abs)
+VFP_HELPER(sqrt)
+VFP_HELPER(cmp)
+VFP_HELPER(cmpe)
+#undef VFP_HELPER
+
+/* XXX: Will this do the right thing for NANs. Should invert the signbit
+ without looking at the rest of the value. */
+VFP_OP(neg, s)
+{
+ FT0s = float32_chs(FT0s);
+}
+
+VFP_OP(neg, d)
+{
+ FT0d = float64_chs(FT0d);
+}
+
+VFP_OP(F1_ld0, s)
+{
+ union {
+ uint32_t i;
+ float32 s;
+ } v;
+ v.i = 0;
+ FT1s = v.s;
+}
+
+VFP_OP(F1_ld0, d)
+{
+ union {
+ uint64_t i;
+ float64 d;
+ } v;
+ v.i = 0;
+ FT1d = v.d;
+}
+
+/* Helper routines to perform bitwise copies between float and int. */
+static inline float32 vfp_itos(uint32_t i)
+{
+ union {
+ uint32_t i;
+ float32 s;
+ } v;
+
+ v.i = i;
+ return v.s;
+}
+
+static inline uint32_t vfp_stoi(float32 s)
+{
+ union {
+ uint32_t i;
+ float32 s;
+ } v;
+
+ v.s = s;
+ return v.i;
+}
+
+/* Integer to float conversion. */
+VFP_OP(uito, s)
{
- spin_lock(&global_cpu_lock);
+ FT0s = uint32_to_float32(vfp_stoi(FT0s), &env->vfp.fp_status);
}
-void cpu_unlock(void)
+VFP_OP(uito, d)
{
- spin_unlock(&global_cpu_lock);
+ FT0d = uint32_to_float64(vfp_stoi(FT0s), &env->vfp.fp_status);
}
+VFP_OP(sito, s)
+{
+ FT0s = int32_to_float32(vfp_stoi(FT0s), &env->vfp.fp_status);
+}
+
+VFP_OP(sito, d)
+{
+ FT0d = int32_to_float64(vfp_stoi(FT0s), &env->vfp.fp_status);
+}
+
+/* Float to integer conversion. */
+VFP_OP(toui, s)
+{
+ FT0s = vfp_itos(float32_to_uint32(FT0s, &env->vfp.fp_status));
+}
+
+VFP_OP(toui, d)
+{
+ FT0s = vfp_itos(float64_to_uint32(FT0d, &env->vfp.fp_status));
+}
+
+VFP_OP(tosi, s)
+{
+ FT0s = vfp_itos(float32_to_int32(FT0s, &env->vfp.fp_status));
+}
+
+VFP_OP(tosi, d)
+{
+ FT0s = vfp_itos(float64_to_int32(FT0d, &env->vfp.fp_status));
+}
+
+/* TODO: Set rounding mode properly. */
+VFP_OP(touiz, s)
+{
+ FT0s = vfp_itos(float32_to_uint32_round_to_zero(FT0s, &env->vfp.fp_status));
+}
+
+VFP_OP(touiz, d)
+{
+ FT0s = vfp_itos(float64_to_uint32_round_to_zero(FT0d, &env->vfp.fp_status));
+}
+
+VFP_OP(tosiz, s)
+{
+ FT0s = vfp_itos(float32_to_int32_round_to_zero(FT0s, &env->vfp.fp_status));
+}
+
+VFP_OP(tosiz, d)
+{
+ FT0s = vfp_itos(float64_to_int32_round_to_zero(FT0d, &env->vfp.fp_status));
+}
+
+/* floating point conversion */
+VFP_OP(fcvtd, s)
+{
+ FT0d = float32_to_float64(FT0s, &env->vfp.fp_status);
+}
+
+VFP_OP(fcvts, d)
+{
+ FT0s = float64_to_float32(FT0d, &env->vfp.fp_status);
+}
+
+/* Get and Put values from registers. */
+VFP_OP(getreg_F0, d)
+{
+ FT0d = *(float64 *)((char *) env + PARAM1);
+}
+
+VFP_OP(getreg_F0, s)
+{
+ FT0s = *(float32 *)((char *) env + PARAM1);
+}
+
+VFP_OP(getreg_F1, d)
+{
+ FT1d = *(float64 *)((char *) env + PARAM1);
+}
+
+VFP_OP(getreg_F1, s)
+{
+ FT1s = *(float32 *)((char *) env + PARAM1);
+}
+
+VFP_OP(setreg_F0, d)
+{
+ *(float64 *)((char *) env + PARAM1) = FT0d;
+}
+
+VFP_OP(setreg_F0, s)
+{
+ *(float32 *)((char *) env + PARAM1) = FT0s;
+}
+
+void OPPROTO op_vfp_movl_T0_fpscr(void)
+{
+ do_vfp_get_fpscr ();
+}
+
+void OPPROTO op_vfp_movl_T0_fpscr_flags(void)
+{
+ T0 = env->vfp.fpscr & (0xf << 28);
+}
+
+void OPPROTO op_vfp_movl_fpscr_T0(void)
+{
+ do_vfp_set_fpscr();
+}
+
+/* Move between FT0s to T0 */
+void OPPROTO op_vfp_mrs(void)
+{
+ T0 = vfp_stoi(FT0s);
+}
+
+void OPPROTO op_vfp_msr(void)
+{
+ FT0s = vfp_itos(T0);
+}
+
+/* Move between FT0d and {T0,T1} */
+void OPPROTO op_vfp_mrrd(void)
+{
+ CPU_DoubleU u;
+
+ u.d = FT0d;
+ T0 = u.l.lower;
+ T1 = u.l.upper;
+}
+
+void OPPROTO op_vfp_mdrr(void)
+{
+ CPU_DoubleU u;
+
+ u.l.lower = T0;
+ u.l.upper = T1;
+ FT0d = u.d;
+}
+
+/* Floating point load/store. Address is in T1 */
+void OPPROTO op_vfp_lds(void)
+{
+ FT0s = ldfl((void *)T1);
+}
+
+void OPPROTO op_vfp_ldd(void)
+{
+ FT0d = ldfq((void *)T1);
+}
+
+void OPPROTO op_vfp_sts(void)
+{
+ stfl((void *)T1, FT0s);
+}
+
+void OPPROTO op_vfp_std(void)
+{
+ stfq((void *)T1, FT0d);
+}
projects / qemu / blobdiff