* ARM micro operations
*
* Copyright (c) 2003 Fabrice Bellard
+ * Copyright (c) 2005 CodeSourcery, LLC
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
T1 = PARAM1;
}
+void OPPROTO op_mov_CF_T1(void)
+{
+ env->CF = ((uint32_t)T1) >> 31;
+}
+
void OPPROTO op_movl_T2_im(void)
{
T2 = PARAM1;
cpu_loop_exit();
}
-/* thread support */
+void OPPROTO op_debug(void)
+{
+ env->exception_index = EXCP_DEBUG;
+ cpu_loop_exit();
+}
+
+/* VFP support. We follow the convention used for VFP instrunctions:
+ Single precition routines have a "s" suffix, double precision a
+ "d" suffix. */
+
+#define VFP_OP(name, p) void OPPROTO op_vfp_##name##p(void)
+
+#define VFP_BINOP(name) \
+VFP_OP(name, s) \
+{ \
+ FT0s = float32_ ## name (FT0s, FT1s, &env->vfp.fp_status); \
+} \
+VFP_OP(name, d) \
+{ \
+ FT0d = float64_ ## name (FT0d, FT1d, &env->vfp.fp_status); \
+}
+VFP_BINOP(add)
+VFP_BINOP(sub)
+VFP_BINOP(mul)
+VFP_BINOP(div)
+#undef VFP_BINOP
+
+#define VFP_HELPER(name) \
+VFP_OP(name, s) \
+{ \
+ do_vfp_##name##s(); \
+} \
+VFP_OP(name, d) \
+{ \
+ do_vfp_##name##d(); \
+}
+VFP_HELPER(abs)
+VFP_HELPER(sqrt)
+VFP_HELPER(cmp)
+VFP_HELPER(cmpe)
+#undef VFP_HELPER
+
+/* XXX: Will this do the right thing for NANs. Should invert the signbit
+ without looking at the rest of the value. */
+VFP_OP(neg, s)
+{
+ FT0s = float32_chs(FT0s);
+}
+
+VFP_OP(neg, d)
+{
+ FT0d = float64_chs(FT0d);
+}
-spinlock_t global_cpu_lock = SPIN_LOCK_UNLOCKED;
+VFP_OP(F1_ld0, s)
+{
+ union {
+ uint32_t i;
+ float32 s;
+ } v;
+ v.i = 0;
+ FT1s = v.s;
+}
-void cpu_lock(void)
+VFP_OP(F1_ld0, d)
{
- spin_lock(&global_cpu_lock);
+ union {
+ uint64_t i;
+ float64 d;
+ } v;
+ v.i = 0;
+ FT1d = v.d;
}
-void cpu_unlock(void)
+/* Helper routines to perform bitwise copies between float and int. */
+static inline float32 vfp_itos(uint32_t i)
{
- spin_unlock(&global_cpu_lock);
+ union {
+ uint32_t i;
+ float32 s;
+ } v;
+
+ v.i = i;
+ return v.s;
}
+static inline uint32_t vfp_stoi(float32 s)
+{
+ union {
+ uint32_t i;
+ float32 s;
+ } v;
+
+ v.s = s;
+ return v.i;
+}
+
+/* Integer to float conversion. */
+VFP_OP(uito, s)
+{
+ FT0s = uint32_to_float32(vfp_stoi(FT0s), &env->vfp.fp_status);
+}
+
+VFP_OP(uito, d)
+{
+ FT0d = uint32_to_float64(vfp_stoi(FT0s), &env->vfp.fp_status);
+}
+
+VFP_OP(sito, s)
+{
+ FT0s = int32_to_float32(vfp_stoi(FT0s), &env->vfp.fp_status);
+}
+
+VFP_OP(sito, d)
+{
+ FT0d = int32_to_float64(vfp_stoi(FT0s), &env->vfp.fp_status);
+}
+
+/* Float to integer conversion. */
+VFP_OP(toui, s)
+{
+ FT0s = vfp_itos(float32_to_uint32(FT0s, &env->vfp.fp_status));
+}
+
+VFP_OP(toui, d)
+{
+ FT0s = vfp_itos(float64_to_uint32(FT0d, &env->vfp.fp_status));
+}
+
+VFP_OP(tosi, s)
+{
+ FT0s = vfp_itos(float32_to_int32(FT0s, &env->vfp.fp_status));
+}
+
+VFP_OP(tosi, d)
+{
+ FT0s = vfp_itos(float64_to_int32(FT0d, &env->vfp.fp_status));
+}
+
+/* TODO: Set rounding mode properly. */
+VFP_OP(touiz, s)
+{
+ FT0s = vfp_itos(float32_to_uint32_round_to_zero(FT0s, &env->vfp.fp_status));
+}
+
+VFP_OP(touiz, d)
+{
+ FT0s = vfp_itos(float64_to_uint32_round_to_zero(FT0d, &env->vfp.fp_status));
+}
+
+VFP_OP(tosiz, s)
+{
+ FT0s = vfp_itos(float32_to_int32_round_to_zero(FT0s, &env->vfp.fp_status));
+}
+
+VFP_OP(tosiz, d)
+{
+ FT0s = vfp_itos(float64_to_int32_round_to_zero(FT0d, &env->vfp.fp_status));
+}
+
+/* floating point conversion */
+VFP_OP(fcvtd, s)
+{
+ FT0d = float32_to_float64(FT0s, &env->vfp.fp_status);
+}
+
+VFP_OP(fcvts, d)
+{
+ FT0s = float64_to_float32(FT0d, &env->vfp.fp_status);
+}
+
+/* Get and Put values from registers. */
+VFP_OP(getreg_F0, d)
+{
+ FT0d = *(float64 *)((char *) env + PARAM1);
+}
+
+VFP_OP(getreg_F0, s)
+{
+ FT0s = *(float32 *)((char *) env + PARAM1);
+}
+
+VFP_OP(getreg_F1, d)
+{
+ FT1d = *(float64 *)((char *) env + PARAM1);
+}
+
+VFP_OP(getreg_F1, s)
+{
+ FT1s = *(float32 *)((char *) env + PARAM1);
+}
+
+VFP_OP(setreg_F0, d)
+{
+ *(float64 *)((char *) env + PARAM1) = FT0d;
+}
+
+VFP_OP(setreg_F0, s)
+{
+ *(float32 *)((char *) env + PARAM1) = FT0s;
+}
+
+void OPPROTO op_vfp_movl_T0_fpscr(void)
+{
+ do_vfp_get_fpscr ();
+}
+
+void OPPROTO op_vfp_movl_T0_fpscr_flags(void)
+{
+ T0 = env->vfp.fpscr & (0xf << 28);
+}
+
+void OPPROTO op_vfp_movl_fpscr_T0(void)
+{
+ do_vfp_set_fpscr();
+}
+
+/* Move between FT0s to T0 */
+void OPPROTO op_vfp_mrs(void)
+{
+ T0 = vfp_stoi(FT0s);
+}
+
+void OPPROTO op_vfp_msr(void)
+{
+ FT0s = vfp_itos(T0);
+}
+
+/* Move between FT0d and {T0,T1} */
+void OPPROTO op_vfp_mrrd(void)
+{
+ CPU_DoubleU u;
+
+ u.d = FT0d;
+ T0 = u.l.lower;
+ T1 = u.l.upper;
+}
+
+void OPPROTO op_vfp_mdrr(void)
+{
+ CPU_DoubleU u;
+
+ u.l.lower = T0;
+ u.l.upper = T1;
+ FT0d = u.d;
+}
+
+/* Floating point load/store. Address is in T1 */
+void OPPROTO op_vfp_lds(void)
+{
+ FT0s = ldfl((void *)T1);
+}
+
+void OPPROTO op_vfp_ldd(void)
+{
+ FT0d = ldfq((void *)T1);
+}
+
+void OPPROTO op_vfp_sts(void)
+{
+ stfl((void *)T1, FT0s);
+}
+
+void OPPROTO op_vfp_std(void)
+{
+ stfq((void *)T1, FT0d);
+}
projects / qemu / blobdiff