/*
* m68k translation
- *
+ *
* Copyright (c) 2005-2007 CodeSourcery
* Written by Paul Brook
*
#include "cpu.h"
#include "exec-all.h"
#include "disas.h"
+#include "tcg-op.h"
#include "m68k-qreg.h"
//#define DEBUG_DISPATCH 1
/* internal defines */
typedef struct DisasContext {
+ CPUM68KState *env;
+ target_ulong insn_pc; /* Start of the current instruction. */
target_ulong pc;
int is_jmp;
int cc_op;
uint32_t fpcr;
struct TranslationBlock *tb;
int singlestep_enabled;
+ int is_mem;
} DisasContext;
#define DISAS_JUMP_NEXT 4
static void *gen_throws_exception;
#define gen_last_qop NULL
-static uint16_t *gen_opc_ptr;
-static uint32_t *gen_opparam_ptr;
extern FILE *logfile;
extern int loglevel;
-enum {
-#define DEF(s, n, copy_size) INDEX_op_ ## s,
-#include "opc.h"
-#undef DEF
- NB_OPS,
-};
-
-#include "gen-op.h"
-
#if defined(CONFIG_USER_ONLY)
#define gen_st(s, name, addr, val) gen_op_st##name##_raw(addr, val)
#define gen_ld(s, name, val, addr) gen_op_ld##name##_raw(val, addr)
#define AREG(insn, pos) (((insn >> pos) & 7) + QREG_A0)
#define FREG(insn, pos) (((insn >> pos) & 7) + QREG_F0)
-#define M68K_INSN_CF_A (1 << 0)
-#define M68K_INSN_CF_B (1 << 1)
-#define M68K_INSN_CF_C (1 << 2)
-#define M68K_INSN_CF_MAC (1 << 3)
-#define M68K_INSN_CF_EMAC (1 << 4)
-#define M68K_INSN_CF_FPU (1 << 5)
-
-struct m68k_def_t {
- const char * name;
- uint32_t insns;
-};
-
-static m68k_def_t m68k_cpu_defs[] = {
- {"m5206", M68K_INSN_CF_A},
- {"cfv4e", M68K_INSN_CF_A | M68K_INSN_CF_B | M68K_INSN_CF_C
- | M68K_INSN_CF_MAC | M68K_INSN_CF_EMAC | M68K_INSN_CF_FPU},
- {NULL, 0},
-};
-
typedef void (*disas_proc)(DisasContext *, uint16_t);
#ifdef DEBUG_DISPATCH
static inline int gen_load(DisasContext * s, int opsize, int addr, int sign)
{
int tmp;
+ s->is_mem = 1;
switch(opsize) {
case OS_BYTE:
tmp = gen_new_qreg(QMODE_I32);
/* Generate a store. */
static inline void gen_store(DisasContext *s, int opsize, int addr, int val)
{
+ s->is_mem = 1;
switch(opsize) {
case OS_BYTE:
gen_st(s, 8, addr, val);
}
}
+/* Read a 32-bit immediate constant. */
+static inline uint32_t read_im32(DisasContext *s)
+{
+ uint32_t im;
+ im = ((uint32_t)lduw_code(s->pc)) << 16;
+ s->pc += 2;
+ im |= lduw_code(s->pc);
+ s->pc += 2;
+ return im;
+}
+
+/* Calculate and address index. */
+static int gen_addr_index(uint16_t ext, int tmp)
+{
+ int add;
+ int scale;
+
+ add = (ext & 0x8000) ? AREG(ext, 12) : DREG(ext, 12);
+ if ((ext & 0x800) == 0) {
+ gen_op_ext16s32(tmp, add);
+ add = tmp;
+ }
+ scale = (ext >> 9) & 3;
+ if (scale != 0) {
+ gen_op_shl32(tmp, add, gen_im32(scale));
+ add = tmp;
+ }
+ return add;
+}
+
/* Handle a base + index + displacement effective addresss. A base of
-1 means pc-relative. */
static int gen_lea_indexed(DisasContext *s, int opsize, int base)
{
- int scale;
uint32_t offset;
uint16_t ext;
int add;
int tmp;
+ uint32_t bd, od;
offset = s->pc;
ext = lduw_code(s->pc);
s->pc += 2;
- tmp = ((ext >> 12) & 7) + ((ext & 0x8000) ? QREG_A0 : QREG_D0);
- /* ??? Check W/L bit. */
- scale = (ext >> 9) & 3;
- if (scale == 0) {
- add = tmp;
- } else {
- add = gen_new_qreg(QMODE_I32);
- gen_op_shl32(add, tmp, gen_im32(scale));
- }
- tmp = gen_new_qreg(QMODE_I32);
- if (base != -1) {
- gen_op_add32(tmp, base, gen_im32((int8_t)ext));
- gen_op_add32(tmp, tmp, add);
+
+ if ((ext & 0x800) == 0 && !m68k_feature(s->env, M68K_FEATURE_WORD_INDEX))
+ return -1;
+
+ if (ext & 0x100) {
+ /* full extension word format */
+ if (!m68k_feature(s->env, M68K_FEATURE_EXT_FULL))
+ return -1;
+
+ if ((ext & 0x30) > 0x10) {
+ /* base displacement */
+ if ((ext & 0x30) == 0x20) {
+ bd = (int16_t)lduw_code(s->pc);
+ s->pc += 2;
+ } else {
+ bd = read_im32(s);
+ }
+ } else {
+ bd = 0;
+ }
+ tmp = gen_new_qreg(QMODE_I32);
+ if ((ext & 0x44) == 0) {
+ /* pre-index */
+ add = gen_addr_index(ext, tmp);
+ } else {
+ add = QREG_NULL;
+ }
+ if ((ext & 0x80) == 0) {
+ /* base not suppressed */
+ if (base == -1) {
+ base = gen_im32(offset + bd);
+ bd = 0;
+ }
+ if (add) {
+ gen_op_add32(tmp, add, base);
+ add = tmp;
+ } else {
+ add = base;
+ }
+ }
+ if (add) {
+ if (bd != 0) {
+ gen_op_add32(tmp, add, gen_im32(bd));
+ add = tmp;
+ }
+ } else {
+ add = gen_im32(bd);
+ }
+ if ((ext & 3) != 0) {
+ /* memory indirect */
+ base = gen_load(s, OS_LONG, add, 0);
+ if ((ext & 0x44) == 4) {
+ add = gen_addr_index(ext, tmp);
+ gen_op_add32(tmp, add, base);
+ add = tmp;
+ } else {
+ add = base;
+ }
+ if ((ext & 3) > 1) {
+ /* outer displacement */
+ if ((ext & 3) == 2) {
+ od = (int16_t)lduw_code(s->pc);
+ s->pc += 2;
+ } else {
+ od = read_im32(s);
+ }
+ } else {
+ od = 0;
+ }
+ if (od != 0) {
+ gen_op_add32(tmp, add, gen_im32(od));
+ add = tmp;
+ }
+ }
} else {
- gen_op_add32(tmp, add, gen_im32(offset + (int8_t)ext));
+ /* brief extension word format */
+ tmp = gen_new_qreg(QMODE_I32);
+ add = gen_addr_index(ext, tmp);
+ if (base != -1) {
+ gen_op_add32(tmp, add, base);
+ if ((int8_t)ext)
+ gen_op_add32(tmp, tmp, gen_im32((int8_t)ext));
+ } else {
+ gen_op_add32(tmp, add, gen_im32(offset + (int8_t)ext));
+ }
+ add = tmp;
}
- return tmp;
-}
-
-/* Read a 32-bit immediate constant. */
-static inline uint32_t read_im32(DisasContext *s)
-{
- uint32_t im;
- im = ((uint32_t)lduw_code(s->pc)) << 16;
- s->pc += 2;
- im |= lduw_code(s->pc);
- s->pc += 2;
- return im;
+ return add;
}
-
/* Update the CPU env CC_OP state. */
static inline void gen_flush_cc_op(DisasContext *s)
{
{
if (s->cc_op == CC_OP_FLAGS)
return;
- gen_op_flush_flags(s->cc_op);
+ gen_flush_cc_op(s);
+ gen_op_flush_flags();
s->cc_op = CC_OP_FLAGS;
}
switch ((insn >> 3) & 7) {
case 0: /* Data register direct. */
case 1: /* Address register direct. */
- /* ??? generate bad addressing mode fault. */
- qemu_assert(0, "invalid addressing mode");
+ return -1;
case 2: /* Indirect register */
case 3: /* Indirect postincrement. */
reg += QREG_A0;
return gen_lea_indexed(s, opsize, -1);
case 4: /* Immediate. */
default:
- /* ??? generate bad addressing mode fault. */
- qemu_assert(0, "invalid addressing mode");
+ return -1;
}
}
/* Should never happen. */
tmp = *addrp;
} else {
tmp = gen_lea(s, insn, opsize);
+ if (tmp == -1)
+ return -1;
if (addrp)
*addrp = tmp;
}
tmp = *addrp;
} else {
tmp = gen_lea(s, insn, opsize);
+ if (tmp == -1)
+ return -1;
if (addrp)
*addrp = tmp;
}
}
return gen_im32(offset);
default:
- qemu_assert(0, "invalid addressing mode");
+ return -1;
}
}
/* Should never happen. */
gen_flush_flags(s);
switch (cond) {
case 0: /* T */
- gen_op_jmp(l1);
+ gen_op_jmp_im(l1);
break;
case 1: /* F */
break;
gen_op_xor32(tmp, tmp, QREG_CC_DEST);
gen_op_and32(tmp, tmp, gen_im32(CCF_V));
gen_op_jmp_nz32(tmp, l2);
- gen_op_jmp(l1);
+ gen_op_jmp_im(l1);
gen_set_label(l2);
}
break;
gen_op_raise_exception(nr);
}
+static inline void gen_addr_fault(DisasContext *s)
+{
+ gen_exception(s, s->insn_pc, EXCP_ADDRESS);
+}
+
+#define SRC_EA(result, opsize, val, addrp) do { \
+ result = gen_ea(s, insn, opsize, val, addrp); \
+ if (result == -1) { \
+ gen_addr_fault(s); \
+ return; \
+ } \
+ } while (0)
+
+#define DEST_EA(insn, opsize, val, addrp) do { \
+ int ea_result = gen_ea(s, insn, opsize, val, addrp); \
+ if (ea_result == -1) { \
+ gen_addr_fault(s); \
+ return; \
+ } \
+ } while (0)
+
/* Generate a jump to an immediate address. */
static void gen_jmp_tb(DisasContext *s, int n, uint32_t dest)
{
gen_exception(s, dest, EXCP_DEBUG);
} else if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) ||
(s->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {
- gen_op_goto_tb(0, n, (long)tb);
+ tcg_gen_goto_tb(n);
gen_op_mov32(QREG_PC, gen_im32(dest));
- gen_op_mov32(QREG_T0, gen_im32((long)tb + n));
- gen_op_exit_tb();
+ tcg_gen_exit_tb((long)tb + n);
} else {
gen_jmp(s, gen_im32(dest));
- gen_op_mov32(QREG_T0, gen_im32(0));
- gen_op_exit_tb();
+ tcg_gen_exit_tb(0);
}
s->is_jmp = DISAS_TB_JUMP;
}
gen_op_ext16s32(tmp, reg);
else
gen_op_ext16u32(tmp, reg);
- src = gen_ea(s, insn, OS_WORD, sign ? -1 : 0, NULL);
+ SRC_EA(src, OS_WORD, sign ? -1 : 0, NULL);
gen_op_mul32(tmp, tmp, src);
gen_op_mov32(reg, tmp);
/* Unlike m68k, coldfire always clears the overflow bit. */
} else {
gen_op_ext16u32(QREG_DIV1, reg);
}
- src = gen_ea(s, insn, OS_WORD, sign ? -1 : 0, NULL);
+ SRC_EA(src, OS_WORD, sign ? -1 : 0, NULL);
gen_op_mov32(QREG_DIV2, src);
if (sign) {
gen_op_divs(1);
num = DREG(ext, 12);
reg = DREG(ext, 0);
gen_op_mov32(QREG_DIV1, num);
- den = gen_ea(s, insn, OS_LONG, 0, NULL);
+ SRC_EA(den, OS_LONG, 0, NULL);
gen_op_mov32(QREG_DIV2, den);
if (ext & 0x0800) {
gen_op_divs(2);
reg = DREG(insn, 9);
dest = gen_new_qreg(QMODE_I32);
if (insn & 0x100) {
- tmp = gen_ea(s, insn, OS_LONG, 0, &addr);
+ SRC_EA(tmp, OS_LONG, 0, &addr);
src = reg;
} else {
tmp = reg;
- src = gen_ea(s, insn, OS_LONG, 0, NULL);
+ SRC_EA(src, OS_LONG, 0, NULL);
}
if (add) {
gen_op_add32(dest, tmp, src);
}
gen_op_update_cc_add(dest, src);
if (insn & 0x100) {
- gen_ea(s, insn, OS_LONG, dest, &addr);
+ DEST_EA(insn, OS_LONG, dest, &addr);
} else {
gen_op_mov32(reg, dest);
}
else
opsize = OS_LONG;
op = (insn >> 6) & 3;
- src1 = gen_ea(s, insn, opsize, 0, op ? &addr: NULL);
+ SRC_EA(src1, opsize, 0, op ? &addr: NULL);
src2 = DREG(insn, 9);
dest = gen_new_qreg(QMODE_I32);
break;
}
if (op)
- gen_ea(s, insn, opsize, dest, &addr);
+ DEST_EA(insn, opsize, dest, &addr);
}
DISAS_INSN(sats)
mask = lduw_code(s->pc);
s->pc += 2;
tmp = gen_lea(s, insn, OS_LONG);
+ if (tmp == -1) {
+ gen_addr_fault(s);
+ return;
+ }
addr = gen_new_qreg(QMODE_I32);
gen_op_mov32(addr, tmp);
is_load = ((insn & 0x0400) != 0);
return;
}
- src1 = gen_ea(s, insn, opsize, 0, op ? &addr: NULL);
+ SRC_EA(src1, opsize, 0, op ? &addr: NULL);
gen_flush_flags(s);
tmp = gen_new_qreg(QMODE_I32);
break;
}
if (op)
- gen_ea(s, insn, opsize, dest, &addr);
+ DEST_EA(insn, opsize, dest, &addr);
}
DISAS_INSN(arith_im)
int addr;
op = (insn >> 9) & 7;
- src1 = gen_ea(s, insn, OS_LONG, 0, (op == 6) ? NULL : &addr);
+ SRC_EA(src1, OS_LONG, 0, (op == 6) ? NULL : &addr);
src2 = gen_im32(read_im32(s));
dest = gen_new_qreg(QMODE_I32);
switch (op) {
abort();
}
if (op != 6) {
- gen_ea(s, insn, OS_LONG, dest, &addr);
+ DEST_EA(insn, OS_LONG, dest, &addr);
}
}
default:
abort();
}
- src = gen_ea(s, insn, opsize, -1, NULL);
+ SRC_EA(src, opsize, -1, NULL);
op = (insn >> 6) & 7;
if (op == 1) {
/* movea */
/* normal move */
uint16_t dest_ea;
dest_ea = ((insn >> 9) & 7) | (op << 3);
- gen_ea(s, dest_ea, opsize, src, NULL);
+ DEST_EA(dest_ea, opsize, src, NULL);
/* This will be correct because loads sign extend. */
gen_logic_cc(s, src);
}
reg = AREG(insn, 9);
tmp = gen_lea(s, insn, OS_LONG);
+ if (tmp == -1) {
+ gen_addr_fault(s);
+ return;
+ }
gen_op_mov32(reg, tmp);
}
default:
abort();
}
- gen_ea (s, insn, opsize, gen_im32(0), NULL);
+ DEST_EA(insn, opsize, gen_im32(0), NULL);
gen_logic_cc(s, gen_im32(0));
}
gen_op_logic_cc(gen_im32(val & 0xf));
gen_op_update_xflag_tst(gen_im32((val & 0x10) >> 4));
if (!ccr_only) {
- gen_op_mov32(QREG_SR, gen_im32(val & 0xff00));
+ gen_op_set_sr(gen_im32(val & 0xff00));
}
}
gen_op_and32(src1, src1, gen_im32(1));
gen_op_update_xflag_tst(src1);
if (!ccr_only) {
- gen_op_and32(QREG_SR, reg, gen_im32(0xff00));
+ gen_op_set_sr(reg);
}
}
else if ((insn & 0x3f) == 0x3c)
int tmp;
tmp = gen_lea(s, insn, OS_LONG);
+ if (tmp == -1) {
+ gen_addr_fault(s);
+ return;
+ }
gen_push(s, tmp);
}
default:
abort();
}
- tmp = gen_ea(s, insn, opsize, -1, NULL);
+ SRC_EA(tmp, opsize, -1, NULL);
gen_logic_cc(s, tmp);
}
int addr;
dest = gen_new_qreg(QMODE_I32);
- src1 = gen_ea(s, insn, OS_BYTE, -1, &addr);
+ SRC_EA(src1, OS_BYTE, -1, &addr);
gen_logic_cc(s, src1);
gen_op_or32(dest, src1, gen_im32(0x80));
- gen_ea(s, insn, OS_BYTE, dest, &addr);
+ DEST_EA(insn, OS_BYTE, dest, &addr);
}
DISAS_INSN(mull)
return;
}
reg = DREG(ext, 12);
- src1 = gen_ea(s, insn, OS_LONG, 0, NULL);
+ SRC_EA(src1, OS_LONG, 0, NULL);
dest = gen_new_qreg(QMODE_I32);
gen_op_mul32(dest, src1, reg);
gen_op_mov32(reg, dest);
/* Load the target address first to ensure correct exception
behavior. */
tmp = gen_lea(s, insn, OS_LONG);
+ if (tmp == -1) {
+ gen_addr_fault(s);
+ return;
+ }
if ((insn & 0x40) == 0) {
/* jsr */
gen_push(s, gen_im32(s->pc));
int val;
int addr;
- src1 = gen_ea(s, insn, OS_LONG, 0, &addr);
+ SRC_EA(src1, OS_LONG, 0, &addr);
val = (insn >> 9) & 7;
if (val == 0)
val = 8;
}
gen_op_update_cc_add(dest, src2);
}
- gen_ea(s, insn, OS_LONG, dest, &addr);
+ DEST_EA(insn, OS_LONG, dest, &addr);
}
DISAS_INSN(tpf)
uint32_t base;
int op;
int l1;
-
+
base = s->pc;
op = (insn >> 8) & 0xf;
offset = (int8_t)insn;
opsize = OS_WORD;
else
opsize = OS_BYTE;
- src = gen_ea(s, insn, opsize, (insn & 0x80) ? 0 : -1, NULL);
+ SRC_EA(src, opsize, (insn & 0x80) ? 0 : -1, NULL);
reg = DREG(insn, 9);
gen_op_mov32(reg, src);
gen_logic_cc(s, src);
reg = DREG(insn, 9);
dest = gen_new_qreg(QMODE_I32);
if (insn & 0x100) {
- src = gen_ea(s, insn, OS_LONG, 0, &addr);
+ SRC_EA(src, OS_LONG, 0, &addr);
gen_op_or32(dest, src, reg);
- gen_ea(s, insn, OS_LONG, dest, &addr);
+ DEST_EA(insn, OS_LONG, dest, &addr);
} else {
- src = gen_ea(s, insn, OS_LONG, 0, NULL);
+ SRC_EA(src, OS_LONG, 0, NULL);
gen_op_or32(dest, src, reg);
gen_op_mov32(reg, dest);
}
int src;
int reg;
- src = gen_ea(s, insn, OS_LONG, 0, NULL);
+ SRC_EA(src, OS_LONG, 0, NULL);
reg = AREG(insn, 9);
gen_op_sub32(reg, reg, src);
}
val = -1;
src = gen_im32(val);
gen_logic_cc(s, src);
- gen_ea(s, insn, OS_LONG, src, NULL);
+ DEST_EA(insn, OS_LONG, src, NULL);
}
DISAS_INSN(cmp)
default:
abort();
}
- src = gen_ea(s, insn, opsize, -1, NULL);
+ SRC_EA(src, opsize, -1, NULL);
reg = DREG(insn, 9);
dest = gen_new_qreg(QMODE_I32);
gen_op_sub32(dest, reg, src);
} else {
opsize = OS_WORD;
}
- src = gen_ea(s, insn, opsize, -1, NULL);
+ SRC_EA(src, opsize, -1, NULL);
reg = AREG(insn, 9);
dest = gen_new_qreg(QMODE_I32);
gen_op_sub32(dest, reg, src);
int dest;
int addr;
- src = gen_ea(s, insn, OS_LONG, 0, &addr);
+ SRC_EA(src, OS_LONG, 0, &addr);
reg = DREG(insn, 9);
dest = gen_new_qreg(QMODE_I32);
gen_op_xor32(dest, src, reg);
gen_logic_cc(s, dest);
- gen_ea(s, insn, OS_LONG, dest, &addr);
+ DEST_EA(insn, OS_LONG, dest, &addr);
}
DISAS_INSN(and)
reg = DREG(insn, 9);
dest = gen_new_qreg(QMODE_I32);
if (insn & 0x100) {
- src = gen_ea(s, insn, OS_LONG, 0, &addr);
+ SRC_EA(src, OS_LONG, 0, &addr);
gen_op_and32(dest, src, reg);
- gen_ea(s, insn, OS_LONG, dest, &addr);
+ DEST_EA(insn, OS_LONG, dest, &addr);
} else {
- src = gen_ea(s, insn, OS_LONG, 0, NULL);
+ SRC_EA(src, OS_LONG, 0, NULL);
gen_op_and32(dest, src, reg);
gen_op_mov32(reg, dest);
}
int src;
int reg;
- src = gen_ea(s, insn, OS_LONG, 0, NULL);
+ SRC_EA(src, OS_LONG, 0, NULL);
reg = AREG(insn, 9);
gen_op_add32(reg, reg, src);
}
DISAS_INSN(ff1)
{
- cpu_abort(NULL, "Unimplemented insn: ff1");
+ int reg;
+ reg = DREG(insn, 0);
+ gen_logic_cc(s, reg);
+ gen_op_ff1(reg, reg);
}
static int gen_get_sr(DisasContext *s)
DISAS_INSN(halt)
{
- gen_flush_cc_op(s);
gen_jmp(s, gen_im32(s->pc));
gen_op_halt();
}
s->pc += 2;
gen_set_sr_im(s, ext, 0);
- disas_halt(s, insn);
+ gen_jmp(s, gen_im32(s->pc));
+ gen_op_stop();
}
DISAS_INSN(rte)
default:
goto undef;
}
- gen_ea(s, insn, opsize, res, NULL);
+ DEST_EA(insn, opsize, res, NULL);
return;
case 4: /* fmove to control register. */
switch ((ext >> 10) & 7) {
(ext >> 10) & 7);
goto undef;
}
- gen_ea(s, insn, OS_LONG, res, NULL);
+ DEST_EA(insn, OS_LONG, res, NULL);
break;
- case 6: /* fmovem */
+ case 6: /* fmovem */
case 7:
{
int addr;
if ((ext & 0x1f00) != 0x1000 || (ext & 0xff) == 0)
goto undef;
src = gen_lea(s, insn, OS_LONG);
+ if (src == -1) {
+ gen_addr_fault(s);
+ return;
+ }
addr = gen_new_qreg(QMODE_I32);
gen_op_mov32(addr, src);
mask = 0x80;
dest = QREG_F0;
while (mask) {
if (ext & mask) {
+ s->is_mem = 1;
if (ext & (1 << 13)) {
/* store */
gen_st(s, f64, addr, dest);
default:
goto undef;
}
- tmp = gen_ea(s, insn, opsize, -1, NULL);
+ SRC_EA(tmp, opsize, -1, NULL);
if (opsize == OS_DOUBLE) {
src = tmp;
} else {
tmp = gen_new_qreg(QMODE_F32);
gen_op_f64_to_f32(tmp, res);
gen_op_f32_to_f64(res, tmp);
- }
+ }
gen_op_fp_result(res);
if (dest) {
gen_op_movf64(dest, res);
qemu_assert(0, "FSAVE not implemented");
}
+static inline int gen_mac_extract_word(DisasContext *s, int val, int upper)
+{
+ int tmp = gen_new_qreg(QMODE_I32);
+ if (s->env->macsr & MACSR_FI) {
+ if (upper)
+ gen_op_and32(tmp, val, gen_im32(0xffff0000));
+ else
+ gen_op_shl32(tmp, val, gen_im32(16));
+ } else if (s->env->macsr & MACSR_SU) {
+ if (upper)
+ gen_op_sar32(tmp, val, gen_im32(16));
+ else
+ gen_op_ext16s32(tmp, val);
+ } else {
+ if (upper)
+ gen_op_shr32(tmp, val, gen_im32(16));
+ else
+ gen_op_ext16u32(tmp, val);
+ }
+ return tmp;
+}
+
+DISAS_INSN(mac)
+{
+ int rx;
+ int ry;
+ uint16_t ext;
+ int acc;
+ int l1;
+ int tmp;
+ int addr;
+ int loadval;
+ int dual;
+ int saved_flags = -1;
+
+ ext = lduw_code(s->pc);
+ s->pc += 2;
+
+ acc = ((insn >> 7) & 1) | ((ext >> 3) & 2);
+ dual = ((insn & 0x30) != 0 && (ext & 3) != 0);
+ if (dual && !m68k_feature(s->env, M68K_FEATURE_CF_EMAC_B)) {
+ disas_undef(s, insn);
+ return;
+ }
+ if (insn & 0x30) {
+ /* MAC with load. */
+ tmp = gen_lea(s, insn, OS_LONG);
+ addr = gen_new_qreg(QMODE_I32);
+ gen_op_and32(addr, tmp, QREG_MAC_MASK);
+ /* Load the value now to ensure correct exception behavior.
+ Perform writeback after reading the MAC inputs. */
+ loadval = gen_load(s, OS_LONG, addr, 0);
+
+ acc ^= 1;
+ rx = (ext & 0x8000) ? AREG(ext, 12) : DREG(insn, 12);
+ ry = (ext & 8) ? AREG(ext, 0) : DREG(ext, 0);
+ } else {
+ loadval = addr = -1;
+ rx = (insn & 0x40) ? AREG(insn, 9) : DREG(insn, 9);
+ ry = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0);
+ }
+
+ gen_op_mac_clear_flags();
+ l1 = -1;
+ if ((s->env->macsr & MACSR_OMC) != 0 && !dual) {
+ /* Skip the multiply if we know we will ignore it. */
+ l1 = gen_new_label();
+ tmp = gen_new_qreg(QMODE_I32);
+ gen_op_and32(tmp, QREG_MACSR, gen_im32(1 << (acc + 8)));
+ gen_op_jmp_nz32(tmp, l1);
+ }
+
+ if ((ext & 0x0800) == 0) {
+ /* Word. */
+ rx = gen_mac_extract_word(s, rx, (ext & 0x80) != 0);
+ ry = gen_mac_extract_word(s, ry, (ext & 0x40) != 0);
+ }
+ if (s->env->macsr & MACSR_FI) {
+ gen_op_macmulf(rx, ry);
+ } else {
+ if (s->env->macsr & MACSR_SU)
+ gen_op_macmuls(rx, ry);
+ else
+ gen_op_macmulu(rx, ry);
+ switch ((ext >> 9) & 3) {
+ case 1:
+ gen_op_macshl();
+ break;
+ case 3:
+ gen_op_macshr();
+ break;
+ }
+ }
+
+ if (dual) {
+ /* Save the overflow flag from the multiply. */
+ saved_flags = gen_new_qreg(QMODE_I32);
+ gen_op_mov32(saved_flags, QREG_MACSR);
+ }
+
+ if ((s->env->macsr & MACSR_OMC) != 0 && dual) {
+ /* Skip the accumulate if the value is already saturated. */
+ l1 = gen_new_label();
+ tmp = gen_new_qreg(QMODE_I32);
+ gen_op_and32(tmp, QREG_MACSR, gen_im32(MACSR_PAV0 << acc));
+ gen_op_jmp_nz32(tmp, l1);
+ }
+
+ if (insn & 0x100)
+ gen_op_macsub(acc);
+ else
+ gen_op_macadd(acc);
+
+ if (s->env->macsr & MACSR_FI)
+ gen_op_macsatf(acc);
+ else if (s->env->macsr & MACSR_SU)
+ gen_op_macsats(acc);
+ else
+ gen_op_macsatu(acc);
+
+ if (l1 != -1)
+ gen_set_label(l1);
+
+ if (dual) {
+ /* Dual accumulate variant. */
+ acc = (ext >> 2) & 3;
+ /* Restore the overflow flag from the multiplier. */
+ gen_op_mov32(QREG_MACSR, saved_flags);
+ if ((s->env->macsr & MACSR_OMC) != 0) {
+ /* Skip the accumulate if the value is already saturated. */
+ l1 = gen_new_label();
+ tmp = gen_new_qreg(QMODE_I32);
+ gen_op_and32(tmp, QREG_MACSR, gen_im32(MACSR_PAV0 << acc));
+ gen_op_jmp_nz32(tmp, l1);
+ }
+ if (ext & 2)
+ gen_op_macsub(acc);
+ else
+ gen_op_macadd(acc);
+ if (s->env->macsr & MACSR_FI)
+ gen_op_macsatf(acc);
+ else if (s->env->macsr & MACSR_SU)
+ gen_op_macsats(acc);
+ else
+ gen_op_macsatu(acc);
+ if (l1 != -1)
+ gen_set_label(l1);
+ }
+ gen_op_mac_set_flags(acc);
+
+ if (insn & 0x30) {
+ int rw;
+ rw = (insn & 0x40) ? AREG(insn, 9) : DREG(insn, 9);
+ gen_op_mov32(rw, loadval);
+ /* FIXME: Should address writeback happen with the masked or
+ unmasked value? */
+ switch ((insn >> 3) & 7) {
+ case 3: /* Post-increment. */
+ gen_op_add32(AREG(insn, 0), addr, gen_im32(4));
+ break;
+ case 4: /* Pre-decrement. */
+ gen_op_mov32(AREG(insn, 0), addr);
+ }
+ }
+}
+
+DISAS_INSN(from_mac)
+{
+ int rx;
+ int acc;
+
+ rx = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0);
+ acc = (insn >> 9) & 3;
+ if (s->env->macsr & MACSR_FI) {
+ gen_op_get_macf(rx, acc);
+ } else if ((s->env->macsr & MACSR_OMC) == 0) {
+ gen_op_get_maci(rx, acc);
+ } else if (s->env->macsr & MACSR_SU) {
+ gen_op_get_macs(rx, acc);
+ } else {
+ gen_op_get_macu(rx, acc);
+ }
+ if (insn & 0x40)
+ gen_op_clear_mac(acc);
+}
+
+DISAS_INSN(move_mac)
+{
+ int src;
+ int dest;
+ src = insn & 3;
+ dest = (insn >> 9) & 3;
+ gen_op_move_mac(dest, src);
+ gen_op_mac_clear_flags();
+ gen_op_mac_set_flags(dest);
+}
+
+DISAS_INSN(from_macsr)
+{
+ int reg;
+
+ reg = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0);
+ gen_op_mov32(reg, QREG_MACSR);
+}
+
+DISAS_INSN(from_mask)
+{
+ int reg;
+ reg = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0);
+ gen_op_mov32(reg, QREG_MAC_MASK);
+}
+
+DISAS_INSN(from_mext)
+{
+ int reg;
+ int acc;
+ reg = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0);
+ acc = (insn & 0x400) ? 2 : 0;
+ if (s->env->macsr & MACSR_FI)
+ gen_op_get_mac_extf(reg, acc);
+ else
+ gen_op_get_mac_exti(reg, acc);
+}
+
+DISAS_INSN(macsr_to_ccr)
+{
+ gen_op_mov32(QREG_CC_X, gen_im32(0));
+ gen_op_and32(QREG_CC_DEST, QREG_MACSR, gen_im32(0xf));
+ s->cc_op = CC_OP_FLAGS;
+}
+
+DISAS_INSN(to_mac)
+{
+ int acc;
+ int val;
+ acc = (insn >>9) & 3;
+ SRC_EA(val, OS_LONG, 0, NULL);
+ if (s->env->macsr & MACSR_FI) {
+ gen_op_set_macf(val, acc);
+ } else if (s->env->macsr & MACSR_SU) {
+ gen_op_set_macs(val, acc);
+ } else {
+ gen_op_set_macu(val, acc);
+ }
+ gen_op_mac_clear_flags();
+ gen_op_mac_set_flags(acc);
+}
+
+DISAS_INSN(to_macsr)
+{
+ int val;
+ SRC_EA(val, OS_LONG, 0, NULL);
+ gen_op_set_macsr(val);
+ gen_lookup_tb(s);
+}
+
+DISAS_INSN(to_mask)
+{
+ int val;
+ SRC_EA(val, OS_LONG, 0, NULL);
+ gen_op_or32(QREG_MAC_MASK, val, gen_im32(0xffff0000));
+}
+
+DISAS_INSN(to_mext)
+{
+ int val;
+ int acc;
+ SRC_EA(val, OS_LONG, 0, NULL);
+ acc = (insn & 0x400) ? 2 : 0;
+ if (s->env->macsr & MACSR_FI)
+ gen_op_set_mac_extf(val, acc);
+ else if (s->env->macsr & MACSR_SU)
+ gen_op_set_mac_exts(val, acc);
+ else
+ gen_op_set_mac_extu(val, acc);
+}
+
static disas_proc opcode_table[65536];
static void
int to;
/* Sanity check. All set bits must be included in the mask. */
- if (opcode & ~mask)
+ if (opcode & ~mask) {
+ fprintf(stderr,
+ "qemu internal error: bogus opcode definition %04x/%04x\n",
+ opcode, mask);
abort();
+ }
/* This could probably be cleverer. For now just optimize the case where
the top bits are known. */
/* Find the first zero bit in the mask. */
/* Register m68k opcode handlers. Order is important.
Later insn override earlier ones. */
-static void
-register_m68k_insns (m68k_def_t *def)
-{
- uint32_t iflags;
-
- iflags = def->insns;
-#define INSN(name, opcode, mask, isa) \
- if (iflags & M68K_INSN_##isa) \
- register_opcode(disas_##name, 0x##opcode, 0x##mask)
- INSN(undef, 0000, 0000, CF_A);
- INSN(arith_im, 0080, fff8, CF_A);
- INSN(bitrev, 00c0, fff8, CF_C);
- INSN(bitop_reg, 0100, f1c0, CF_A);
- INSN(bitop_reg, 0140, f1c0, CF_A);
- INSN(bitop_reg, 0180, f1c0, CF_A);
- INSN(bitop_reg, 01c0, f1c0, CF_A);
- INSN(arith_im, 0280, fff8, CF_A);
- INSN(byterev, 02c0, fff8, CF_A);
- INSN(arith_im, 0480, fff8, CF_A);
- INSN(ff1, 04c0, fff8, CF_C);
- INSN(arith_im, 0680, fff8, CF_A);
- INSN(bitop_im, 0800, ffc0, CF_A);
- INSN(bitop_im, 0840, ffc0, CF_A);
- INSN(bitop_im, 0880, ffc0, CF_A);
- INSN(bitop_im, 08c0, ffc0, CF_A);
- INSN(arith_im, 0a80, fff8, CF_A);
- INSN(arith_im, 0c00, ff38, CF_A);
- INSN(move, 1000, f000, CF_A);
- INSN(move, 2000, f000, CF_A);
- INSN(move, 3000, f000, CF_A);
- INSN(strldsr, 40e7, ffff, CF_A);
- INSN(negx, 4080, fff8, CF_A);
- INSN(move_from_sr, 40c0, fff8, CF_A);
- INSN(lea, 41c0, f1c0, CF_A);
- INSN(clr, 4200, ff00, CF_A);
- INSN(undef, 42c0, ffc0, CF_A);
- INSN(move_from_ccr, 42c0, fff8, CF_A);
- INSN(neg, 4480, fff8, CF_A);
- INSN(move_to_ccr, 44c0, ffc0, CF_A);
- INSN(not, 4680, fff8, CF_A);
- INSN(move_to_sr, 46c0, ffc0, CF_A);
- INSN(pea, 4840, ffc0, CF_A);
- INSN(swap, 4840, fff8, CF_A);
- INSN(movem, 48c0, fbc0, CF_A);
- INSN(ext, 4880, fff8, CF_A);
- INSN(ext, 48c0, fff8, CF_A);
- INSN(ext, 49c0, fff8, CF_A);
- INSN(tst, 4a00, ff00, CF_A);
- INSN(tas, 4ac0, ffc0, CF_B);
- INSN(halt, 4ac8, ffff, CF_A);
- INSN(pulse, 4acc, ffff, CF_A);
- INSN(illegal, 4afc, ffff, CF_A);
- INSN(mull, 4c00, ffc0, CF_A);
- INSN(divl, 4c40, ffc0, CF_A);
- INSN(sats, 4c80, fff8, CF_B);
- INSN(trap, 4e40, fff0, CF_A);
- INSN(link, 4e50, fff8, CF_A);
- INSN(unlk, 4e58, fff8, CF_A);
- INSN(move_to_usp, 4e60, fff8, CF_B);
- INSN(move_from_usp, 4e68, fff8, CF_B);
- INSN(nop, 4e71, ffff, CF_A);
- INSN(stop, 4e72, ffff, CF_A);
- INSN(rte, 4e73, ffff, CF_A);
- INSN(rts, 4e75, ffff, CF_A);
- INSN(movec, 4e7b, ffff, CF_A);
- INSN(jump, 4e80, ffc0, CF_A);
- INSN(jump, 4ec0, ffc0, CF_A);
- INSN(addsubq, 5180, f1c0, CF_A);
- INSN(scc, 50c0, f0f8, CF_A);
- INSN(addsubq, 5080, f1c0, CF_A);
- INSN(tpf, 51f8, fff8, CF_A);
- INSN(branch, 6000, f000, CF_A);
- INSN(moveq, 7000, f100, CF_A);
- INSN(mvzs, 7100, f100, CF_B);
- INSN(or, 8000, f000, CF_A);
- INSN(divw, 80c0, f0c0, CF_A);
- INSN(addsub, 9000, f000, CF_A);
- INSN(subx, 9180, f1f8, CF_A);
- INSN(suba, 91c0, f1c0, CF_A);
- INSN(undef_mac, a000, f000, CF_A);
- INSN(mov3q, a140, f1c0, CF_B);
- INSN(cmp, b000, f1c0, CF_B); /* cmp.b */
- INSN(cmp, b040, f1c0, CF_B); /* cmp.w */
- INSN(cmpa, b0c0, f1c0, CF_B); /* cmpa.w */
- INSN(cmp, b080, f1c0, CF_A);
- INSN(cmpa, b1c0, f1c0, CF_A);
- INSN(eor, b180, f1c0, CF_A);
- INSN(and, c000, f000, CF_A);
- INSN(mulw, c0c0, f0c0, CF_A);
- INSN(addsub, d000, f000, CF_A);
- INSN(addx, d180, f1f8, CF_A);
- INSN(adda, d1c0, f1c0, CF_A);
- INSN(shift_im, e080, f0f0, CF_A);
- INSN(shift_reg, e0a0, f0f0, CF_A);
- INSN(undef_fpu, f000, f000, CF_A);
+void register_m68k_insns (CPUM68KState *env)
+{
+#define INSN(name, opcode, mask, feature) do { \
+ if (m68k_feature(env, M68K_FEATURE_##feature)) \
+ register_opcode(disas_##name, 0x##opcode, 0x##mask); \
+ } while(0)
+ INSN(undef, 0000, 0000, CF_ISA_A);
+ INSN(arith_im, 0080, fff8, CF_ISA_A);
+ INSN(bitrev, 00c0, fff8, CF_ISA_APLUSC);
+ INSN(bitop_reg, 0100, f1c0, CF_ISA_A);
+ INSN(bitop_reg, 0140, f1c0, CF_ISA_A);
+ INSN(bitop_reg, 0180, f1c0, CF_ISA_A);
+ INSN(bitop_reg, 01c0, f1c0, CF_ISA_A);
+ INSN(arith_im, 0280, fff8, CF_ISA_A);
+ INSN(byterev, 02c0, fff8, CF_ISA_APLUSC);
+ INSN(arith_im, 0480, fff8, CF_ISA_A);
+ INSN(ff1, 04c0, fff8, CF_ISA_APLUSC);
+ INSN(arith_im, 0680, fff8, CF_ISA_A);
+ INSN(bitop_im, 0800, ffc0, CF_ISA_A);
+ INSN(bitop_im, 0840, ffc0, CF_ISA_A);
+ INSN(bitop_im, 0880, ffc0, CF_ISA_A);
+ INSN(bitop_im, 08c0, ffc0, CF_ISA_A);
+ INSN(arith_im, 0a80, fff8, CF_ISA_A);
+ INSN(arith_im, 0c00, ff38, CF_ISA_A);
+ INSN(move, 1000, f000, CF_ISA_A);
+ INSN(move, 2000, f000, CF_ISA_A);
+ INSN(move, 3000, f000, CF_ISA_A);
+ INSN(strldsr, 40e7, ffff, CF_ISA_APLUSC);
+ INSN(negx, 4080, fff8, CF_ISA_A);
+ INSN(move_from_sr, 40c0, fff8, CF_ISA_A);
+ INSN(lea, 41c0, f1c0, CF_ISA_A);
+ INSN(clr, 4200, ff00, CF_ISA_A);
+ INSN(undef, 42c0, ffc0, CF_ISA_A);
+ INSN(move_from_ccr, 42c0, fff8, CF_ISA_A);
+ INSN(neg, 4480, fff8, CF_ISA_A);
+ INSN(move_to_ccr, 44c0, ffc0, CF_ISA_A);
+ INSN(not, 4680, fff8, CF_ISA_A);
+ INSN(move_to_sr, 46c0, ffc0, CF_ISA_A);
+ INSN(pea, 4840, ffc0, CF_ISA_A);
+ INSN(swap, 4840, fff8, CF_ISA_A);
+ INSN(movem, 48c0, fbc0, CF_ISA_A);
+ INSN(ext, 4880, fff8, CF_ISA_A);
+ INSN(ext, 48c0, fff8, CF_ISA_A);
+ INSN(ext, 49c0, fff8, CF_ISA_A);
+ INSN(tst, 4a00, ff00, CF_ISA_A);
+ INSN(tas, 4ac0, ffc0, CF_ISA_B);
+ INSN(halt, 4ac8, ffff, CF_ISA_A);
+ INSN(pulse, 4acc, ffff, CF_ISA_A);
+ INSN(illegal, 4afc, ffff, CF_ISA_A);
+ INSN(mull, 4c00, ffc0, CF_ISA_A);
+ INSN(divl, 4c40, ffc0, CF_ISA_A);
+ INSN(sats, 4c80, fff8, CF_ISA_B);
+ INSN(trap, 4e40, fff0, CF_ISA_A);
+ INSN(link, 4e50, fff8, CF_ISA_A);
+ INSN(unlk, 4e58, fff8, CF_ISA_A);
+ INSN(move_to_usp, 4e60, fff8, USP);
+ INSN(move_from_usp, 4e68, fff8, USP);
+ INSN(nop, 4e71, ffff, CF_ISA_A);
+ INSN(stop, 4e72, ffff, CF_ISA_A);
+ INSN(rte, 4e73, ffff, CF_ISA_A);
+ INSN(rts, 4e75, ffff, CF_ISA_A);
+ INSN(movec, 4e7b, ffff, CF_ISA_A);
+ INSN(jump, 4e80, ffc0, CF_ISA_A);
+ INSN(jump, 4ec0, ffc0, CF_ISA_A);
+ INSN(addsubq, 5180, f1c0, CF_ISA_A);
+ INSN(scc, 50c0, f0f8, CF_ISA_A);
+ INSN(addsubq, 5080, f1c0, CF_ISA_A);
+ INSN(tpf, 51f8, fff8, CF_ISA_A);
+
+ /* Branch instructions. */
+ INSN(branch, 6000, f000, CF_ISA_A);
+ /* Disable long branch instructions, then add back the ones we want. */
+ INSN(undef, 60ff, f0ff, CF_ISA_A); /* All long branches. */
+ INSN(branch, 60ff, f0ff, CF_ISA_B);
+ INSN(undef, 60ff, ffff, CF_ISA_B); /* bra.l */
+ INSN(branch, 60ff, ffff, BRAL);
+
+ INSN(moveq, 7000, f100, CF_ISA_A);
+ INSN(mvzs, 7100, f100, CF_ISA_B);
+ INSN(or, 8000, f000, CF_ISA_A);
+ INSN(divw, 80c0, f0c0, CF_ISA_A);
+ INSN(addsub, 9000, f000, CF_ISA_A);
+ INSN(subx, 9180, f1f8, CF_ISA_A);
+ INSN(suba, 91c0, f1c0, CF_ISA_A);
+
+ INSN(undef_mac, a000, f000, CF_ISA_A);
+ INSN(mac, a000, f100, CF_EMAC);
+ INSN(from_mac, a180, f9b0, CF_EMAC);
+ INSN(move_mac, a110, f9fc, CF_EMAC);
+ INSN(from_macsr,a980, f9f0, CF_EMAC);
+ INSN(from_mask, ad80, fff0, CF_EMAC);
+ INSN(from_mext, ab80, fbf0, CF_EMAC);
+ INSN(macsr_to_ccr, a9c0, ffff, CF_EMAC);
+ INSN(to_mac, a100, f9c0, CF_EMAC);
+ INSN(to_macsr, a900, ffc0, CF_EMAC);
+ INSN(to_mext, ab00, fbc0, CF_EMAC);
+ INSN(to_mask, ad00, ffc0, CF_EMAC);
+
+ INSN(mov3q, a140, f1c0, CF_ISA_B);
+ INSN(cmp, b000, f1c0, CF_ISA_B); /* cmp.b */
+ INSN(cmp, b040, f1c0, CF_ISA_B); /* cmp.w */
+ INSN(cmpa, b0c0, f1c0, CF_ISA_B); /* cmpa.w */
+ INSN(cmp, b080, f1c0, CF_ISA_A);
+ INSN(cmpa, b1c0, f1c0, CF_ISA_A);
+ INSN(eor, b180, f1c0, CF_ISA_A);
+ INSN(and, c000, f000, CF_ISA_A);
+ INSN(mulw, c0c0, f0c0, CF_ISA_A);
+ INSN(addsub, d000, f000, CF_ISA_A);
+ INSN(addx, d180, f1f8, CF_ISA_A);
+ INSN(adda, d1c0, f1c0, CF_ISA_A);
+ INSN(shift_im, e080, f0f0, CF_ISA_A);
+ INSN(shift_reg, e0a0, f0f0, CF_ISA_A);
+ INSN(undef_fpu, f000, f000, CF_ISA_A);
INSN(fpu, f200, ffc0, CF_FPU);
INSN(fbcc, f280, ffc0, CF_FPU);
INSN(frestore, f340, ffc0, CF_FPU);
INSN(fsave, f340, ffc0, CF_FPU);
- INSN(intouch, f340, ffc0, CF_A);
- INSN(cpushl, f428, ff38, CF_A);
- INSN(wddata, fb00, ff00, CF_A);
- INSN(wdebug, fbc0, ffc0, CF_A);
+ INSN(intouch, f340, ffc0, CF_ISA_A);
+ INSN(cpushl, f428, ff38, CF_ISA_A);
+ INSN(wddata, fb00, ff00, CF_ISA_A);
+ INSN(wdebug, fbc0, ffc0, CF_ISA_A);
#undef INSN
}
int arg0 = qop->args[0];
int arg1 = qop->args[1];
int l1, l2;
-
+
gen_op_add32 (arg0, arg0, arg1);
l1 = gen_new_label();
l2 = gen_new_label();
gen_op_add32(arg0, arg0, gen_im32(1));
gen_op_mov32(QREG_CC_OP, gen_im32(CC_OP_ADDX));
gen_op_set_leu32(QREG_CC_X, arg0, arg1);
- gen_op_jmp(l2);
+ gen_op_jmp_im(l2);
gen_set_label(l1);
gen_op_mov32(QREG_CC_OP, gen_im32(CC_OP_ADD));
gen_op_set_ltu32(QREG_CC_X, arg0, arg1);
gen_op_set_leu32(QREG_CC_X, arg0, arg1);
gen_op_sub32(arg0, arg0, gen_im32(1));
gen_op_mov32(QREG_CC_OP, gen_im32(CC_OP_SUBX));
- gen_op_jmp(l2);
+ gen_op_jmp_im(l2);
gen_set_label(l1);
gen_op_set_ltu32(QREG_CC_X, arg0, arg1);
gen_op_mov32(QREG_CC_OP, gen_im32(CC_OP_SUB));
/* generate intermediate code */
pc_start = tb->pc;
-
+
dc->tb = tb;
- gen_opc_ptr = gen_opc_buf;
gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
- gen_opparam_ptr = gen_opparam_buf;
+ dc->env = env;
dc->is_jmp = DISAS_NEXT;
dc->pc = pc_start;
dc->cc_op = CC_OP_DYNAMIC;
dc->singlestep_enabled = env->singlestep_enabled;
dc->fpcr = env->fpcr;
dc->user = (env->sr & SR_S) == 0;
- nb_gen_labels = 0;
+ dc->is_mem = 0;
lj = -1;
do {
free_qreg = 0;
gen_opc_instr_start[lj] = 1;
}
last_cc_op = dc->cc_op;
+ dc->insn_pc = dc->pc;
disas_m68k_insn(env, dc);
+
+ /* Terminate the TB on memory ops if watchpoints are present. */
+ /* FIXME: This should be replacd by the deterministic execution
+ * IRQ raising bits. */
+ if (dc->is_mem && env->nb_watchpoints)
+ break;
} while (!dc->is_jmp && gen_opc_ptr < gen_opc_end &&
!env->singlestep_enabled &&
(pc_offset) < (TARGET_PAGE_SIZE - 32));
case DISAS_UPDATE:
gen_flush_cc_op(dc);
/* indicate that the hash table must be used to find the next TB */
- gen_op_mov32(QREG_T0, gen_im32(0));
- gen_op_exit_tb();
+ tcg_gen_exit_tb(0);
break;
case DISAS_TB_JUMP:
/* nothing more to generate */
fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
target_disas(logfile, pc_start, dc->pc - pc_start, 0);
fprintf(logfile, "\n");
- if (loglevel & (CPU_LOG_TB_OP)) {
- fprintf(logfile, "OP:\n");
- dump_ops(gen_opc_buf, gen_opparam_buf);
- fprintf(logfile, "\n");
- }
}
#endif
if (search_pc) {
lj++;
while (lj <= j)
gen_opc_instr_start[lj++] = 0;
- tb->size = 0;
} else {
tb->size = dc->pc - pc_start;
}
return gen_intermediate_code_internal(env, tb, 1);
}
-void cpu_reset(CPUM68KState *env)
-{
- memset(env, 0, offsetof(CPUM68KState, breakpoints));
-#if !defined (CONFIG_USER_ONLY)
- env->sr = 0x2700;
-#endif
- /* ??? FP regs should be initialized to NaN. */
- env->cc_op = CC_OP_FLAGS;
- /* TODO: We should set PC from the interrupt vector. */
- env->pc = 0;
- tlb_flush(env, 1);
-}
-
-CPUM68KState *cpu_m68k_init(void)
-{
- CPUM68KState *env;
-
- env = malloc(sizeof(CPUM68KState));
- if (!env)
- return NULL;
- cpu_exec_init(env);
-
- cpu_reset(env);
- return env;
-}
-
-void cpu_m68k_close(CPUM68KState *env)
-{
- free(env);
-}
-
-int cpu_m68k_set_model(CPUM68KState *env, const char * name)
-{
- m68k_def_t *def;
-
- for (def = m68k_cpu_defs; def->name; def++) {
- if (strcmp(def->name, name) == 0)
- break;
- }
- if (!def->name)
- return 1;
-
- register_m68k_insns(def);
-
- return 0;
-}
-
-void cpu_dump_state(CPUState *env, FILE *f,
+void cpu_dump_state(CPUState *env, FILE *f,
int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
int flags)
{
u.d = env->fregs[i];
cpu_fprintf (f, "D%d = %08x A%d = %08x F%d = %08x%08x (%12g)\n",
i, env->dregs[i], i, env->aregs[i],
- i, u.l.upper, u.l.lower, u.d);
+ i, u.l.upper, u.l.lower, *(double *)&u.d);
}
cpu_fprintf (f, "PC = %08x ", env->pc);
sr = env->sr;
cpu_fprintf (f, "SR = %04x %c%c%c%c%c ", sr, (sr & 0x10) ? 'X' : '-',
(sr & CCF_N) ? 'N' : '-', (sr & CCF_Z) ? 'Z' : '-',
(sr & CCF_V) ? 'V' : '-', (sr & CCF_C) ? 'C' : '-');
- cpu_fprintf (f, "FPRESULT = %12g\n", env->fp_result);
+ cpu_fprintf (f, "FPRESULT = %12g\n", *(double *)&env->fp_result);
}
projects / qemu / blobdiff