*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
*/
#include <stdarg.h>
#include <stdlib.h>
#include <string.h>
#include <inttypes.h>
#include <signal.h>
-#include <assert.h>
#include "cpu.h"
#include "exec-all.h"
target_ulong mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
target_ulong tag = address & ~mask;
target_ulong VPN = tlb->VPN & ~mask;
-#ifdef TARGET_MIPS64
+#if defined(TARGET_MIPS64)
tag &= env->SEGMask;
#endif
return TLBRET_NOMATCH;
}
+#if !defined(CONFIG_USER_ONLY)
static int get_physical_address (CPUState *env, target_ulong *physical,
int *prot, target_ulong address,
int rw, int access_type)
{
/* User mode can only access useg/xuseg */
int user_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM;
-#ifdef TARGET_MIPS64
+ int supervisor_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_SM;
+ int kernel_mode = !user_mode && !supervisor_mode;
+#if defined(TARGET_MIPS64)
int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
int ret = TLBRET_MATCH;
#if 0
- if (logfile) {
- fprintf(logfile, "user mode %d h %08x\n",
- user_mode, env->hflags);
- }
-#endif
-
-#ifdef TARGET_MIPS64
- if (user_mode && address > 0x3FFFFFFFFFFFFFFFULL)
- return TLBRET_BADADDR;
-#else
- if (user_mode && address > 0x7FFFFFFFUL)
- return TLBRET_BADADDR;
+ qemu_log("user mode %d h %08x\n", user_mode, env->hflags);
#endif
if (address <= (int32_t)0x7FFFFFFFUL) {
} else {
ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
}
-#ifdef TARGET_MIPS64
-/*
- XXX: Assuming :
- - PABITS = 36 (correct for MIPS64R1)
-*/
- } else if (address < 0x3FFFFFFFFFFFFFFFULL) {
+#if defined(TARGET_MIPS64)
+ } else if (address < 0x4000000000000000ULL) {
/* xuseg */
- if (UX && address < (0x3FFFFFFFFFFFFFFFULL & env->SEGMask)) {
+ if (UX && address <= (0x3FFFFFFFFFFFFFFFULL & env->SEGMask)) {
ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
- } else {
- ret = TLBRET_BADADDR;
+ } else {
+ ret = TLBRET_BADADDR;
}
- } else if (address < 0x7FFFFFFFFFFFFFFFULL) {
+ } else if (address < 0x8000000000000000ULL) {
/* xsseg */
- if (SX && address < (0x7FFFFFFFFFFFFFFFULL & env->SEGMask)) {
+ if ((supervisor_mode || kernel_mode) &&
+ SX && address <= (0x7FFFFFFFFFFFFFFFULL & env->SEGMask)) {
ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
- } else {
- ret = TLBRET_BADADDR;
+ } else {
+ ret = TLBRET_BADADDR;
}
- } else if (address < 0xBFFFFFFFFFFFFFFFULL) {
+ } else if (address < 0xC000000000000000ULL) {
/* xkphys */
- /* XXX: check supervisor mode */
- if (KX && (address & 0x07FFFFFFFFFFFFFFULL) < 0X0000000FFFFFFFFFULL)
- {
- *physical = address & 0X0000000FFFFFFFFFULL;
+ if (kernel_mode && KX &&
+ (address & 0x07FFFFFFFFFFFFFFULL) <= env->PAMask) {
+ *physical = address & env->PAMask;
*prot = PAGE_READ | PAGE_WRITE;
- } else {
- ret = TLBRET_BADADDR;
- }
- } else if (address < 0xFFFFFFFF7FFFFFFFULL) {
+ } else {
+ ret = TLBRET_BADADDR;
+ }
+ } else if (address < 0xFFFFFFFF80000000ULL) {
/* xkseg */
- /* XXX: check supervisor mode */
- if (KX && address < (0xFFFFFFFF7FFFFFFFULL & env->SEGMask)) {
+ if (kernel_mode && KX &&
+ address <= (0xFFFFFFFF7FFFFFFFULL & env->SEGMask)) {
ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
- } else {
- ret = TLBRET_BADADDR;
- }
+ } else {
+ ret = TLBRET_BADADDR;
+ }
#endif
} else if (address < (int32_t)0xA0000000UL) {
/* kseg0 */
- /* XXX: check supervisor mode */
- *physical = address - (int32_t)0x80000000UL;
- *prot = PAGE_READ | PAGE_WRITE;
+ if (kernel_mode) {
+ *physical = address - (int32_t)0x80000000UL;
+ *prot = PAGE_READ | PAGE_WRITE;
+ } else {
+ ret = TLBRET_BADADDR;
+ }
} else if (address < (int32_t)0xC0000000UL) {
/* kseg1 */
- /* XXX: check supervisor mode */
- *physical = address - (int32_t)0xA0000000UL;
- *prot = PAGE_READ | PAGE_WRITE;
+ if (kernel_mode) {
+ *physical = address - (int32_t)0xA0000000UL;
+ *prot = PAGE_READ | PAGE_WRITE;
+ } else {
+ ret = TLBRET_BADADDR;
+ }
} else if (address < (int32_t)0xE0000000UL) {
- /* kseg2 */
- ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
+ /* sseg (kseg2) */
+ if (supervisor_mode || kernel_mode) {
+ ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
+ } else {
+ ret = TLBRET_BADADDR;
+ }
} else {
/* kseg3 */
- /* XXX: check supervisor mode */
/* XXX: debug segment is not emulated */
- ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
+ if (kernel_mode) {
+ ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
+ } else {
+ ret = TLBRET_BADADDR;
+ }
}
#if 0
- if (logfile) {
- fprintf(logfile, TARGET_FMT_lx " %d %d => " TARGET_FMT_lx " %d (%d)\n",
- address, rw, access_type, *physical, *prot, ret);
+ qemu_log(TARGET_FMT_lx " %d %d => " TARGET_FMT_lx " %d (%d)\n",
+ address, rw, access_type, *physical, *prot, ret);
}
#endif
return ret;
}
+#endif
-#if defined(CONFIG_USER_ONLY)
target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
{
+#if defined(CONFIG_USER_ONLY)
return addr;
-}
#else
-target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
-{
target_ulong phys_addr;
int prot;
if (get_physical_address(env, &phys_addr, &prot, addr, 0, ACCESS_INT) != 0)
return -1;
return phys_addr;
+#endif
}
-void cpu_mips_init_mmu (CPUState *env)
-{
-}
-#endif /* !defined(CONFIG_USER_ONLY) */
-
int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
- int is_user, int is_softmmu)
+ int mmu_idx, int is_softmmu)
{
+#if !defined(CONFIG_USER_ONLY)
target_ulong physical;
int prot;
+#endif
int exception = 0, error_code = 0;
int access_type;
int ret = 0;
- if (logfile) {
#if 0
- cpu_dump_state(env, logfile, fprintf, 0);
+ log_cpu_state(env, 0);
#endif
- fprintf(logfile, "%s pc " TARGET_FMT_lx " ad " TARGET_FMT_lx " rw %d is_user %d smmu %d\n",
- __func__, env->PC[env->current_tc], address, rw, is_user, is_softmmu);
- }
+ qemu_log("%s pc " TARGET_FMT_lx " ad " TARGET_FMT_lx " rw %d mmu_idx %d smmu %d\n",
+ __func__, env->active_tc.PC, address, rw, mmu_idx, is_softmmu);
rw &= 1;
/* XXX: put correct access by using cpu_restore_state()
correctly */
access_type = ACCESS_INT;
- if (env->user_mode_only) {
- /* user mode only emulation */
- ret = TLBRET_NOMATCH;
- goto do_fault;
- }
+#if defined(CONFIG_USER_ONLY)
+ ret = TLBRET_NOMATCH;
+#else
ret = get_physical_address(env, &physical, &prot,
address, rw, access_type);
- if (logfile) {
- fprintf(logfile, "%s address=" TARGET_FMT_lx " ret %d physical " TARGET_FMT_lx " prot %d\n",
- __func__, address, ret, physical, prot);
- }
+ qemu_log("%s address=" TARGET_FMT_lx " ret %d physical " TARGET_FMT_lx " prot %d\n",
+ __func__, address, ret, physical, prot);
if (ret == TLBRET_MATCH) {
ret = tlb_set_page(env, address & TARGET_PAGE_MASK,
physical & TARGET_PAGE_MASK, prot,
- is_user, is_softmmu);
- } else if (ret < 0) {
- do_fault:
+ mmu_idx, is_softmmu);
+ } else if (ret < 0)
+#endif
+ {
switch (ret) {
default:
case TLBRET_BADADDR:
/* Raise exception */
env->CP0_BadVAddr = address;
env->CP0_Context = (env->CP0_Context & ~0x007fffff) |
- ((address >> 9) & 0x007ffff0);
+ ((address >> 9) & 0x007ffff0);
env->CP0_EntryHi =
(env->CP0_EntryHi & 0xFF) | (address & (TARGET_PAGE_MASK << 1));
-#ifdef TARGET_MIPS64
+#if defined(TARGET_MIPS64)
env->CP0_EntryHi &= env->SEGMask;
env->CP0_XContext = (env->CP0_XContext & ((~0ULL) << (env->SEGBITS - 7))) |
- ((address & 0xC00000000000ULL) >> (env->SEGBITS - 9)) |
+ ((address & 0xC00000000000ULL) >> (55 - env->SEGBITS)) |
((address & ((1ULL << env->SEGBITS) - 1) & 0xFFFFFFFFFFFFE000ULL) >> 9);
#endif
env->exception_index = exception;
return ret;
}
-#if defined(CONFIG_USER_ONLY)
-void do_interrupt (CPUState *env)
-{
- env->exception_index = EXCP_NONE;
-}
-#else
+static const char * const excp_names[EXCP_LAST + 1] = {
+ [EXCP_RESET] = "reset",
+ [EXCP_SRESET] = "soft reset",
+ [EXCP_DSS] = "debug single step",
+ [EXCP_DINT] = "debug interrupt",
+ [EXCP_NMI] = "non-maskable interrupt",
+ [EXCP_MCHECK] = "machine check",
+ [EXCP_EXT_INTERRUPT] = "interrupt",
+ [EXCP_DFWATCH] = "deferred watchpoint",
+ [EXCP_DIB] = "debug instruction breakpoint",
+ [EXCP_IWATCH] = "instruction fetch watchpoint",
+ [EXCP_AdEL] = "address error load",
+ [EXCP_AdES] = "address error store",
+ [EXCP_TLBF] = "TLB refill",
+ [EXCP_IBE] = "instruction bus error",
+ [EXCP_DBp] = "debug breakpoint",
+ [EXCP_SYSCALL] = "syscall",
+ [EXCP_BREAK] = "break",
+ [EXCP_CpU] = "coprocessor unusable",
+ [EXCP_RI] = "reserved instruction",
+ [EXCP_OVERFLOW] = "arithmetic overflow",
+ [EXCP_TRAP] = "trap",
+ [EXCP_FPE] = "floating point",
+ [EXCP_DDBS] = "debug data break store",
+ [EXCP_DWATCH] = "data watchpoint",
+ [EXCP_LTLBL] = "TLB modify",
+ [EXCP_TLBL] = "TLB load",
+ [EXCP_TLBS] = "TLB store",
+ [EXCP_DBE] = "data bus error",
+ [EXCP_DDBL] = "debug data break load",
+ [EXCP_THREAD] = "thread",
+ [EXCP_MDMX] = "MDMX",
+ [EXCP_C2E] = "precise coprocessor 2",
+ [EXCP_CACHE] = "cache error",
+};
+
void do_interrupt (CPUState *env)
{
+#if !defined(CONFIG_USER_ONLY)
target_ulong offset;
int cause = -1;
+ const char *name;
+
+ if (qemu_log_enabled() && env->exception_index != EXCP_EXT_INTERRUPT) {
+ if (env->exception_index < 0 || env->exception_index > EXCP_LAST)
+ name = "unknown";
+ else
+ name = excp_names[env->exception_index];
- if (logfile && env->exception_index != EXCP_EXT_INTERRUPT) {
- fprintf(logfile, "%s enter: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " cause %d excp %d\n",
- __func__, env->PC[env->current_tc], env->CP0_EPC, cause, env->exception_index);
+ qemu_log("%s enter: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " %s exception\n",
+ __func__, env->active_tc.PC, env->CP0_EPC, name);
}
if (env->exception_index == EXCP_EXT_INTERRUPT &&
(env->hflags & MIPS_HFLAG_DM))
case EXCP_DSS:
env->CP0_Debug |= 1 << CP0DB_DSS;
/* Debug single step cannot be raised inside a delay slot and
- * resume will always occur on the next instruction
- * (but we assume the pc has always been updated during
- * code translation).
- */
- env->CP0_DEPC = env->PC[env->current_tc];
+ resume will always occur on the next instruction
+ (but we assume the pc has always been updated during
+ code translation). */
+ env->CP0_DEPC = env->active_tc.PC;
goto enter_debug_mode;
case EXCP_DINT:
env->CP0_Debug |= 1 << CP0DB_DINT;
if (env->hflags & MIPS_HFLAG_BMASK) {
/* If the exception was raised from a delay slot,
come back to the jump. */
- env->CP0_DEPC = env->PC[env->current_tc] - 4;
+ env->CP0_DEPC = env->active_tc.PC - 4;
env->hflags &= ~MIPS_HFLAG_BMASK;
} else {
- env->CP0_DEPC = env->PC[env->current_tc];
+ env->CP0_DEPC = env->active_tc.PC;
}
- enter_debug_mode:
- env->hflags |= MIPS_HFLAG_DM;
- if ((env->CP0_Config0 & (0x3 << CP0C0_AT)))
- env->hflags |= MIPS_HFLAG_64;
- env->hflags &= ~MIPS_HFLAG_UM;
+ enter_debug_mode:
+ env->hflags |= MIPS_HFLAG_DM | MIPS_HFLAG_64 | MIPS_HFLAG_CP0;
+ env->hflags &= ~(MIPS_HFLAG_KSU);
/* EJTAG probe trap enable is not implemented... */
if (!(env->CP0_Status & (1 << CP0St_EXL)))
env->CP0_Cause &= ~(1 << CP0Ca_BD);
- env->PC[env->current_tc] = (int32_t)0xBFC00480;
+ env->active_tc.PC = (int32_t)0xBFC00480;
break;
case EXCP_RESET:
cpu_reset(env);
goto set_error_EPC;
case EXCP_NMI:
env->CP0_Status |= (1 << CP0St_NMI);
- set_error_EPC:
+ set_error_EPC:
if (env->hflags & MIPS_HFLAG_BMASK) {
/* If the exception was raised from a delay slot,
come back to the jump. */
- env->CP0_ErrorEPC = env->PC[env->current_tc] - 4;
+ env->CP0_ErrorEPC = env->active_tc.PC - 4;
env->hflags &= ~MIPS_HFLAG_BMASK;
} else {
- env->CP0_ErrorEPC = env->PC[env->current_tc];
+ env->CP0_ErrorEPC = env->active_tc.PC;
}
env->CP0_Status |= (1 << CP0St_ERL) | (1 << CP0St_BEV);
- if ((env->CP0_Config0 & (0x3 << CP0C0_AT)))
- env->hflags |= MIPS_HFLAG_64;
- env->hflags &= ~MIPS_HFLAG_UM;
+ env->hflags |= MIPS_HFLAG_64 | MIPS_HFLAG_CP0;
+ env->hflags &= ~(MIPS_HFLAG_KSU);
if (!(env->CP0_Status & (1 << CP0St_EXL)))
env->CP0_Cause &= ~(1 << CP0Ca_BD);
- env->PC[env->current_tc] = (int32_t)0xBFC00000;
+ env->active_tc.PC = (int32_t)0xBFC00000;
break;
- case EXCP_MCHECK:
- cause = 24;
- goto set_EPC;
case EXCP_EXT_INTERRUPT:
cause = 0;
if (env->CP0_Cause & (1 << CP0Ca_IV))
offset = 0x200;
goto set_EPC;
- case EXCP_DWATCH:
- cause = 23;
- /* XXX: TODO: manage defered watch exceptions */
- goto set_EPC;
- case EXCP_AdEL:
- cause = 4;
- goto set_EPC;
- case EXCP_AdES:
- cause = 5;
+ case EXCP_LTLBL:
+ cause = 1;
goto set_EPC;
case EXCP_TLBL:
cause = 2;
if (env->error_code == 1 && !(env->CP0_Status & (1 << CP0St_EXL))) {
-#ifdef TARGET_MIPS64
+#if defined(TARGET_MIPS64)
+ int R = env->CP0_BadVAddr >> 62;
+ int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
+ int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
+ int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
+
+ if ((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX))
+ offset = 0x080;
+ else
+#endif
+ offset = 0x000;
+ }
+ goto set_EPC;
+ case EXCP_TLBS:
+ cause = 3;
+ if (env->error_code == 1 && !(env->CP0_Status & (1 << CP0St_EXL))) {
+#if defined(TARGET_MIPS64)
int R = env->CP0_BadVAddr >> 62;
int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
offset = 0x000;
}
goto set_EPC;
+ case EXCP_AdEL:
+ cause = 4;
+ goto set_EPC;
+ case EXCP_AdES:
+ cause = 5;
+ goto set_EPC;
case EXCP_IBE:
cause = 6;
goto set_EPC;
case EXCP_FPE:
cause = 15;
goto set_EPC;
- case EXCP_LTLBL:
- cause = 1;
+ case EXCP_C2E:
+ cause = 18;
goto set_EPC;
- case EXCP_TLBS:
- cause = 3;
+ case EXCP_MDMX:
+ cause = 22;
+ goto set_EPC;
+ case EXCP_DWATCH:
+ cause = 23;
+ /* XXX: TODO: manage defered watch exceptions */
+ goto set_EPC;
+ case EXCP_MCHECK:
+ cause = 24;
goto set_EPC;
case EXCP_THREAD:
cause = 25;
- if (env->error_code == 1 && !(env->CP0_Status & (1 << CP0St_EXL))) {
-#ifdef TARGET_MIPS64
- int R = env->CP0_BadVAddr >> 62;
- int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
- int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
- int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
-
- if ((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX))
- offset = 0x080;
- else
-#endif
- offset = 0x000;
+ goto set_EPC;
+ case EXCP_CACHE:
+ cause = 30;
+ if (env->CP0_Status & (1 << CP0St_BEV)) {
+ offset = 0x100;
+ } else {
+ offset = 0x20000100;
}
- set_EPC:
+ set_EPC:
if (!(env->CP0_Status & (1 << CP0St_EXL))) {
if (env->hflags & MIPS_HFLAG_BMASK) {
/* If the exception was raised from a delay slot,
come back to the jump. */
- env->CP0_EPC = env->PC[env->current_tc] - 4;
+ env->CP0_EPC = env->active_tc.PC - 4;
env->CP0_Cause |= (1 << CP0Ca_BD);
} else {
- env->CP0_EPC = env->PC[env->current_tc];
+ env->CP0_EPC = env->active_tc.PC;
env->CP0_Cause &= ~(1 << CP0Ca_BD);
}
env->CP0_Status |= (1 << CP0St_EXL);
- if ((env->CP0_Config0 & (0x3 << CP0C0_AT)))
- env->hflags |= MIPS_HFLAG_64;
- env->hflags &= ~MIPS_HFLAG_UM;
+ env->hflags |= MIPS_HFLAG_64 | MIPS_HFLAG_CP0;
+ env->hflags &= ~(MIPS_HFLAG_KSU);
}
env->hflags &= ~MIPS_HFLAG_BMASK;
if (env->CP0_Status & (1 << CP0St_BEV)) {
- env->PC[env->current_tc] = (int32_t)0xBFC00200;
+ env->active_tc.PC = (int32_t)0xBFC00200;
} else {
- env->PC[env->current_tc] = (int32_t)(env->CP0_EBase & ~0x3ff);
+ env->active_tc.PC = (int32_t)(env->CP0_EBase & ~0x3ff);
}
- env->PC[env->current_tc] += offset;
+ env->active_tc.PC += offset;
env->CP0_Cause = (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) | (cause << CP0Ca_EC);
break;
default:
- if (logfile) {
- fprintf(logfile, "Invalid MIPS exception %d. Exiting\n",
- env->exception_index);
- }
+ qemu_log("Invalid MIPS exception %d. Exiting\n", env->exception_index);
printf("Invalid MIPS exception %d. Exiting\n", env->exception_index);
exit(1);
}
- if (logfile && env->exception_index != EXCP_EXT_INTERRUPT) {
- fprintf(logfile, "%s: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " cause %d excp %d\n"
+ if (qemu_log_enabled() && env->exception_index != EXCP_EXT_INTERRUPT) {
+ qemu_log("%s: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " cause %d\n"
" S %08x C %08x A " TARGET_FMT_lx " D " TARGET_FMT_lx "\n",
- __func__, env->PC[env->current_tc], env->CP0_EPC, cause, env->exception_index,
+ __func__, env->active_tc.PC, env->CP0_EPC, cause,
env->CP0_Status, env->CP0_Cause, env->CP0_BadVAddr,
env->CP0_DEPC);
}
+#endif
env->exception_index = EXCP_NONE;
}
-#endif /* !defined(CONFIG_USER_ONLY) */
void r4k_invalidate_tlb (CPUState *env, int idx, int use_extra)
{
if (use_extra && env->tlb->tlb_in_use < MIPS_TLB_MAX) {
/* For tlbwr, we can shadow the discarded entry into
- a new (fake) TLB entry, as long as the guest can not
- tell that it's there. */
+ a new (fake) TLB entry, as long as the guest can not
+ tell that it's there. */
env->tlb->mmu.r4k.tlb[env->tlb->tlb_in_use] = *tlb;
env->tlb->tlb_in_use++;
return;
mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
if (tlb->V0) {
addr = tlb->VPN & ~mask;
-#ifdef TARGET_MIPS64
+#if defined(TARGET_MIPS64)
if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) {
addr |= 0x3FFFFF0000000000ULL;
}
}
if (tlb->V1) {
addr = (tlb->VPN & ~mask) | ((mask >> 1) + 1);
-#ifdef TARGET_MIPS64
+#if defined(TARGET_MIPS64)
if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) {
addr |= 0x3FFFFF0000000000ULL;
}
#endif
end = addr | mask;
- while (addr < end) {
+ while (addr - 1 < end) {
tlb_flush_page (env, addr);
addr += TARGET_PAGE_SIZE;
}
projects / qemu / blobdiff