/* Moves to/from shadow registers. */
static inline void gen_load_srsgpr (int from, int to)
{
- TCGv r_tmp1 = tcg_temp_new();
+ TCGv t0 = tcg_temp_new();
if (from == 0)
- tcg_gen_movi_tl(r_tmp1, 0);
+ tcg_gen_movi_tl(t0, 0);
else {
- TCGv_i32 r_tmp2 = tcg_temp_new_i32();
+ TCGv_i32 t2 = tcg_temp_new_i32();
TCGv_ptr addr = tcg_temp_new_ptr();
- tcg_gen_ld_i32(r_tmp2, cpu_env, offsetof(CPUState, CP0_SRSCtl));
- tcg_gen_shri_i32(r_tmp2, r_tmp2, CP0SRSCtl_PSS);
- tcg_gen_andi_i32(r_tmp2, r_tmp2, 0xf);
- tcg_gen_muli_i32(r_tmp2, r_tmp2, sizeof(target_ulong) * 32);
- tcg_gen_ext_i32_ptr(addr, r_tmp2);
+ tcg_gen_ld_i32(t2, cpu_env, offsetof(CPUState, CP0_SRSCtl));
+ tcg_gen_shri_i32(t2, t2, CP0SRSCtl_PSS);
+ tcg_gen_andi_i32(t2, t2, 0xf);
+ tcg_gen_muli_i32(t2, t2, sizeof(target_ulong) * 32);
+ tcg_gen_ext_i32_ptr(addr, t2);
tcg_gen_add_ptr(addr, cpu_env, addr);
- tcg_gen_ld_tl(r_tmp1, addr, sizeof(target_ulong) * from);
+ tcg_gen_ld_tl(t0, addr, sizeof(target_ulong) * from);
tcg_temp_free_ptr(addr);
- tcg_temp_free_i32(r_tmp2);
+ tcg_temp_free_i32(t2);
}
- gen_store_gpr(r_tmp1, to);
- tcg_temp_free(r_tmp1);
+ gen_store_gpr(t0, to);
+ tcg_temp_free(t0);
}
static inline void gen_store_srsgpr (int from, int to)
{
if (to != 0) {
- TCGv r_tmp1 = tcg_temp_new();
- TCGv_i32 r_tmp2 = tcg_temp_new_i32();
+ TCGv t0 = tcg_temp_new();
+ TCGv_i32 t2 = tcg_temp_new_i32();
TCGv_ptr addr = tcg_temp_new_ptr();
- gen_load_gpr(r_tmp1, from);
- tcg_gen_ld_i32(r_tmp2, cpu_env, offsetof(CPUState, CP0_SRSCtl));
- tcg_gen_shri_i32(r_tmp2, r_tmp2, CP0SRSCtl_PSS);
- tcg_gen_andi_i32(r_tmp2, r_tmp2, 0xf);
- tcg_gen_muli_i32(r_tmp2, r_tmp2, sizeof(target_ulong) * 32);
- tcg_gen_ext_i32_ptr(addr, r_tmp2);
+ gen_load_gpr(t0, from);
+ tcg_gen_ld_i32(t2, cpu_env, offsetof(CPUState, CP0_SRSCtl));
+ tcg_gen_shri_i32(t2, t2, CP0SRSCtl_PSS);
+ tcg_gen_andi_i32(t2, t2, 0xf);
+ tcg_gen_muli_i32(t2, t2, sizeof(target_ulong) * 32);
+ tcg_gen_ext_i32_ptr(addr, t2);
tcg_gen_add_ptr(addr, cpu_env, addr);
- tcg_gen_st_tl(r_tmp1, addr, sizeof(target_ulong) * to);
+ tcg_gen_st_tl(t0, addr, sizeof(target_ulong) * to);
tcg_temp_free_ptr(addr);
- tcg_temp_free_i32(r_tmp2);
- tcg_temp_free(r_tmp1);
+ tcg_temp_free_i32(t2);
+ tcg_temp_free(t0);
}
}
gen_helper_raise_exception_err(texcp, terr);
tcg_temp_free_i32(terr);
tcg_temp_free_i32(texcp);
- gen_helper_interrupt_restart();
- tcg_gen_exit_tb(0);
}
static inline void
{
save_cpu_state(ctx, 1);
gen_helper_0i(raise_exception, excp);
- gen_helper_interrupt_restart();
- tcg_gen_exit_tb(0);
}
/* Addresses computation */
}
/* load/store instructions. */
-#define OP_LD(insn,fname) \
-static inline void op_ldst_##insn(TCGv t0, DisasContext *ctx) \
-{ \
- tcg_gen_qemu_##fname(t0, t0, ctx->mem_idx); \
+#define OP_LD(insn,fname) \
+static inline void op_ldst_##insn(TCGv ret, TCGv arg1, DisasContext *ctx) \
+{ \
+ tcg_gen_qemu_##fname(ret, arg1, ctx->mem_idx); \
}
OP_LD(lb,ld8s);
OP_LD(lbu,ld8u);
#endif
#undef OP_LD
-#define OP_ST(insn,fname) \
-static inline void op_ldst_##insn(TCGv t0, TCGv t1, DisasContext *ctx) \
-{ \
- tcg_gen_qemu_##fname(t1, t0, ctx->mem_idx); \
+#define OP_ST(insn,fname) \
+static inline void op_ldst_##insn(TCGv arg1, TCGv arg2, DisasContext *ctx) \
+{ \
+ tcg_gen_qemu_##fname(arg1, arg2, ctx->mem_idx); \
}
OP_ST(sb,st8);
OP_ST(sh,st16);
#endif
#undef OP_ST
-#define OP_LD_ATOMIC(insn,fname) \
-static inline void op_ldst_##insn(TCGv t0, TCGv t1, DisasContext *ctx) \
-{ \
- tcg_gen_mov_tl(t1, t0); \
- tcg_gen_qemu_##fname(t0, t0, ctx->mem_idx); \
- tcg_gen_st_tl(t1, cpu_env, offsetof(CPUState, CP0_LLAddr)); \
+#define OP_LD_ATOMIC(insn,fname) \
+static inline void op_ldst_##insn(TCGv ret, TCGv arg1, DisasContext *ctx) \
+{ \
+ TCGv t0 = tcg_temp_new(); \
+ tcg_gen_mov_tl(t0, arg1); \
+ tcg_gen_qemu_##fname(ret, arg1, ctx->mem_idx); \
+ tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, CP0_LLAddr)); \
+ tcg_temp_free(t0); \
}
OP_LD_ATOMIC(ll,ld32s);
#if defined(TARGET_MIPS64)
#endif
#undef OP_LD_ATOMIC
-#define OP_ST_ATOMIC(insn,fname,almask) \
-static inline void op_ldst_##insn(TCGv t0, TCGv t1, DisasContext *ctx) \
-{ \
- TCGv r_tmp = tcg_temp_new(); \
- int l1 = gen_new_label(); \
- int l2 = gen_new_label(); \
- int l3 = gen_new_label(); \
- \
- tcg_gen_andi_tl(r_tmp, t0, almask); \
- tcg_gen_brcondi_tl(TCG_COND_EQ, r_tmp, 0, l1); \
- tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, CP0_BadVAddr)); \
- generate_exception(ctx, EXCP_AdES); \
- gen_set_label(l1); \
- tcg_gen_ld_tl(r_tmp, cpu_env, offsetof(CPUState, CP0_LLAddr)); \
- tcg_gen_brcond_tl(TCG_COND_NE, t0, r_tmp, l2); \
- tcg_temp_free(r_tmp); \
- tcg_gen_qemu_##fname(t1, t0, ctx->mem_idx); \
- tcg_gen_movi_tl(t0, 1); \
- tcg_gen_br(l3); \
- gen_set_label(l2); \
- tcg_gen_movi_tl(t0, 0); \
- gen_set_label(l3); \
+#define OP_ST_ATOMIC(insn,fname,almask) \
+static inline void op_ldst_##insn(TCGv ret, TCGv arg1, TCGv arg2, DisasContext *ctx) \
+{ \
+ TCGv t0 = tcg_temp_new(); \
+ int l1 = gen_new_label(); \
+ int l2 = gen_new_label(); \
+ int l3 = gen_new_label(); \
+ \
+ tcg_gen_andi_tl(t0, arg2, almask); \
+ tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); \
+ tcg_gen_st_tl(arg2, cpu_env, offsetof(CPUState, CP0_BadVAddr)); \
+ generate_exception(ctx, EXCP_AdES); \
+ gen_set_label(l1); \
+ tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_LLAddr)); \
+ tcg_gen_brcond_tl(TCG_COND_NE, arg2, t0, l2); \
+ tcg_temp_free(t0); \
+ tcg_gen_qemu_##fname(arg1, arg2, ctx->mem_idx); \
+ tcg_gen_movi_tl(ret, 1); \
+ tcg_gen_br(l3); \
+ gen_set_label(l2); \
+ tcg_gen_movi_tl(ret, 0); \
+ gen_set_label(l3); \
}
OP_ST_ATOMIC(sc,st32,0x3);
#if defined(TARGET_MIPS64)
#if defined(TARGET_MIPS64)
case OPC_LWU:
save_cpu_state(ctx, 0);
- op_ldst_lwu(t0, ctx);
+ op_ldst_lwu(t0, t0, ctx);
gen_store_gpr(t0, rt);
opn = "lwu";
break;
case OPC_LD:
save_cpu_state(ctx, 0);
- op_ldst_ld(t0, ctx);
+ op_ldst_ld(t0, t0, ctx);
gen_store_gpr(t0, rt);
opn = "ld";
break;
case OPC_LLD:
save_cpu_state(ctx, 0);
- op_ldst_lld(t0, t1, ctx);
+ op_ldst_lld(t0, t0, ctx);
gen_store_gpr(t0, rt);
opn = "lld";
break;
case OPC_SD:
save_cpu_state(ctx, 0);
gen_load_gpr(t1, rt);
- op_ldst_sd(t0, t1, ctx);
+ op_ldst_sd(t1, t0, ctx);
opn = "sd";
break;
case OPC_LDL:
save_cpu_state(ctx, 1);
gen_load_gpr(t1, rt);
- gen_helper_3i(ldl, t1, t0, t1, ctx->mem_idx);
+ gen_helper_3i(ldl, t1, t1, t0, ctx->mem_idx);
gen_store_gpr(t1, rt);
opn = "ldl";
break;
case OPC_SDL:
save_cpu_state(ctx, 1);
gen_load_gpr(t1, rt);
- gen_helper_2i(sdl, t0, t1, ctx->mem_idx);
+ gen_helper_2i(sdl, t1, t0, ctx->mem_idx);
opn = "sdl";
break;
case OPC_LDR:
save_cpu_state(ctx, 1);
gen_load_gpr(t1, rt);
- gen_helper_3i(ldr, t1, t0, t1, ctx->mem_idx);
+ gen_helper_3i(ldr, t1, t1, t0, ctx->mem_idx);
gen_store_gpr(t1, rt);
opn = "ldr";
break;
case OPC_SDR:
save_cpu_state(ctx, 1);
gen_load_gpr(t1, rt);
- gen_helper_2i(sdr, t0, t1, ctx->mem_idx);
+ gen_helper_2i(sdr, t1, t0, ctx->mem_idx);
opn = "sdr";
break;
#endif
case OPC_LW:
save_cpu_state(ctx, 0);
- op_ldst_lw(t0, ctx);
+ op_ldst_lw(t0, t0, ctx);
gen_store_gpr(t0, rt);
opn = "lw";
break;
case OPC_SW:
save_cpu_state(ctx, 0);
gen_load_gpr(t1, rt);
- op_ldst_sw(t0, t1, ctx);
+ op_ldst_sw(t1, t0, ctx);
opn = "sw";
break;
case OPC_LH:
save_cpu_state(ctx, 0);
- op_ldst_lh(t0, ctx);
+ op_ldst_lh(t0, t0, ctx);
gen_store_gpr(t0, rt);
opn = "lh";
break;
case OPC_SH:
save_cpu_state(ctx, 0);
gen_load_gpr(t1, rt);
- op_ldst_sh(t0, t1, ctx);
+ op_ldst_sh(t1, t0, ctx);
opn = "sh";
break;
case OPC_LHU:
save_cpu_state(ctx, 0);
- op_ldst_lhu(t0, ctx);
+ op_ldst_lhu(t0, t0, ctx);
gen_store_gpr(t0, rt);
opn = "lhu";
break;
case OPC_LB:
save_cpu_state(ctx, 0);
- op_ldst_lb(t0, ctx);
+ op_ldst_lb(t0, t0, ctx);
gen_store_gpr(t0, rt);
opn = "lb";
break;
case OPC_SB:
save_cpu_state(ctx, 0);
gen_load_gpr(t1, rt);
- op_ldst_sb(t0, t1, ctx);
+ op_ldst_sb(t1, t0, ctx);
opn = "sb";
break;
case OPC_LBU:
save_cpu_state(ctx, 0);
- op_ldst_lbu(t0, ctx);
+ op_ldst_lbu(t0, t0, ctx);
gen_store_gpr(t0, rt);
opn = "lbu";
break;
case OPC_LWL:
save_cpu_state(ctx, 1);
gen_load_gpr(t1, rt);
- gen_helper_3i(lwl, t1, t0, t1, ctx->mem_idx);
+ gen_helper_3i(lwl, t1, t1, t0, ctx->mem_idx);
gen_store_gpr(t1, rt);
opn = "lwl";
break;
case OPC_SWL:
save_cpu_state(ctx, 1);
gen_load_gpr(t1, rt);
- gen_helper_2i(swl, t0, t1, ctx->mem_idx);
+ gen_helper_2i(swl, t1, t0, ctx->mem_idx);
opn = "swr";
break;
case OPC_LWR:
save_cpu_state(ctx, 1);
gen_load_gpr(t1, rt);
- gen_helper_3i(lwr, t1, t0, t1, ctx->mem_idx);
+ gen_helper_3i(lwr, t1, t1, t0, ctx->mem_idx);
gen_store_gpr(t1, rt);
opn = "lwr";
break;
case OPC_SWR:
save_cpu_state(ctx, 1);
gen_load_gpr(t1, rt);
- gen_helper_2i(swr, t0, t1, ctx->mem_idx);
+ gen_helper_2i(swr, t1, t0, ctx->mem_idx);
opn = "swr";
break;
case OPC_LL:
save_cpu_state(ctx, 0);
- op_ldst_ll(t0, t1, ctx);
+ op_ldst_ll(t0, t0, ctx);
gen_store_gpr(t0, rt);
opn = "ll";
break;
#if defined(TARGET_MIPS64)
case OPC_SCD:
save_cpu_state(ctx, 0);
- op_ldst_scd(t0, t1, ctx);
+ op_ldst_scd(t0, t1, t0, ctx);
opn = "scd";
break;
#endif
case OPC_SC:
save_cpu_state(ctx, 0);
- op_ldst_sc(t0, t1, ctx);
+ op_ldst_sc(t0, t1, t0, ctx);
opn = "sc";
break;
}
case OPC_LWC1:
{
TCGv_i32 fp0 = tcg_temp_new_i32();
- TCGv t1 = tcg_temp_new();
- tcg_gen_qemu_ld32s(t1, t0, ctx->mem_idx);
- tcg_gen_trunc_tl_i32(fp0, t1);
+ tcg_gen_qemu_ld32s(t0, t0, ctx->mem_idx);
+ tcg_gen_trunc_tl_i32(fp0, t0);
gen_store_fpr32(fp0, ft);
- tcg_temp_free(t1);
tcg_temp_free_i32(fp0);
}
opn = "lwc1";
/* rotr is decoded as srl on non-R2 CPUs */
if (env->insn_flags & ISA_MIPS32R2) {
if (uimm != 0) {
- TCGv_i32 r_tmp1 = tcg_temp_new_i32();
+ TCGv_i32 t1 = tcg_temp_new_i32();
- tcg_gen_trunc_tl_i32(r_tmp1, t0);
- tcg_gen_rotri_i32(r_tmp1, r_tmp1, uimm);
- tcg_gen_ext_i32_tl(cpu_gpr[rt], r_tmp1);
- tcg_temp_free_i32(r_tmp1);
+ tcg_gen_trunc_tl_i32(t1, t0);
+ tcg_gen_rotri_i32(t1, t1, uimm);
+ tcg_gen_ext_i32_tl(cpu_gpr[rt], t1);
+ tcg_temp_free_i32(t1);
}
opn = "rotr";
} else {
tcg_temp_free(t2);
tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
tcg_temp_free(t1);
- /* operands of same sign, result different sign */
+ /* operands of different sign, first operand and result different sign */
generate_exception(ctx, EXCP_OVERFLOW);
gen_set_label(l1);
gen_store_gpr(t0, rd);
tcg_temp_free(t2);
tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
tcg_temp_free(t1);
- /* operands of same sign, result different sign */
+ /* operands of different sign, first operand and result different sign */
generate_exception(ctx, EXCP_OVERFLOW);
gen_set_label(l1);
gen_store_gpr(t0, rd);
#ifndef CONFIG_USER_ONLY
/* CP0 (MMU and control) */
-static inline void gen_mfc0_load32 (TCGv t, target_ulong off)
+static inline void gen_mfc0_load32 (TCGv arg, target_ulong off)
{
- TCGv_i32 r_tmp = tcg_temp_new_i32();
+ TCGv_i32 t0 = tcg_temp_new_i32();
- tcg_gen_ld_i32(r_tmp, cpu_env, off);
- tcg_gen_ext_i32_tl(t, r_tmp);
- tcg_temp_free_i32(r_tmp);
+ tcg_gen_ld_i32(t0, cpu_env, off);
+ tcg_gen_ext_i32_tl(arg, t0);
+ tcg_temp_free_i32(t0);
}
-static inline void gen_mfc0_load64 (TCGv t, target_ulong off)
+static inline void gen_mfc0_load64 (TCGv arg, target_ulong off)
{
- tcg_gen_ld_tl(t, cpu_env, off);
- tcg_gen_ext32s_tl(t, t);
+ tcg_gen_ld_tl(arg, cpu_env, off);
+ tcg_gen_ext32s_tl(arg, arg);
}
-static inline void gen_mtc0_store32 (TCGv t, target_ulong off)
+static inline void gen_mtc0_store32 (TCGv arg, target_ulong off)
{
- TCGv_i32 r_tmp = tcg_temp_new_i32();
+ TCGv_i32 t0 = tcg_temp_new_i32();
- tcg_gen_trunc_tl_i32(r_tmp, t);
- tcg_gen_st_i32(r_tmp, cpu_env, off);
- tcg_temp_free_i32(r_tmp);
+ tcg_gen_trunc_tl_i32(t0, arg);
+ tcg_gen_st_i32(t0, cpu_env, off);
+ tcg_temp_free_i32(t0);
}
-static inline void gen_mtc0_store64 (TCGv t, target_ulong off)
+static inline void gen_mtc0_store64 (TCGv arg, target_ulong off)
{
- tcg_gen_ext32s_tl(t, t);
- tcg_gen_st_tl(t, cpu_env, off);
+ tcg_gen_ext32s_tl(arg, arg);
+ tcg_gen_st_tl(arg, cpu_env, off);
}
-static void gen_mfc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int sel)
+static void gen_mfc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int sel)
{
const char *rn = "invalid";
case 0:
switch (sel) {
case 0:
- gen_mfc0_load32(t0, offsetof(CPUState, CP0_Index));
+ gen_mfc0_load32(arg, offsetof(CPUState, CP0_Index));
rn = "Index";
break;
case 1:
check_insn(env, ctx, ASE_MT);
- gen_helper_mfc0_mvpcontrol(t0);
+ gen_helper_mfc0_mvpcontrol(arg);
rn = "MVPControl";
break;
case 2:
check_insn(env, ctx, ASE_MT);
- gen_helper_mfc0_mvpconf0(t0);
+ gen_helper_mfc0_mvpconf0(arg);
rn = "MVPConf0";
break;
case 3:
check_insn(env, ctx, ASE_MT);
- gen_helper_mfc0_mvpconf1(t0);
+ gen_helper_mfc0_mvpconf1(arg);
rn = "MVPConf1";
break;
default:
case 1:
switch (sel) {
case 0:
- gen_helper_mfc0_random(t0);
+ gen_helper_mfc0_random(arg);
rn = "Random";
break;
case 1:
check_insn(env, ctx, ASE_MT);
- gen_mfc0_load32(t0, offsetof(CPUState, CP0_VPEControl));
+ gen_mfc0_load32(arg, offsetof(CPUState, CP0_VPEControl));
rn = "VPEControl";
break;
case 2:
check_insn(env, ctx, ASE_MT);
- gen_mfc0_load32(t0, offsetof(CPUState, CP0_VPEConf0));
+ gen_mfc0_load32(arg, offsetof(CPUState, CP0_VPEConf0));
rn = "VPEConf0";
break;
case 3:
check_insn(env, ctx, ASE_MT);
- gen_mfc0_load32(t0, offsetof(CPUState, CP0_VPEConf1));
+ gen_mfc0_load32(arg, offsetof(CPUState, CP0_VPEConf1));
rn = "VPEConf1";
break;
case 4:
check_insn(env, ctx, ASE_MT);
- gen_mfc0_load64(t0, offsetof(CPUState, CP0_YQMask));
+ gen_mfc0_load64(arg, offsetof(CPUState, CP0_YQMask));
rn = "YQMask";
break;
case 5:
check_insn(env, ctx, ASE_MT);
- gen_mfc0_load64(t0, offsetof(CPUState, CP0_VPESchedule));
+ gen_mfc0_load64(arg, offsetof(CPUState, CP0_VPESchedule));
rn = "VPESchedule";
break;
case 6:
check_insn(env, ctx, ASE_MT);
- gen_mfc0_load64(t0, offsetof(CPUState, CP0_VPEScheFBack));
+ gen_mfc0_load64(arg, offsetof(CPUState, CP0_VPEScheFBack));
rn = "VPEScheFBack";
break;
case 7:
check_insn(env, ctx, ASE_MT);
- gen_mfc0_load32(t0, offsetof(CPUState, CP0_VPEOpt));
+ gen_mfc0_load32(arg, offsetof(CPUState, CP0_VPEOpt));
rn = "VPEOpt";
break;
default:
case 2:
switch (sel) {
case 0:
- tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_EntryLo0));
- tcg_gen_ext32s_tl(t0, t0);
+ tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_EntryLo0));
+ tcg_gen_ext32s_tl(arg, arg);
rn = "EntryLo0";
break;
case 1:
check_insn(env, ctx, ASE_MT);
- gen_helper_mfc0_tcstatus(t0);
+ gen_helper_mfc0_tcstatus(arg);
rn = "TCStatus";
break;
case 2:
check_insn(env, ctx, ASE_MT);
- gen_helper_mfc0_tcbind(t0);
+ gen_helper_mfc0_tcbind(arg);
rn = "TCBind";
break;
case 3:
check_insn(env, ctx, ASE_MT);
- gen_helper_mfc0_tcrestart(t0);
+ gen_helper_mfc0_tcrestart(arg);
rn = "TCRestart";
break;
case 4:
check_insn(env, ctx, ASE_MT);
- gen_helper_mfc0_tchalt(t0);
+ gen_helper_mfc0_tchalt(arg);
rn = "TCHalt";
break;
case 5:
check_insn(env, ctx, ASE_MT);
- gen_helper_mfc0_tccontext(t0);
+ gen_helper_mfc0_tccontext(arg);
rn = "TCContext";
break;
case 6:
check_insn(env, ctx, ASE_MT);
- gen_helper_mfc0_tcschedule(t0);
+ gen_helper_mfc0_tcschedule(arg);
rn = "TCSchedule";
break;
case 7:
check_insn(env, ctx, ASE_MT);
- gen_helper_mfc0_tcschefback(t0);
+ gen_helper_mfc0_tcschefback(arg);
rn = "TCScheFBack";
break;
default:
case 3:
switch (sel) {
case 0:
- tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_EntryLo1));
- tcg_gen_ext32s_tl(t0, t0);
+ tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_EntryLo1));
+ tcg_gen_ext32s_tl(arg, arg);
rn = "EntryLo1";
break;
default:
case 4:
switch (sel) {
case 0:
- tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_Context));
- tcg_gen_ext32s_tl(t0, t0);
+ tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_Context));
+ tcg_gen_ext32s_tl(arg, arg);
rn = "Context";
break;
case 1:
-// gen_helper_mfc0_contextconfig(t0); /* SmartMIPS ASE */
+// gen_helper_mfc0_contextconfig(arg); /* SmartMIPS ASE */
rn = "ContextConfig";
// break;
default:
case 5:
switch (sel) {
case 0:
- gen_mfc0_load32(t0, offsetof(CPUState, CP0_PageMask));
+ gen_mfc0_load32(arg, offsetof(CPUState, CP0_PageMask));
rn = "PageMask";
break;
case 1:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_mfc0_load32(t0, offsetof(CPUState, CP0_PageGrain));
+ gen_mfc0_load32(arg, offsetof(CPUState, CP0_PageGrain));
rn = "PageGrain";
break;
default:
case 6:
switch (sel) {
case 0:
- gen_mfc0_load32(t0, offsetof(CPUState, CP0_Wired));
+ gen_mfc0_load32(arg, offsetof(CPUState, CP0_Wired));
rn = "Wired";
break;
case 1:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_mfc0_load32(t0, offsetof(CPUState, CP0_SRSConf0));
+ gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf0));
rn = "SRSConf0";
break;
case 2:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_mfc0_load32(t0, offsetof(CPUState, CP0_SRSConf1));
+ gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf1));
rn = "SRSConf1";
break;
case 3:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_mfc0_load32(t0, offsetof(CPUState, CP0_SRSConf2));
+ gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf2));
rn = "SRSConf2";
break;
case 4:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_mfc0_load32(t0, offsetof(CPUState, CP0_SRSConf3));
+ gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf3));
rn = "SRSConf3";
break;
case 5:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_mfc0_load32(t0, offsetof(CPUState, CP0_SRSConf4));
+ gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf4));
rn = "SRSConf4";
break;
default:
switch (sel) {
case 0:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_mfc0_load32(t0, offsetof(CPUState, CP0_HWREna));
+ gen_mfc0_load32(arg, offsetof(CPUState, CP0_HWREna));
rn = "HWREna";
break;
default:
case 8:
switch (sel) {
case 0:
- tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_BadVAddr));
- tcg_gen_ext32s_tl(t0, t0);
+ tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_BadVAddr));
+ tcg_gen_ext32s_tl(arg, arg);
rn = "BadVAddr";
break;
default:
/* Mark as an IO operation because we read the time. */
if (use_icount)
gen_io_start();
- gen_helper_mfc0_count(t0);
+ gen_helper_mfc0_count(arg);
if (use_icount) {
gen_io_end();
ctx->bstate = BS_STOP;
case 10:
switch (sel) {
case 0:
- tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_EntryHi));
- tcg_gen_ext32s_tl(t0, t0);
+ tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_EntryHi));
+ tcg_gen_ext32s_tl(arg, arg);
rn = "EntryHi";
break;
default:
case 11:
switch (sel) {
case 0:
- gen_mfc0_load32(t0, offsetof(CPUState, CP0_Compare));
+ gen_mfc0_load32(arg, offsetof(CPUState, CP0_Compare));
rn = "Compare";
break;
/* 6,7 are implementation dependent */
case 12:
switch (sel) {
case 0:
- gen_mfc0_load32(t0, offsetof(CPUState, CP0_Status));
+ gen_mfc0_load32(arg, offsetof(CPUState, CP0_Status));
rn = "Status";
break;
case 1:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_mfc0_load32(t0, offsetof(CPUState, CP0_IntCtl));
+ gen_mfc0_load32(arg, offsetof(CPUState, CP0_IntCtl));
rn = "IntCtl";
break;
case 2:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_mfc0_load32(t0, offsetof(CPUState, CP0_SRSCtl));
+ gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSCtl));
rn = "SRSCtl";
break;
case 3:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_mfc0_load32(t0, offsetof(CPUState, CP0_SRSMap));
+ gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSMap));
rn = "SRSMap";
break;
default:
case 13:
switch (sel) {
case 0:
- gen_mfc0_load32(t0, offsetof(CPUState, CP0_Cause));
+ gen_mfc0_load32(arg, offsetof(CPUState, CP0_Cause));
rn = "Cause";
break;
default:
case 14:
switch (sel) {
case 0:
- tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_EPC));
- tcg_gen_ext32s_tl(t0, t0);
+ tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_EPC));
+ tcg_gen_ext32s_tl(arg, arg);
rn = "EPC";
break;
default:
case 15:
switch (sel) {
case 0:
- gen_mfc0_load32(t0, offsetof(CPUState, CP0_PRid));
+ gen_mfc0_load32(arg, offsetof(CPUState, CP0_PRid));
rn = "PRid";
break;
case 1:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_mfc0_load32(t0, offsetof(CPUState, CP0_EBase));
+ gen_mfc0_load32(arg, offsetof(CPUState, CP0_EBase));
rn = "EBase";
break;
default:
case 16:
switch (sel) {
case 0:
- gen_mfc0_load32(t0, offsetof(CPUState, CP0_Config0));
+ gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config0));
rn = "Config";
break;
case 1:
- gen_mfc0_load32(t0, offsetof(CPUState, CP0_Config1));
+ gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config1));
rn = "Config1";
break;
case 2:
- gen_mfc0_load32(t0, offsetof(CPUState, CP0_Config2));
+ gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config2));
rn = "Config2";
break;
case 3:
- gen_mfc0_load32(t0, offsetof(CPUState, CP0_Config3));
+ gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config3));
rn = "Config3";
break;
/* 4,5 are reserved */
/* 6,7 are implementation dependent */
case 6:
- gen_mfc0_load32(t0, offsetof(CPUState, CP0_Config6));
+ gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config6));
rn = "Config6";
break;
case 7:
- gen_mfc0_load32(t0, offsetof(CPUState, CP0_Config7));
+ gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config7));
rn = "Config7";
break;
default:
case 17:
switch (sel) {
case 0:
- gen_helper_mfc0_lladdr(t0);
+ gen_helper_mfc0_lladdr(arg);
rn = "LLAddr";
break;
default:
case 18:
switch (sel) {
case 0 ... 7:
- gen_helper_1i(mfc0_watchlo, t0, sel);
+ gen_helper_1i(mfc0_watchlo, arg, sel);
rn = "WatchLo";
break;
default:
case 19:
switch (sel) {
case 0 ...7:
- gen_helper_1i(mfc0_watchhi, t0, sel);
+ gen_helper_1i(mfc0_watchhi, arg, sel);
rn = "WatchHi";
break;
default:
case 0:
#if defined(TARGET_MIPS64)
check_insn(env, ctx, ISA_MIPS3);
- tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_XContext));
- tcg_gen_ext32s_tl(t0, t0);
+ tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_XContext));
+ tcg_gen_ext32s_tl(arg, arg);
rn = "XContext";
break;
#endif
/* Officially reserved, but sel 0 is used for R1x000 framemask */
switch (sel) {
case 0:
- gen_mfc0_load32(t0, offsetof(CPUState, CP0_Framemask));
+ gen_mfc0_load32(arg, offsetof(CPUState, CP0_Framemask));
rn = "Framemask";
break;
default:
}
break;
case 22:
- tcg_gen_movi_tl(t0, 0); /* unimplemented */
+ tcg_gen_movi_tl(arg, 0); /* unimplemented */
rn = "'Diagnostic"; /* implementation dependent */
break;
case 23:
switch (sel) {
case 0:
- gen_helper_mfc0_debug(t0); /* EJTAG support */
+ gen_helper_mfc0_debug(arg); /* EJTAG support */
rn = "Debug";
break;
case 1:
-// gen_helper_mfc0_tracecontrol(t0); /* PDtrace support */
+// gen_helper_mfc0_tracecontrol(arg); /* PDtrace support */
rn = "TraceControl";
// break;
case 2:
-// gen_helper_mfc0_tracecontrol2(t0); /* PDtrace support */
+// gen_helper_mfc0_tracecontrol2(arg); /* PDtrace support */
rn = "TraceControl2";
// break;
case 3:
-// gen_helper_mfc0_usertracedata(t0); /* PDtrace support */
+// gen_helper_mfc0_usertracedata(arg); /* PDtrace support */
rn = "UserTraceData";
// break;
case 4:
-// gen_helper_mfc0_tracebpc(t0); /* PDtrace support */
+// gen_helper_mfc0_tracebpc(arg); /* PDtrace support */
rn = "TraceBPC";
// break;
default:
switch (sel) {
case 0:
/* EJTAG support */
- tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_DEPC));
- tcg_gen_ext32s_tl(t0, t0);
+ tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_DEPC));
+ tcg_gen_ext32s_tl(arg, arg);
rn = "DEPC";
break;
default:
case 25:
switch (sel) {
case 0:
- gen_mfc0_load32(t0, offsetof(CPUState, CP0_Performance0));
+ gen_mfc0_load32(arg, offsetof(CPUState, CP0_Performance0));
rn = "Performance0";
break;
case 1:
-// gen_helper_mfc0_performance1(t0);
+// gen_helper_mfc0_performance1(arg);
rn = "Performance1";
// break;
case 2:
-// gen_helper_mfc0_performance2(t0);
+// gen_helper_mfc0_performance2(arg);
rn = "Performance2";
// break;
case 3:
-// gen_helper_mfc0_performance3(t0);
+// gen_helper_mfc0_performance3(arg);
rn = "Performance3";
// break;
case 4:
-// gen_helper_mfc0_performance4(t0);
+// gen_helper_mfc0_performance4(arg);
rn = "Performance4";
// break;
case 5:
-// gen_helper_mfc0_performance5(t0);
+// gen_helper_mfc0_performance5(arg);
rn = "Performance5";
// break;
case 6:
-// gen_helper_mfc0_performance6(t0);
+// gen_helper_mfc0_performance6(arg);
rn = "Performance6";
// break;
case 7:
-// gen_helper_mfc0_performance7(t0);
+// gen_helper_mfc0_performance7(arg);
rn = "Performance7";
// break;
default:
}
break;
case 26:
- tcg_gen_movi_tl(t0, 0); /* unimplemented */
+ tcg_gen_movi_tl(arg, 0); /* unimplemented */
rn = "ECC";
break;
case 27:
switch (sel) {
case 0 ... 3:
- tcg_gen_movi_tl(t0, 0); /* unimplemented */
+ tcg_gen_movi_tl(arg, 0); /* unimplemented */
rn = "CacheErr";
break;
default:
case 2:
case 4:
case 6:
- gen_mfc0_load32(t0, offsetof(CPUState, CP0_TagLo));
+ gen_mfc0_load32(arg, offsetof(CPUState, CP0_TagLo));
rn = "TagLo";
break;
case 1:
case 3:
case 5:
case 7:
- gen_mfc0_load32(t0, offsetof(CPUState, CP0_DataLo));
+ gen_mfc0_load32(arg, offsetof(CPUState, CP0_DataLo));
rn = "DataLo";
break;
default:
case 2:
case 4:
case 6:
- gen_mfc0_load32(t0, offsetof(CPUState, CP0_TagHi));
+ gen_mfc0_load32(arg, offsetof(CPUState, CP0_TagHi));
rn = "TagHi";
break;
case 1:
case 3:
case 5:
case 7:
- gen_mfc0_load32(t0, offsetof(CPUState, CP0_DataHi));
+ gen_mfc0_load32(arg, offsetof(CPUState, CP0_DataHi));
rn = "DataHi";
break;
default:
case 30:
switch (sel) {
case 0:
- tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_ErrorEPC));
- tcg_gen_ext32s_tl(t0, t0);
+ tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_ErrorEPC));
+ tcg_gen_ext32s_tl(arg, arg);
rn = "ErrorEPC";
break;
default:
switch (sel) {
case 0:
/* EJTAG support */
- gen_mfc0_load32(t0, offsetof(CPUState, CP0_DESAVE));
+ gen_mfc0_load32(arg, offsetof(CPUState, CP0_DESAVE));
rn = "DESAVE";
break;
default:
generate_exception(ctx, EXCP_RI);
}
-static void gen_mtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int sel)
+static void gen_mtc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int sel)
{
const char *rn = "invalid";
case 0:
switch (sel) {
case 0:
- gen_helper_mtc0_index(t0);
+ gen_helper_mtc0_index(arg);
rn = "Index";
break;
case 1:
check_insn(env, ctx, ASE_MT);
- gen_helper_mtc0_mvpcontrol(t0);
+ gen_helper_mtc0_mvpcontrol(arg);
rn = "MVPControl";
break;
case 2:
break;
case 1:
check_insn(env, ctx, ASE_MT);
- gen_helper_mtc0_vpecontrol(t0);
+ gen_helper_mtc0_vpecontrol(arg);
rn = "VPEControl";
break;
case 2:
check_insn(env, ctx, ASE_MT);
- gen_helper_mtc0_vpeconf0(t0);
+ gen_helper_mtc0_vpeconf0(arg);
rn = "VPEConf0";
break;
case 3:
check_insn(env, ctx, ASE_MT);
- gen_helper_mtc0_vpeconf1(t0);
+ gen_helper_mtc0_vpeconf1(arg);
rn = "VPEConf1";
break;
case 4:
check_insn(env, ctx, ASE_MT);
- gen_helper_mtc0_yqmask(t0);
+ gen_helper_mtc0_yqmask(arg);
rn = "YQMask";
break;
case 5:
check_insn(env, ctx, ASE_MT);
- gen_mtc0_store64(t0, offsetof(CPUState, CP0_VPESchedule));
+ gen_mtc0_store64(arg, offsetof(CPUState, CP0_VPESchedule));
rn = "VPESchedule";
break;
case 6:
check_insn(env, ctx, ASE_MT);
- gen_mtc0_store64(t0, offsetof(CPUState, CP0_VPEScheFBack));
+ gen_mtc0_store64(arg, offsetof(CPUState, CP0_VPEScheFBack));
rn = "VPEScheFBack";
break;
case 7:
check_insn(env, ctx, ASE_MT);
- gen_helper_mtc0_vpeopt(t0);
+ gen_helper_mtc0_vpeopt(arg);
rn = "VPEOpt";
break;
default:
case 2:
switch (sel) {
case 0:
- gen_helper_mtc0_entrylo0(t0);
+ gen_helper_mtc0_entrylo0(arg);
rn = "EntryLo0";
break;
case 1:
check_insn(env, ctx, ASE_MT);
- gen_helper_mtc0_tcstatus(t0);
+ gen_helper_mtc0_tcstatus(arg);
rn = "TCStatus";
break;
case 2:
check_insn(env, ctx, ASE_MT);
- gen_helper_mtc0_tcbind(t0);
+ gen_helper_mtc0_tcbind(arg);
rn = "TCBind";
break;
case 3:
check_insn(env, ctx, ASE_MT);
- gen_helper_mtc0_tcrestart(t0);
+ gen_helper_mtc0_tcrestart(arg);
rn = "TCRestart";
break;
case 4:
check_insn(env, ctx, ASE_MT);
- gen_helper_mtc0_tchalt(t0);
+ gen_helper_mtc0_tchalt(arg);
rn = "TCHalt";
break;
case 5:
check_insn(env, ctx, ASE_MT);
- gen_helper_mtc0_tccontext(t0);
+ gen_helper_mtc0_tccontext(arg);
rn = "TCContext";
break;
case 6:
check_insn(env, ctx, ASE_MT);
- gen_helper_mtc0_tcschedule(t0);
+ gen_helper_mtc0_tcschedule(arg);
rn = "TCSchedule";
break;
case 7:
check_insn(env, ctx, ASE_MT);
- gen_helper_mtc0_tcschefback(t0);
+ gen_helper_mtc0_tcschefback(arg);
rn = "TCScheFBack";
break;
default:
case 3:
switch (sel) {
case 0:
- gen_helper_mtc0_entrylo1(t0);
+ gen_helper_mtc0_entrylo1(arg);
rn = "EntryLo1";
break;
default:
case 4:
switch (sel) {
case 0:
- gen_helper_mtc0_context(t0);
+ gen_helper_mtc0_context(arg);
rn = "Context";
break;
case 1:
-// gen_helper_mtc0_contextconfig(t0); /* SmartMIPS ASE */
+// gen_helper_mtc0_contextconfig(arg); /* SmartMIPS ASE */
rn = "ContextConfig";
// break;
default:
case 5:
switch (sel) {
case 0:
- gen_helper_mtc0_pagemask(t0);
+ gen_helper_mtc0_pagemask(arg);
rn = "PageMask";
break;
case 1:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_helper_mtc0_pagegrain(t0);
+ gen_helper_mtc0_pagegrain(arg);
rn = "PageGrain";
break;
default:
case 6:
switch (sel) {
case 0:
- gen_helper_mtc0_wired(t0);
+ gen_helper_mtc0_wired(arg);
rn = "Wired";
break;
case 1:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_helper_mtc0_srsconf0(t0);
+ gen_helper_mtc0_srsconf0(arg);
rn = "SRSConf0";
break;
case 2:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_helper_mtc0_srsconf1(t0);
+ gen_helper_mtc0_srsconf1(arg);
rn = "SRSConf1";
break;
case 3:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_helper_mtc0_srsconf2(t0);
+ gen_helper_mtc0_srsconf2(arg);
rn = "SRSConf2";
break;
case 4:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_helper_mtc0_srsconf3(t0);
+ gen_helper_mtc0_srsconf3(arg);
rn = "SRSConf3";
break;
case 5:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_helper_mtc0_srsconf4(t0);
+ gen_helper_mtc0_srsconf4(arg);
rn = "SRSConf4";
break;
default:
switch (sel) {
case 0:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_helper_mtc0_hwrena(t0);
+ gen_helper_mtc0_hwrena(arg);
rn = "HWREna";
break;
default:
case 9:
switch (sel) {
case 0:
- gen_helper_mtc0_count(t0);
+ gen_helper_mtc0_count(arg);
rn = "Count";
break;
/* 6,7 are implementation dependent */
case 10:
switch (sel) {
case 0:
- gen_helper_mtc0_entryhi(t0);
+ gen_helper_mtc0_entryhi(arg);
rn = "EntryHi";
break;
default:
case 11:
switch (sel) {
case 0:
- gen_helper_mtc0_compare(t0);
+ gen_helper_mtc0_compare(arg);
rn = "Compare";
break;
/* 6,7 are implementation dependent */
case 12:
switch (sel) {
case 0:
- gen_helper_mtc0_status(t0);
+ save_cpu_state(ctx, 1);
+ gen_helper_mtc0_status(arg);
/* BS_STOP isn't good enough here, hflags may have changed. */
gen_save_pc(ctx->pc + 4);
ctx->bstate = BS_EXCP;
break;
case 1:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_helper_mtc0_intctl(t0);
+ gen_helper_mtc0_intctl(arg);
/* Stop translation as we may have switched the execution mode */
ctx->bstate = BS_STOP;
rn = "IntCtl";
break;
case 2:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_helper_mtc0_srsctl(t0);
+ gen_helper_mtc0_srsctl(arg);
/* Stop translation as we may have switched the execution mode */
ctx->bstate = BS_STOP;
rn = "SRSCtl";
break;
case 3:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_mtc0_store32(t0, offsetof(CPUState, CP0_SRSMap));
+ gen_mtc0_store32(arg, offsetof(CPUState, CP0_SRSMap));
/* Stop translation as we may have switched the execution mode */
ctx->bstate = BS_STOP;
rn = "SRSMap";
case 13:
switch (sel) {
case 0:
- gen_helper_mtc0_cause(t0);
+ save_cpu_state(ctx, 1);
+ gen_helper_mtc0_cause(arg);
rn = "Cause";
break;
default:
case 14:
switch (sel) {
case 0:
- gen_mtc0_store64(t0, offsetof(CPUState, CP0_EPC));
+ gen_mtc0_store64(arg, offsetof(CPUState, CP0_EPC));
rn = "EPC";
break;
default:
break;
case 1:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_helper_mtc0_ebase(t0);
+ gen_helper_mtc0_ebase(arg);
rn = "EBase";
break;
default:
case 16:
switch (sel) {
case 0:
- gen_helper_mtc0_config0(t0);
+ gen_helper_mtc0_config0(arg);
rn = "Config";
/* Stop translation as we may have switched the execution mode */
ctx->bstate = BS_STOP;
rn = "Config1";
break;
case 2:
- gen_helper_mtc0_config2(t0);
+ gen_helper_mtc0_config2(arg);
rn = "Config2";
/* Stop translation as we may have switched the execution mode */
ctx->bstate = BS_STOP;
case 18:
switch (sel) {
case 0 ... 7:
- gen_helper_1i(mtc0_watchlo, t0, sel);
+ gen_helper_1i(mtc0_watchlo, arg, sel);
rn = "WatchLo";
break;
default:
case 19:
switch (sel) {
case 0 ... 7:
- gen_helper_1i(mtc0_watchhi, t0, sel);
+ gen_helper_1i(mtc0_watchhi, arg, sel);
rn = "WatchHi";
break;
default:
case 0:
#if defined(TARGET_MIPS64)
check_insn(env, ctx, ISA_MIPS3);
- gen_helper_mtc0_xcontext(t0);
+ gen_helper_mtc0_xcontext(arg);
rn = "XContext";
break;
#endif
/* Officially reserved, but sel 0 is used for R1x000 framemask */
switch (sel) {
case 0:
- gen_helper_mtc0_framemask(t0);
+ gen_helper_mtc0_framemask(arg);
rn = "Framemask";
break;
default:
case 23:
switch (sel) {
case 0:
- gen_helper_mtc0_debug(t0); /* EJTAG support */
+ gen_helper_mtc0_debug(arg); /* EJTAG support */
/* BS_STOP isn't good enough here, hflags may have changed. */
gen_save_pc(ctx->pc + 4);
ctx->bstate = BS_EXCP;
rn = "Debug";
break;
case 1:
-// gen_helper_mtc0_tracecontrol(t0); /* PDtrace support */
+// gen_helper_mtc0_tracecontrol(arg); /* PDtrace support */
rn = "TraceControl";
/* Stop translation as we may have switched the execution mode */
ctx->bstate = BS_STOP;
// break;
case 2:
-// gen_helper_mtc0_tracecontrol2(t0); /* PDtrace support */
+// gen_helper_mtc0_tracecontrol2(arg); /* PDtrace support */
rn = "TraceControl2";
/* Stop translation as we may have switched the execution mode */
ctx->bstate = BS_STOP;
case 3:
/* Stop translation as we may have switched the execution mode */
ctx->bstate = BS_STOP;
-// gen_helper_mtc0_usertracedata(t0); /* PDtrace support */
+// gen_helper_mtc0_usertracedata(arg); /* PDtrace support */
rn = "UserTraceData";
/* Stop translation as we may have switched the execution mode */
ctx->bstate = BS_STOP;
// break;
case 4:
-// gen_helper_mtc0_tracebpc(t0); /* PDtrace support */
+// gen_helper_mtc0_tracebpc(arg); /* PDtrace support */
/* Stop translation as we may have switched the execution mode */
ctx->bstate = BS_STOP;
rn = "TraceBPC";
switch (sel) {
case 0:
/* EJTAG support */
- gen_mtc0_store64(t0, offsetof(CPUState, CP0_DEPC));
+ gen_mtc0_store64(arg, offsetof(CPUState, CP0_DEPC));
rn = "DEPC";
break;
default:
case 25:
switch (sel) {
case 0:
- gen_helper_mtc0_performance0(t0);
+ gen_helper_mtc0_performance0(arg);
rn = "Performance0";
break;
case 1:
-// gen_helper_mtc0_performance1(t0);
+// gen_helper_mtc0_performance1(arg);
rn = "Performance1";
// break;
case 2:
-// gen_helper_mtc0_performance2(t0);
+// gen_helper_mtc0_performance2(arg);
rn = "Performance2";
// break;
case 3:
-// gen_helper_mtc0_performance3(t0);
+// gen_helper_mtc0_performance3(arg);
rn = "Performance3";
// break;
case 4:
-// gen_helper_mtc0_performance4(t0);
+// gen_helper_mtc0_performance4(arg);
rn = "Performance4";
// break;
case 5:
-// gen_helper_mtc0_performance5(t0);
+// gen_helper_mtc0_performance5(arg);
rn = "Performance5";
// break;
case 6:
-// gen_helper_mtc0_performance6(t0);
+// gen_helper_mtc0_performance6(arg);
rn = "Performance6";
// break;
case 7:
-// gen_helper_mtc0_performance7(t0);
+// gen_helper_mtc0_performance7(arg);
rn = "Performance7";
// break;
default:
case 2:
case 4:
case 6:
- gen_helper_mtc0_taglo(t0);
+ gen_helper_mtc0_taglo(arg);
rn = "TagLo";
break;
case 1:
case 3:
case 5:
case 7:
- gen_helper_mtc0_datalo(t0);
+ gen_helper_mtc0_datalo(arg);
rn = "DataLo";
break;
default:
case 2:
case 4:
case 6:
- gen_helper_mtc0_taghi(t0);
+ gen_helper_mtc0_taghi(arg);
rn = "TagHi";
break;
case 1:
case 3:
case 5:
case 7:
- gen_helper_mtc0_datahi(t0);
+ gen_helper_mtc0_datahi(arg);
rn = "DataHi";
break;
default:
case 30:
switch (sel) {
case 0:
- gen_mtc0_store64(t0, offsetof(CPUState, CP0_ErrorEPC));
+ gen_mtc0_store64(arg, offsetof(CPUState, CP0_ErrorEPC));
rn = "ErrorEPC";
break;
default:
switch (sel) {
case 0:
/* EJTAG support */
- gen_mtc0_store32(t0, offsetof(CPUState, CP0_DESAVE));
+ gen_mtc0_store32(arg, offsetof(CPUState, CP0_DESAVE));
rn = "DESAVE";
break;
default:
}
#if defined(TARGET_MIPS64)
-static void gen_dmfc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int sel)
+static void gen_dmfc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int sel)
{
const char *rn = "invalid";
case 0:
switch (sel) {
case 0:
- gen_mfc0_load32(t0, offsetof(CPUState, CP0_Index));
+ gen_mfc0_load32(arg, offsetof(CPUState, CP0_Index));
rn = "Index";
break;
case 1:
check_insn(env, ctx, ASE_MT);
- gen_helper_mfc0_mvpcontrol(t0);
+ gen_helper_mfc0_mvpcontrol(arg);
rn = "MVPControl";
break;
case 2:
check_insn(env, ctx, ASE_MT);
- gen_helper_mfc0_mvpconf0(t0);
+ gen_helper_mfc0_mvpconf0(arg);
rn = "MVPConf0";
break;
case 3:
check_insn(env, ctx, ASE_MT);
- gen_helper_mfc0_mvpconf1(t0);
+ gen_helper_mfc0_mvpconf1(arg);
rn = "MVPConf1";
break;
default:
case 1:
switch (sel) {
case 0:
- gen_helper_mfc0_random(t0);
+ gen_helper_mfc0_random(arg);
rn = "Random";
break;
case 1:
check_insn(env, ctx, ASE_MT);
- gen_mfc0_load32(t0, offsetof(CPUState, CP0_VPEControl));
+ gen_mfc0_load32(arg, offsetof(CPUState, CP0_VPEControl));
rn = "VPEControl";
break;
case 2:
check_insn(env, ctx, ASE_MT);
- gen_mfc0_load32(t0, offsetof(CPUState, CP0_VPEConf0));
+ gen_mfc0_load32(arg, offsetof(CPUState, CP0_VPEConf0));
rn = "VPEConf0";
break;
case 3:
check_insn(env, ctx, ASE_MT);
- gen_mfc0_load32(t0, offsetof(CPUState, CP0_VPEConf1));
+ gen_mfc0_load32(arg, offsetof(CPUState, CP0_VPEConf1));
rn = "VPEConf1";
break;
case 4:
check_insn(env, ctx, ASE_MT);
- tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_YQMask));
+ tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_YQMask));
rn = "YQMask";
break;
case 5:
check_insn(env, ctx, ASE_MT);
- tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_VPESchedule));
+ tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_VPESchedule));
rn = "VPESchedule";
break;
case 6:
check_insn(env, ctx, ASE_MT);
- tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_VPEScheFBack));
+ tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_VPEScheFBack));
rn = "VPEScheFBack";
break;
case 7:
check_insn(env, ctx, ASE_MT);
- gen_mfc0_load32(t0, offsetof(CPUState, CP0_VPEOpt));
+ gen_mfc0_load32(arg, offsetof(CPUState, CP0_VPEOpt));
rn = "VPEOpt";
break;
default:
case 2:
switch (sel) {
case 0:
- tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_EntryLo0));
+ tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_EntryLo0));
rn = "EntryLo0";
break;
case 1:
check_insn(env, ctx, ASE_MT);
- gen_helper_mfc0_tcstatus(t0);
+ gen_helper_mfc0_tcstatus(arg);
rn = "TCStatus";
break;
case 2:
check_insn(env, ctx, ASE_MT);
- gen_helper_mfc0_tcbind(t0);
+ gen_helper_mfc0_tcbind(arg);
rn = "TCBind";
break;
case 3:
check_insn(env, ctx, ASE_MT);
- gen_helper_dmfc0_tcrestart(t0);
+ gen_helper_dmfc0_tcrestart(arg);
rn = "TCRestart";
break;
case 4:
check_insn(env, ctx, ASE_MT);
- gen_helper_dmfc0_tchalt(t0);
+ gen_helper_dmfc0_tchalt(arg);
rn = "TCHalt";
break;
case 5:
check_insn(env, ctx, ASE_MT);
- gen_helper_dmfc0_tccontext(t0);
+ gen_helper_dmfc0_tccontext(arg);
rn = "TCContext";
break;
case 6:
check_insn(env, ctx, ASE_MT);
- gen_helper_dmfc0_tcschedule(t0);
+ gen_helper_dmfc0_tcschedule(arg);
rn = "TCSchedule";
break;
case 7:
check_insn(env, ctx, ASE_MT);
- gen_helper_dmfc0_tcschefback(t0);
+ gen_helper_dmfc0_tcschefback(arg);
rn = "TCScheFBack";
break;
default:
case 3:
switch (sel) {
case 0:
- tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_EntryLo1));
+ tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_EntryLo1));
rn = "EntryLo1";
break;
default:
case 4:
switch (sel) {
case 0:
- tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_Context));
+ tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_Context));
rn = "Context";
break;
case 1:
-// gen_helper_dmfc0_contextconfig(t0); /* SmartMIPS ASE */
+// gen_helper_dmfc0_contextconfig(arg); /* SmartMIPS ASE */
rn = "ContextConfig";
// break;
default:
case 5:
switch (sel) {
case 0:
- gen_mfc0_load32(t0, offsetof(CPUState, CP0_PageMask));
+ gen_mfc0_load32(arg, offsetof(CPUState, CP0_PageMask));
rn = "PageMask";
break;
case 1:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_mfc0_load32(t0, offsetof(CPUState, CP0_PageGrain));
+ gen_mfc0_load32(arg, offsetof(CPUState, CP0_PageGrain));
rn = "PageGrain";
break;
default:
case 6:
switch (sel) {
case 0:
- gen_mfc0_load32(t0, offsetof(CPUState, CP0_Wired));
+ gen_mfc0_load32(arg, offsetof(CPUState, CP0_Wired));
rn = "Wired";
break;
case 1:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_mfc0_load32(t0, offsetof(CPUState, CP0_SRSConf0));
+ gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf0));
rn = "SRSConf0";
break;
case 2:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_mfc0_load32(t0, offsetof(CPUState, CP0_SRSConf1));
+ gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf1));
rn = "SRSConf1";
break;
case 3:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_mfc0_load32(t0, offsetof(CPUState, CP0_SRSConf2));
+ gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf2));
rn = "SRSConf2";
break;
case 4:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_mfc0_load32(t0, offsetof(CPUState, CP0_SRSConf3));
+ gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf3));
rn = "SRSConf3";
break;
case 5:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_mfc0_load32(t0, offsetof(CPUState, CP0_SRSConf4));
+ gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf4));
rn = "SRSConf4";
break;
default:
switch (sel) {
case 0:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_mfc0_load32(t0, offsetof(CPUState, CP0_HWREna));
+ gen_mfc0_load32(arg, offsetof(CPUState, CP0_HWREna));
rn = "HWREna";
break;
default:
case 8:
switch (sel) {
case 0:
- tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_BadVAddr));
+ tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_BadVAddr));
rn = "BadVAddr";
break;
default:
/* Mark as an IO operation because we read the time. */
if (use_icount)
gen_io_start();
- gen_helper_mfc0_count(t0);
+ gen_helper_mfc0_count(arg);
if (use_icount) {
gen_io_end();
ctx->bstate = BS_STOP;
case 10:
switch (sel) {
case 0:
- tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_EntryHi));
+ tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_EntryHi));
rn = "EntryHi";
break;
default:
case 11:
switch (sel) {
case 0:
- gen_mfc0_load32(t0, offsetof(CPUState, CP0_Compare));
+ gen_mfc0_load32(arg, offsetof(CPUState, CP0_Compare));
rn = "Compare";
break;
/* 6,7 are implementation dependent */
case 12:
switch (sel) {
case 0:
- gen_mfc0_load32(t0, offsetof(CPUState, CP0_Status));
+ gen_mfc0_load32(arg, offsetof(CPUState, CP0_Status));
rn = "Status";
break;
case 1:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_mfc0_load32(t0, offsetof(CPUState, CP0_IntCtl));
+ gen_mfc0_load32(arg, offsetof(CPUState, CP0_IntCtl));
rn = "IntCtl";
break;
case 2:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_mfc0_load32(t0, offsetof(CPUState, CP0_SRSCtl));
+ gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSCtl));
rn = "SRSCtl";
break;
case 3:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_mfc0_load32(t0, offsetof(CPUState, CP0_SRSMap));
+ gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSMap));
rn = "SRSMap";
break;
default:
case 13:
switch (sel) {
case 0:
- gen_mfc0_load32(t0, offsetof(CPUState, CP0_Cause));
+ gen_mfc0_load32(arg, offsetof(CPUState, CP0_Cause));
rn = "Cause";
break;
default:
case 14:
switch (sel) {
case 0:
- tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_EPC));
+ tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_EPC));
rn = "EPC";
break;
default:
case 15:
switch (sel) {
case 0:
- gen_mfc0_load32(t0, offsetof(CPUState, CP0_PRid));
+ gen_mfc0_load32(arg, offsetof(CPUState, CP0_PRid));
rn = "PRid";
break;
case 1:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_mfc0_load32(t0, offsetof(CPUState, CP0_EBase));
+ gen_mfc0_load32(arg, offsetof(CPUState, CP0_EBase));
rn = "EBase";
break;
default:
case 16:
switch (sel) {
case 0:
- gen_mfc0_load32(t0, offsetof(CPUState, CP0_Config0));
+ gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config0));
rn = "Config";
break;
case 1:
- gen_mfc0_load32(t0, offsetof(CPUState, CP0_Config1));
+ gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config1));
rn = "Config1";
break;
case 2:
- gen_mfc0_load32(t0, offsetof(CPUState, CP0_Config2));
+ gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config2));
rn = "Config2";
break;
case 3:
- gen_mfc0_load32(t0, offsetof(CPUState, CP0_Config3));
+ gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config3));
rn = "Config3";
break;
/* 6,7 are implementation dependent */
case 6:
- gen_mfc0_load32(t0, offsetof(CPUState, CP0_Config6));
+ gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config6));
rn = "Config6";
break;
case 7:
- gen_mfc0_load32(t0, offsetof(CPUState, CP0_Config7));
+ gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config7));
rn = "Config7";
break;
default:
case 17:
switch (sel) {
case 0:
- gen_helper_dmfc0_lladdr(t0);
+ gen_helper_dmfc0_lladdr(arg);
rn = "LLAddr";
break;
default:
case 18:
switch (sel) {
case 0 ... 7:
- gen_helper_1i(dmfc0_watchlo, t0, sel);
+ gen_helper_1i(dmfc0_watchlo, arg, sel);
rn = "WatchLo";
break;
default:
case 19:
switch (sel) {
case 0 ... 7:
- gen_helper_1i(mfc0_watchhi, t0, sel);
+ gen_helper_1i(mfc0_watchhi, arg, sel);
rn = "WatchHi";
break;
default:
switch (sel) {
case 0:
check_insn(env, ctx, ISA_MIPS3);
- tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_XContext));
+ tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_XContext));
rn = "XContext";
break;
default:
/* Officially reserved, but sel 0 is used for R1x000 framemask */
switch (sel) {
case 0:
- gen_mfc0_load32(t0, offsetof(CPUState, CP0_Framemask));
+ gen_mfc0_load32(arg, offsetof(CPUState, CP0_Framemask));
rn = "Framemask";
break;
default:
}
break;
case 22:
- tcg_gen_movi_tl(t0, 0); /* unimplemented */
+ tcg_gen_movi_tl(arg, 0); /* unimplemented */
rn = "'Diagnostic"; /* implementation dependent */
break;
case 23:
switch (sel) {
case 0:
- gen_helper_mfc0_debug(t0); /* EJTAG support */
+ gen_helper_mfc0_debug(arg); /* EJTAG support */
rn = "Debug";
break;
case 1:
-// gen_helper_dmfc0_tracecontrol(t0); /* PDtrace support */
+// gen_helper_dmfc0_tracecontrol(arg); /* PDtrace support */
rn = "TraceControl";
// break;
case 2:
-// gen_helper_dmfc0_tracecontrol2(t0); /* PDtrace support */
+// gen_helper_dmfc0_tracecontrol2(arg); /* PDtrace support */
rn = "TraceControl2";
// break;
case 3:
-// gen_helper_dmfc0_usertracedata(t0); /* PDtrace support */
+// gen_helper_dmfc0_usertracedata(arg); /* PDtrace support */
rn = "UserTraceData";
// break;
case 4:
-// gen_helper_dmfc0_tracebpc(t0); /* PDtrace support */
+// gen_helper_dmfc0_tracebpc(arg); /* PDtrace support */
rn = "TraceBPC";
// break;
default:
switch (sel) {
case 0:
/* EJTAG support */
- tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_DEPC));
+ tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_DEPC));
rn = "DEPC";
break;
default:
case 25:
switch (sel) {
case 0:
- gen_mfc0_load32(t0, offsetof(CPUState, CP0_Performance0));
+ gen_mfc0_load32(arg, offsetof(CPUState, CP0_Performance0));
rn = "Performance0";
break;
case 1:
-// gen_helper_dmfc0_performance1(t0);
+// gen_helper_dmfc0_performance1(arg);
rn = "Performance1";
// break;
case 2:
-// gen_helper_dmfc0_performance2(t0);
+// gen_helper_dmfc0_performance2(arg);
rn = "Performance2";
// break;
case 3:
-// gen_helper_dmfc0_performance3(t0);
+// gen_helper_dmfc0_performance3(arg);
rn = "Performance3";
// break;
case 4:
-// gen_helper_dmfc0_performance4(t0);
+// gen_helper_dmfc0_performance4(arg);
rn = "Performance4";
// break;
case 5:
-// gen_helper_dmfc0_performance5(t0);
+// gen_helper_dmfc0_performance5(arg);
rn = "Performance5";
// break;
case 6:
-// gen_helper_dmfc0_performance6(t0);
+// gen_helper_dmfc0_performance6(arg);
rn = "Performance6";
// break;
case 7:
-// gen_helper_dmfc0_performance7(t0);
+// gen_helper_dmfc0_performance7(arg);
rn = "Performance7";
// break;
default:
}
break;
case 26:
- tcg_gen_movi_tl(t0, 0); /* unimplemented */
+ tcg_gen_movi_tl(arg, 0); /* unimplemented */
rn = "ECC";
break;
case 27:
switch (sel) {
/* ignored */
case 0 ... 3:
- tcg_gen_movi_tl(t0, 0); /* unimplemented */
+ tcg_gen_movi_tl(arg, 0); /* unimplemented */
rn = "CacheErr";
break;
default:
case 2:
case 4:
case 6:
- gen_mfc0_load32(t0, offsetof(CPUState, CP0_TagLo));
+ gen_mfc0_load32(arg, offsetof(CPUState, CP0_TagLo));
rn = "TagLo";
break;
case 1:
case 3:
case 5:
case 7:
- gen_mfc0_load32(t0, offsetof(CPUState, CP0_DataLo));
+ gen_mfc0_load32(arg, offsetof(CPUState, CP0_DataLo));
rn = "DataLo";
break;
default:
case 2:
case 4:
case 6:
- gen_mfc0_load32(t0, offsetof(CPUState, CP0_TagHi));
+ gen_mfc0_load32(arg, offsetof(CPUState, CP0_TagHi));
rn = "TagHi";
break;
case 1:
case 3:
case 5:
case 7:
- gen_mfc0_load32(t0, offsetof(CPUState, CP0_DataHi));
+ gen_mfc0_load32(arg, offsetof(CPUState, CP0_DataHi));
rn = "DataHi";
break;
default:
case 30:
switch (sel) {
case 0:
- tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_ErrorEPC));
+ tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_ErrorEPC));
rn = "ErrorEPC";
break;
default:
switch (sel) {
case 0:
/* EJTAG support */
- gen_mfc0_load32(t0, offsetof(CPUState, CP0_DESAVE));
+ gen_mfc0_load32(arg, offsetof(CPUState, CP0_DESAVE));
rn = "DESAVE";
break;
default:
generate_exception(ctx, EXCP_RI);
}
-static void gen_dmtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int sel)
+static void gen_dmtc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int sel)
{
const char *rn = "invalid";
case 0:
switch (sel) {
case 0:
- gen_helper_mtc0_index(t0);
+ gen_helper_mtc0_index(arg);
rn = "Index";
break;
case 1:
check_insn(env, ctx, ASE_MT);
- gen_helper_mtc0_mvpcontrol(t0);
+ gen_helper_mtc0_mvpcontrol(arg);
rn = "MVPControl";
break;
case 2:
break;
case 1:
check_insn(env, ctx, ASE_MT);
- gen_helper_mtc0_vpecontrol(t0);
+ gen_helper_mtc0_vpecontrol(arg);
rn = "VPEControl";
break;
case 2:
check_insn(env, ctx, ASE_MT);
- gen_helper_mtc0_vpeconf0(t0);
+ gen_helper_mtc0_vpeconf0(arg);
rn = "VPEConf0";
break;
case 3:
check_insn(env, ctx, ASE_MT);
- gen_helper_mtc0_vpeconf1(t0);
+ gen_helper_mtc0_vpeconf1(arg);
rn = "VPEConf1";
break;
case 4:
check_insn(env, ctx, ASE_MT);
- gen_helper_mtc0_yqmask(t0);
+ gen_helper_mtc0_yqmask(arg);
rn = "YQMask";
break;
case 5:
check_insn(env, ctx, ASE_MT);
- tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, CP0_VPESchedule));
+ tcg_gen_st_tl(arg, cpu_env, offsetof(CPUState, CP0_VPESchedule));
rn = "VPESchedule";
break;
case 6:
check_insn(env, ctx, ASE_MT);
- tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, CP0_VPEScheFBack));
+ tcg_gen_st_tl(arg, cpu_env, offsetof(CPUState, CP0_VPEScheFBack));
rn = "VPEScheFBack";
break;
case 7:
check_insn(env, ctx, ASE_MT);
- gen_helper_mtc0_vpeopt(t0);
+ gen_helper_mtc0_vpeopt(arg);
rn = "VPEOpt";
break;
default:
case 2:
switch (sel) {
case 0:
- gen_helper_mtc0_entrylo0(t0);
+ gen_helper_mtc0_entrylo0(arg);
rn = "EntryLo0";
break;
case 1:
check_insn(env, ctx, ASE_MT);
- gen_helper_mtc0_tcstatus(t0);
+ gen_helper_mtc0_tcstatus(arg);
rn = "TCStatus";
break;
case 2:
check_insn(env, ctx, ASE_MT);
- gen_helper_mtc0_tcbind(t0);
+ gen_helper_mtc0_tcbind(arg);
rn = "TCBind";
break;
case 3:
check_insn(env, ctx, ASE_MT);
- gen_helper_mtc0_tcrestart(t0);
+ gen_helper_mtc0_tcrestart(arg);
rn = "TCRestart";
break;
case 4:
check_insn(env, ctx, ASE_MT);
- gen_helper_mtc0_tchalt(t0);
+ gen_helper_mtc0_tchalt(arg);
rn = "TCHalt";
break;
case 5:
check_insn(env, ctx, ASE_MT);
- gen_helper_mtc0_tccontext(t0);
+ gen_helper_mtc0_tccontext(arg);
rn = "TCContext";
break;
case 6:
check_insn(env, ctx, ASE_MT);
- gen_helper_mtc0_tcschedule(t0);
+ gen_helper_mtc0_tcschedule(arg);
rn = "TCSchedule";
break;
case 7:
check_insn(env, ctx, ASE_MT);
- gen_helper_mtc0_tcschefback(t0);
+ gen_helper_mtc0_tcschefback(arg);
rn = "TCScheFBack";
break;
default:
case 3:
switch (sel) {
case 0:
- gen_helper_mtc0_entrylo1(t0);
+ gen_helper_mtc0_entrylo1(arg);
rn = "EntryLo1";
break;
default:
case 4:
switch (sel) {
case 0:
- gen_helper_mtc0_context(t0);
+ gen_helper_mtc0_context(arg);
rn = "Context";
break;
case 1:
-// gen_helper_mtc0_contextconfig(t0); /* SmartMIPS ASE */
+// gen_helper_mtc0_contextconfig(arg); /* SmartMIPS ASE */
rn = "ContextConfig";
// break;
default:
case 5:
switch (sel) {
case 0:
- gen_helper_mtc0_pagemask(t0);
+ gen_helper_mtc0_pagemask(arg);
rn = "PageMask";
break;
case 1:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_helper_mtc0_pagegrain(t0);
+ gen_helper_mtc0_pagegrain(arg);
rn = "PageGrain";
break;
default:
case 6:
switch (sel) {
case 0:
- gen_helper_mtc0_wired(t0);
+ gen_helper_mtc0_wired(arg);
rn = "Wired";
break;
case 1:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_helper_mtc0_srsconf0(t0);
+ gen_helper_mtc0_srsconf0(arg);
rn = "SRSConf0";
break;
case 2:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_helper_mtc0_srsconf1(t0);
+ gen_helper_mtc0_srsconf1(arg);
rn = "SRSConf1";
break;
case 3:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_helper_mtc0_srsconf2(t0);
+ gen_helper_mtc0_srsconf2(arg);
rn = "SRSConf2";
break;
case 4:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_helper_mtc0_srsconf3(t0);
+ gen_helper_mtc0_srsconf3(arg);
rn = "SRSConf3";
break;
case 5:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_helper_mtc0_srsconf4(t0);
+ gen_helper_mtc0_srsconf4(arg);
rn = "SRSConf4";
break;
default:
switch (sel) {
case 0:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_helper_mtc0_hwrena(t0);
+ gen_helper_mtc0_hwrena(arg);
rn = "HWREna";
break;
default:
case 9:
switch (sel) {
case 0:
- gen_helper_mtc0_count(t0);
+ gen_helper_mtc0_count(arg);
rn = "Count";
break;
/* 6,7 are implementation dependent */
case 10:
switch (sel) {
case 0:
- gen_helper_mtc0_entryhi(t0);
+ gen_helper_mtc0_entryhi(arg);
rn = "EntryHi";
break;
default:
case 11:
switch (sel) {
case 0:
- gen_helper_mtc0_compare(t0);
+ gen_helper_mtc0_compare(arg);
rn = "Compare";
break;
/* 6,7 are implementation dependent */
case 12:
switch (sel) {
case 0:
- gen_helper_mtc0_status(t0);
+ save_cpu_state(ctx, 1);
+ gen_helper_mtc0_status(arg);
/* BS_STOP isn't good enough here, hflags may have changed. */
gen_save_pc(ctx->pc + 4);
ctx->bstate = BS_EXCP;
break;
case 1:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_helper_mtc0_intctl(t0);
+ gen_helper_mtc0_intctl(arg);
/* Stop translation as we may have switched the execution mode */
ctx->bstate = BS_STOP;
rn = "IntCtl";
break;
case 2:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_helper_mtc0_srsctl(t0);
+ gen_helper_mtc0_srsctl(arg);
/* Stop translation as we may have switched the execution mode */
ctx->bstate = BS_STOP;
rn = "SRSCtl";
break;
case 3:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_mtc0_store32(t0, offsetof(CPUState, CP0_SRSMap));
+ gen_mtc0_store32(arg, offsetof(CPUState, CP0_SRSMap));
/* Stop translation as we may have switched the execution mode */
ctx->bstate = BS_STOP;
rn = "SRSMap";
case 13:
switch (sel) {
case 0:
- gen_helper_mtc0_cause(t0);
+ save_cpu_state(ctx, 1);
+ gen_helper_mtc0_cause(arg);
rn = "Cause";
break;
default:
goto die;
}
- /* Stop translation as we may have switched the execution mode */
- ctx->bstate = BS_STOP;
break;
case 14:
switch (sel) {
case 0:
- tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, CP0_EPC));
+ tcg_gen_st_tl(arg, cpu_env, offsetof(CPUState, CP0_EPC));
rn = "EPC";
break;
default:
break;
case 1:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_helper_mtc0_ebase(t0);
+ gen_helper_mtc0_ebase(arg);
rn = "EBase";
break;
default:
case 16:
switch (sel) {
case 0:
- gen_helper_mtc0_config0(t0);
+ gen_helper_mtc0_config0(arg);
rn = "Config";
/* Stop translation as we may have switched the execution mode */
ctx->bstate = BS_STOP;
rn = "Config1";
break;
case 2:
- gen_helper_mtc0_config2(t0);
+ gen_helper_mtc0_config2(arg);
rn = "Config2";
/* Stop translation as we may have switched the execution mode */
ctx->bstate = BS_STOP;
case 18:
switch (sel) {
case 0 ... 7:
- gen_helper_1i(mtc0_watchlo, t0, sel);
+ gen_helper_1i(mtc0_watchlo, arg, sel);
rn = "WatchLo";
break;
default:
case 19:
switch (sel) {
case 0 ... 7:
- gen_helper_1i(mtc0_watchhi, t0, sel);
+ gen_helper_1i(mtc0_watchhi, arg, sel);
rn = "WatchHi";
break;
default:
switch (sel) {
case 0:
check_insn(env, ctx, ISA_MIPS3);
- gen_helper_mtc0_xcontext(t0);
+ gen_helper_mtc0_xcontext(arg);
rn = "XContext";
break;
default:
/* Officially reserved, but sel 0 is used for R1x000 framemask */
switch (sel) {
case 0:
- gen_helper_mtc0_framemask(t0);
+ gen_helper_mtc0_framemask(arg);
rn = "Framemask";
break;
default:
case 23:
switch (sel) {
case 0:
- gen_helper_mtc0_debug(t0); /* EJTAG support */
+ gen_helper_mtc0_debug(arg); /* EJTAG support */
/* BS_STOP isn't good enough here, hflags may have changed. */
gen_save_pc(ctx->pc + 4);
ctx->bstate = BS_EXCP;
rn = "Debug";
break;
case 1:
-// gen_helper_mtc0_tracecontrol(t0); /* PDtrace support */
+// gen_helper_mtc0_tracecontrol(arg); /* PDtrace support */
/* Stop translation as we may have switched the execution mode */
ctx->bstate = BS_STOP;
rn = "TraceControl";
// break;
case 2:
-// gen_helper_mtc0_tracecontrol2(t0); /* PDtrace support */
+// gen_helper_mtc0_tracecontrol2(arg); /* PDtrace support */
/* Stop translation as we may have switched the execution mode */
ctx->bstate = BS_STOP;
rn = "TraceControl2";
// break;
case 3:
-// gen_helper_mtc0_usertracedata(t0); /* PDtrace support */
+// gen_helper_mtc0_usertracedata(arg); /* PDtrace support */
/* Stop translation as we may have switched the execution mode */
ctx->bstate = BS_STOP;
rn = "UserTraceData";
// break;
case 4:
-// gen_helper_mtc0_tracebpc(t0); /* PDtrace support */
+// gen_helper_mtc0_tracebpc(arg); /* PDtrace support */
/* Stop translation as we may have switched the execution mode */
ctx->bstate = BS_STOP;
rn = "TraceBPC";
switch (sel) {
case 0:
/* EJTAG support */
- tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, CP0_DEPC));
+ tcg_gen_st_tl(arg, cpu_env, offsetof(CPUState, CP0_DEPC));
rn = "DEPC";
break;
default:
case 25:
switch (sel) {
case 0:
- gen_helper_mtc0_performance0(t0);
+ gen_helper_mtc0_performance0(arg);
rn = "Performance0";
break;
case 1:
-// gen_helper_mtc0_performance1(t0);
+// gen_helper_mtc0_performance1(arg);
rn = "Performance1";
// break;
case 2:
-// gen_helper_mtc0_performance2(t0);
+// gen_helper_mtc0_performance2(arg);
rn = "Performance2";
// break;
case 3:
-// gen_helper_mtc0_performance3(t0);
+// gen_helper_mtc0_performance3(arg);
rn = "Performance3";
// break;
case 4:
-// gen_helper_mtc0_performance4(t0);
+// gen_helper_mtc0_performance4(arg);
rn = "Performance4";
// break;
case 5:
-// gen_helper_mtc0_performance5(t0);
+// gen_helper_mtc0_performance5(arg);
rn = "Performance5";
// break;
case 6:
-// gen_helper_mtc0_performance6(t0);
+// gen_helper_mtc0_performance6(arg);
rn = "Performance6";
// break;
case 7:
-// gen_helper_mtc0_performance7(t0);
+// gen_helper_mtc0_performance7(arg);
rn = "Performance7";
// break;
default:
case 2:
case 4:
case 6:
- gen_helper_mtc0_taglo(t0);
+ gen_helper_mtc0_taglo(arg);
rn = "TagLo";
break;
case 1:
case 3:
case 5:
case 7:
- gen_helper_mtc0_datalo(t0);
+ gen_helper_mtc0_datalo(arg);
rn = "DataLo";
break;
default:
case 2:
case 4:
case 6:
- gen_helper_mtc0_taghi(t0);
+ gen_helper_mtc0_taghi(arg);
rn = "TagHi";
break;
case 1:
case 3:
case 5:
case 7:
- gen_helper_mtc0_datahi(t0);
+ gen_helper_mtc0_datahi(arg);
rn = "DataHi";
break;
default:
case 30:
switch (sel) {
case 0:
- tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, CP0_ErrorEPC));
+ tcg_gen_st_tl(arg, cpu_env, offsetof(CPUState, CP0_ErrorEPC));
rn = "ErrorEPC";
break;
default:
switch (sel) {
case 0:
/* EJTAG support */
- gen_mtc0_store32(t0, offsetof(CPUState, CP0_DESAVE));
+ gen_mtc0_store32(arg, offsetof(CPUState, CP0_DESAVE));
rn = "DESAVE";
break;
default:
check_cp1_64bitmode(ctx);
{
int l1 = gen_new_label();
- TCGv_i32 fp0;
+ TCGv_i64 fp0;
if (ft != 0)
tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[ft], 0, l1);
check_cp1_64bitmode(ctx);
{
int l1 = gen_new_label();
- TCGv_i32 fp0;
+ TCGv_i64 fp0;
if (ft != 0) {
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[ft], 0, l1);
const char *opn = "extended float load/store";
int store = 0;
TCGv t0 = tcg_temp_new();
- TCGv t1 = tcg_temp_new();
if (base == 0) {
gen_load_gpr(t0, index);
{
TCGv_i32 fp0 = tcg_temp_new_i32();
- tcg_gen_qemu_ld32s(t1, t0, ctx->mem_idx);
- tcg_gen_trunc_tl_i32(fp0, t1);
+ tcg_gen_qemu_ld32s(t0, t0, ctx->mem_idx);
+ tcg_gen_trunc_tl_i32(fp0, t0);
gen_store_fpr32(fp0, fd);
tcg_temp_free_i32(fp0);
}
check_cop1x(ctx);
{
TCGv_i32 fp0 = tcg_temp_new_i32();
+ TCGv t1 = tcg_temp_new();
gen_load_fpr32(fp0, fs);
tcg_gen_extu_i32_tl(t1, fp0);
tcg_gen_qemu_st32(t1, t0, ctx->mem_idx);
tcg_temp_free_i32(fp0);
+ tcg_temp_free(t1);
}
opn = "swxc1";
store = 1;
break;
}
tcg_temp_free(t0);
- tcg_temp_free(t1);
MIPS_DEBUG("%s %s, %s(%s)", opn, fregnames[store ? fs : fd],
regnames[index], regnames[base]);
}
break;
case OPC_SYSCALL:
generate_exception(ctx, EXCP_SYSCALL);
+ ctx->bstate = BS_STOP;
break;
case OPC_BREAK:
generate_exception(ctx, EXCP_BREAK);
break;
case OPC_DI:
check_insn(env, ctx, ISA_MIPS32R2);
+ save_cpu_state(ctx, 1);
gen_helper_di(t0);
gen_store_gpr(t0, rt);
/* Stop translation as we may have switched the execution mode */
break;
case OPC_EI:
check_insn(env, ctx, ISA_MIPS32R2);
+ save_cpu_state(ctx, 1);
gen_helper_ei(t0);
gen_store_gpr(t0, rt);
/* Stop translation as we may have switched the execution mode */
return;
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
+ TCGV_UNUSED(cpu_gpr[0]);
for (i = 1; i < 32; i++)
cpu_gpr[i] = tcg_global_mem_new(TCG_AREG0,
offsetof(CPUState, active_tc.gpr[i]),
env->cpu_model_str = cpu_model;
mips_tcg_init();
cpu_reset(env);
+ qemu_init_vcpu(env);
return env;
}
/* Minimal init */
#if defined(CONFIG_USER_ONLY)
env->hflags = MIPS_HFLAG_UM;
+ /* Enable access to the SYNCI_Step register. */
+ env->CP0_HWREna |= (1 << 1);
#else
if (env->hflags & MIPS_HFLAG_BMASK) {
/* If the exception was raised from a delay slot,
projects / qemu / blobdiff