Fix typo

[qemu] / target-mips / translate.c

diff --git a/target-mips/translate.c b/target-mips/translate.c
index 2b617c5..6f5bea4 100644 (file)
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -501,13 +501,13 @@ static const char *fregnames[] =
       "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", };
 
 #ifdef MIPS_DEBUG_DISAS
-#define MIPS_DEBUG(fmt, args...)                         \
+#define MIPS_DEBUG(fmt, ...)                         \
         qemu_log_mask(CPU_LOG_TB_IN_ASM,                \
                        TARGET_FMT_lx ": %08x " fmt "\n", \
-                       ctx->pc, ctx->opcode , ##args)
+                       ctx->pc, ctx->opcode , ## __VA_ARGS__)
 #define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
 #else
-#define MIPS_DEBUG(fmt, args...) do { } while(0)
+#define MIPS_DEBUG(fmt, ...) do { } while(0)
 #define LOG_DISAS(...) do { } while (0)
 #endif
 
@@ -793,8 +793,6 @@ generate_exception_err (DisasContext *ctx, int excp, int err)
     gen_helper_raise_exception_err(texcp, terr);
     tcg_temp_free_i32(terr);
     tcg_temp_free_i32(texcp);
-    gen_helper_interrupt_restart();
-    tcg_gen_exit_tb(0);
 }
 
 static inline void
@@ -802,8 +800,6 @@ generate_exception (DisasContext *ctx, int excp)
 {
     save_cpu_state(ctx, 1);
     gen_helper_0i(raise_exception, excp);
-    gen_helper_interrupt_restart();
-    tcg_gen_exit_tb(0);
 }
 
 /* Addresses computation */
@@ -1594,7 +1590,7 @@ static void gen_arith (CPUState *env, DisasContext *ctx, uint32_t opc,
             tcg_temp_free(t2);
             tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
             tcg_temp_free(t1);
-            /* operands of same sign, result different sign */
+           /* operands of different sign, first operand and result different sign */
             generate_exception(ctx, EXCP_OVERFLOW);
             gen_set_label(l1);
             gen_store_gpr(t0, rd);
@@ -1608,6 +1604,7 @@ static void gen_arith (CPUState *env, DisasContext *ctx, uint32_t opc,
             tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
         } else if (rs == 0 && rt != 0) {
             tcg_gen_neg_tl(cpu_gpr[rd], cpu_gpr[rt]);
+            tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
         } else if (rs != 0 && rt == 0) {
             tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]);
         } else {
@@ -1669,7 +1666,7 @@ static void gen_arith (CPUState *env, DisasContext *ctx, uint32_t opc,
             tcg_temp_free(t2);
             tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
             tcg_temp_free(t1);
-            /* operands of same sign, result different sign */
+           /* operands of different sign, first operand and result different sign */
             generate_exception(ctx, EXCP_OVERFLOW);
             gen_set_label(l1);
             gen_store_gpr(t0, rd);
@@ -6382,13 +6379,10 @@ static void gen_farith (DisasContext *ctx, uint32_t op1,
             TCGv_i32 fp0 = tcg_temp_new_i32();
             TCGv_i32 fp1 = tcg_temp_new_i32();
 
-            if (ctx->opcode & (1 << 6)) {
-                check_cop1x(ctx);
-            }
-
             gen_load_fpr32(fp0, fs);
             gen_load_fpr32(fp1, ft);
             if (ctx->opcode & (1 << 6)) {
+                check_cop1x(ctx);
                 gen_cmpabs_s(func-48, fp0, fp1, cc);
                 opn = condnames_abs[func-48];
             } else {
@@ -6747,17 +6741,16 @@ static void gen_farith (DisasContext *ctx, uint32_t op1,
         {
             TCGv_i64 fp0 = tcg_temp_new_i64();
             TCGv_i64 fp1 = tcg_temp_new_i64();
-            if (ctx->opcode & (1 << 6)) {
-                check_cop1x(ctx);
-            }
-            check_cp1_registers(ctx, fs | ft);
 
             gen_load_fpr64(ctx, fp0, fs);
             gen_load_fpr64(ctx, fp1, ft);
             if (ctx->opcode & (1 << 6)) {
+                check_cop1x(ctx);
+                check_cp1_registers(ctx, fs | ft);
                 gen_cmpabs_d(func-48, fp0, fp1, cc);
                 opn = condnames_abs[func-48];
             } else {
+                check_cp1_registers(ctx, fs | ft);
                 gen_cmp_d(func-48, fp0, fp1, cc);
                 opn = condnames[func-48];
             }
@@ -7226,22 +7219,6 @@ static void gen_flt3_ldst (DisasContext *ctx, uint32_t opc,
     int store = 0;
     TCGv t0 = tcg_temp_new();
 
-    switch (opc) {
-    case OPC_LWXC1:
-    case OPC_SWXC1:
-        check_cop1x(ctx);
-        break;
-    case OPC_LDXC1:
-    case OPC_SDXC1:
-        check_cop1x(ctx);
-        check_cp1_registers(ctx, fd);
-        break;
-    case OPC_LUXC1:
-    case OPC_SUXC1:
-        check_cp1_64bitmode(ctx);
-        break;
-    }
-
     if (base == 0) {
         gen_load_gpr(t0, index);
     } else if (index == 0) {
@@ -7255,6 +7232,7 @@ static void gen_flt3_ldst (DisasContext *ctx, uint32_t opc,
     save_cpu_state(ctx, 0);
     switch (opc) {
     case OPC_LWXC1:
+        check_cop1x(ctx);
         {
             TCGv_i32 fp0 = tcg_temp_new_i32();
 
@@ -7266,6 +7244,8 @@ static void gen_flt3_ldst (DisasContext *ctx, uint32_t opc,
         opn = "lwxc1";
         break;
     case OPC_LDXC1:
+        check_cop1x(ctx);
+        check_cp1_registers(ctx, fd);
         {
             TCGv_i64 fp0 = tcg_temp_new_i64();
 
@@ -7276,6 +7256,7 @@ static void gen_flt3_ldst (DisasContext *ctx, uint32_t opc,
         opn = "ldxc1";
         break;
     case OPC_LUXC1:
+        check_cp1_64bitmode(ctx);
         tcg_gen_andi_tl(t0, t0, ~0x7);
         {
             TCGv_i64 fp0 = tcg_temp_new_i64();
@@ -7287,6 +7268,7 @@ static void gen_flt3_ldst (DisasContext *ctx, uint32_t opc,
         opn = "luxc1";
         break;
     case OPC_SWXC1:
+        check_cop1x(ctx);
         {
             TCGv_i32 fp0 = tcg_temp_new_i32();
             TCGv t1 = tcg_temp_new();
@@ -7301,6 +7283,8 @@ static void gen_flt3_ldst (DisasContext *ctx, uint32_t opc,
         store = 1;
         break;
     case OPC_SDXC1:
+        check_cop1x(ctx);
+        check_cp1_registers(ctx, fs);
         {
             TCGv_i64 fp0 = tcg_temp_new_i64();
 
@@ -7312,6 +7296,7 @@ static void gen_flt3_ldst (DisasContext *ctx, uint32_t opc,
         store = 1;
         break;
     case OPC_SUXC1:
+        check_cp1_64bitmode(ctx);
         tcg_gen_andi_tl(t0, t0, ~0x7);
         {
             TCGv_i64 fp0 = tcg_temp_new_i64();
@@ -8567,6 +8552,7 @@ CPUMIPSState *cpu_mips_init (const char *cpu_model)
     env->cpu_model_str = cpu_model;
     mips_tcg_init();
     cpu_reset(env);
+    qemu_init_vcpu(env);
     return env;
 }
 
@@ -8584,6 +8570,8 @@ void cpu_reset (CPUMIPSState *env)
     /* Minimal init */
 #if defined(CONFIG_USER_ONLY)
     env->hflags = MIPS_HFLAG_UM;
+    /* Enable access to the SYNCI_Step register.  */
+    env->CP0_HWREna |= (1 << 1);
 #else
     if (env->hflags & MIPS_HFLAG_BMASK) {
         /* If the exception was raised from a delay slot,