#include <string.h>
#include <inttypes.h>
#include <signal.h>
-#include <assert.h>
#include "cpu.h"
#include "exec-all.h"
return addr;
}
+int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr)
+{
+ /* For user mode, only U0 area is cachable. */
+ return !(addr & 0x80000000);
+}
+
#else /* !CONFIG_USER_ONLY */
#define MMU_OK 0
}
}
- if (loglevel & CPU_LOG_INT) {
+ if (qemu_loglevel_mask(CPU_LOG_INT)) {
const char *expname;
switch (env->exception_index) {
case 0x0e0:
urb = ((env->mmucr) >> 18) & 0x3f;
urc = ((env->mmucr) >> 10) & 0x3f;
urc++;
- if (urc == urb || urc == UTLB_SIZE - 1)
+ if ((urb > 0 && urc > urb) || urc > (UTLB_SIZE - 1))
urc = 0;
env->mmucr = (env->mmucr & 0xffff03ff) | (urc << 10);
}
Return entry, MMU_ITLB_MISS, MMU_ITLB_MULTIPLE or MMU_DTLB_MULTIPLE
Update the itlb from utlb if update is not 0
*/
-int find_itlb_entry(CPUState * env, target_ulong address,
- int use_asid, int update)
+static int find_itlb_entry(CPUState * env, target_ulong address,
+ int use_asid, int update)
{
int e, n;
/* Find utlb entry
Return entry, MMU_DTLB_MISS, MMU_DTLB_MULTIPLE */
-int find_utlb_entry(CPUState * env, target_ulong address, int use_asid)
+static int find_utlb_entry(CPUState * env, target_ulong address, int use_asid)
{
/* per utlb access */
increment_urc(env);
return n;
}
-int get_physical_address(CPUState * env, target_ulong * physical,
- int *prot, target_ulong address,
- int rw, int access_type)
+static int get_physical_address(CPUState * env, target_ulong * physical,
+ int *prot, target_ulong address,
+ int rw, int access_type)
{
/* P1, P2 and P4 areas do not use translation */
if ((address >= 0x80000000 && address < 0xc0000000) ||
return physical;
}
-void cpu_load_tlb(CPUState * env)
+void cpu_load_tlb(CPUSH4State * env)
{
int n = cpu_mmucr_urc(env->mmucr);
tlb_t * entry = &env->utlb[n];
}
}
+int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr)
+{
+ int n;
+ int use_asid = (env->mmucr & MMUCR_SV) == 0 || (env->sr & SR_MD) == 0;
+
+ /* check area */
+ if (env->sr & SR_MD) {
+ /* For previledged mode, P2 and P4 area is not cachable. */
+ if ((0xA0000000 <= addr && addr < 0xC0000000) || 0xE0000000 <= addr)
+ return 0;
+ } else {
+ /* For user mode, only U0 area is cachable. */
+ if (0x80000000 <= addr)
+ return 0;
+ }
+
+ /*
+ * TODO : Evaluate CCR and check if the cache is on or off.
+ * Now CCR is not in CPUSH4State, but in SH7750State.
+ * When you move the ccr inot CPUSH4State, the code will be
+ * as follows.
+ */
+#if 0
+ /* check if operand cache is enabled or not. */
+ if (!(env->ccr & 1))
+ return 0;
+#endif
+
+ /* if MMU is off, no check for TLB. */
+ if (env->mmucr & MMUCR_AT)
+ return 1;
+
+ /* check TLB */
+ n = find_tlb_entry(env, addr, env->itlb, ITLB_SIZE, use_asid);
+ if (n >= 0)
+ return env->itlb[n].c;
+
+ n = find_tlb_entry(env, addr, env->utlb, UTLB_SIZE, use_asid);
+ if (n >= 0)
+ return env->utlb[n].c;
+
+ return 0;
+}
+
#endif