#define TARGET_PAGE_BITS 13 /* 8k */
#endif
-#define TARGET_PHYS_ADDR_BITS 64
+#define CPUState struct CPUSPARCState
#include "cpu-defs.h"
#define PSR_ET (1<<5)
#define PSR_CWP 0x1f
+#define CC_SRC (env->cc_src)
+#define CC_SRC2 (env->cc_src2)
+#define CC_DST (env->cc_dst)
+#define CC_OP (env->cc_op)
+
+enum {
+ CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */
+ CC_OP_FLAGS, /* all cc are back in status register */
+ CC_OP_DIV, /* modify N, Z and V, C = 0*/
+ CC_OP_ADD, /* modify all flags, CC_DST = res, CC_SRC = src1 */
+ CC_OP_ADDX, /* modify all flags, CC_DST = res, CC_SRC = src1 */
+ CC_OP_TADD, /* modify all flags, CC_DST = res, CC_SRC = src1 */
+ CC_OP_TADDTV, /* modify all flags except V, CC_DST = res, CC_SRC = src1 */
+ CC_OP_SUB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
+ CC_OP_SUBX, /* modify all flags, CC_DST = res, CC_SRC = src1 */
+ CC_OP_TSUB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
+ CC_OP_TSUBTV, /* modify all flags except V, CC_DST = res, CC_SRC = src1 */
+ CC_OP_LOGIC, /* modify N and Z, C = V = 0, CC_DST = res */
+ CC_OP_NB,
+};
+
/* Trap base register */
#define TBR_BASE_MASK 0xfffff000
uint32_t mmu_cxr_mask;
uint32_t mmu_sfsr_mask;
uint32_t mmu_trcr_mask;
+ uint32_t mxcc_version;
uint32_t features;
uint32_t nwindows;
uint32_t maxtl;
/* emulator internal flags handling */
target_ulong cc_src, cc_src2;
target_ulong cc_dst;
+ uint32_t cc_op;
target_ulong t0, t1; /* temporaries live across basic blocks */
target_ulong cond; /* conditional branch result (XXX: save it in a
uint32_t mmuregs[32];
uint64_t mxccdata[4];
uint64_t mxccregs[8];
+ uint64_t mmubpregs[4];
uint64_t prom_addr;
#endif
/* temporary float registers */
uint64_t hpstate, htstate[MAXTL_MAX], hintp, htba, hver, hstick_cmpr, ssr;
void *hstick; // UA 2005
uint32_t softint;
-#define SOFTINT_TIMER 1
+#define SOFTINT_TIMER 1
+#define SOFTINT_STIMER (1 << 16)
#endif
sparc_def_t *def;
} CPUSPARCState;
env->psrps = (_tmp & PSR_PS)? 1 : 0; \
env->psret = (_tmp & PSR_ET)? 1 : 0; \
cpu_set_cwp(env, _tmp & PSR_CWP); \
+ CC_OP = CC_OP_FLAGS; \
} while (0)
#ifdef TARGET_SPARC64
#define PUT_CCR(env, val) do { int _tmp = val; \
env->xcc = (_tmp >> 4) << 20; \
env->psr = (_tmp & 0xf) << 20; \
+ CC_OP = CC_OP_FLAGS; \
} while (0)
#define GET_CWP64(env) (env->nwindows - 1 - (env)->cwp)
/* cpu-exec.c */
void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
- int is_asi);
+ int is_asi, int size);
int cpu_sparc_signal_handler(int host_signum, void *pinfo, void *puc);
-#define CPUState CPUSPARCState
#define cpu_init cpu_sparc_init
#define cpu_exec cpu_sparc_exec
#define cpu_gen_code cpu_sparc_gen_code
}
#endif
-#define CPU_PC_FROM_TB(env, tb) do { \
- env->pc = tb->pc; \
- env->npc = tb->cs_base; \
- } while(0)
-
#include "cpu-all.h"
+#include "exec-all.h"
/* sum4m.c, sun4u.c */
void cpu_check_irqs(CPUSPARCState *env);
void cpu_tick_set_limit(void *opaque, uint64_t limit);
#endif
+static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
+{
+ env->pc = tb->pc;
+ env->npc = tb->cs_base;
+}
+
+static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
+ target_ulong *cs_base, int *flags)
+{
+ *pc = env->pc;
+ *cs_base = env->npc;
+#ifdef TARGET_SPARC64
+ // AM . Combined FPU enable bits . PRIV . DMMU enabled . IMMU enabled
+ *flags = ((env->pstate & PS_AM) << 2)
+ | (((env->pstate & PS_PEF) >> 1) | ((env->fprs & FPRS_FEF) << 2))
+ | (env->pstate & PS_PRIV) | ((env->lsu & (DMMU_E | IMMU_E)) >> 2);
+#else
+ // FPU enable . Supervisor
+ *flags = (env->psref << 4) | env->psrs;
+#endif
+}
+
#endif