Add T1 and T2 CPUs, add a Sun4v machine

[qemu] / target-sparc / helper.c

diff --git a/target-sparc/helper.c b/target-sparc/helper.c
index 7b87d59..85b9d5c 100644 (file)
--- a/target-sparc/helper.c
+++ b/target-sparc/helper.c
@@ -87,14 +87,14 @@ int cpu_sparc_handle_mmu_fault(CPUState *env1, target_ulong address, int rw,
  * Sparc V8 Reference MMU (SRMMU)
  */
 static const int access_table[8][8] = {
-    { 0, 0, 0, 0, 2, 0, 3, 3 },
-    { 0, 0, 0, 0, 2, 0, 0, 0 },
-    { 2, 2, 0, 0, 0, 2, 3, 3 },
-    { 2, 2, 0, 0, 0, 2, 0, 0 },
-    { 2, 0, 2, 0, 2, 2, 3, 3 },
-    { 2, 0, 2, 0, 2, 0, 2, 0 },
-    { 2, 2, 2, 0, 2, 2, 3, 3 },
-    { 2, 2, 2, 0, 2, 2, 2, 0 }
+    { 0, 0, 0, 0, 8, 0, 12, 12 },
+    { 0, 0, 0, 0, 8, 0, 0, 0 },
+    { 8, 8, 0, 0, 0, 8, 12, 12 },
+    { 8, 8, 0, 0, 0, 8, 0, 0 },
+    { 8, 0, 8, 0, 8, 8, 12, 12 },
+    { 8, 0, 8, 0, 8, 0, 8, 0 },
+    { 8, 8, 8, 0, 8, 8, 12, 12 },
+    { 8, 8, 8, 0, 8, 8, 8, 0 }
 };
 
 static const int perm_table[2][8] = {
@@ -449,6 +449,7 @@ static int get_physical_address_data(CPUState *env,
 #ifdef DEBUG_MMU
     printf("DMISS at 0x%" PRIx64 "\n", address);
 #endif
+    env->dmmuregs[6] = (address & ~0x1fffULL) | (env->dmmuregs[1] & 0x1fff);
     env->exception_index = TT_DMISS;
     return 1;
 }
@@ -507,6 +508,7 @@ static int get_physical_address_code(CPUState *env,
 #ifdef DEBUG_MMU
     printf("TMISS at 0x%" PRIx64 "\n", address);
 #endif
+    env->immuregs[6] = (address & ~0x1fffULL) | (env->dmmuregs[1] & 0x1fff);
     env->exception_index = TT_TMISS;
     return 1;
 }
@@ -655,7 +657,7 @@ target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
 
 #ifdef TARGET_SPARC64
 #ifdef DEBUG_PCALL
-static const char * const excp_names[0x50] = {
+static const char * const excp_names[0x80] = {
     [TT_TFAULT] = "Instruction Access Fault",
     [TT_TMISS] = "Instruction Access MMU Miss",
     [TT_CODE_ACCESS] = "Instruction Access Error",
@@ -699,7 +701,7 @@ void do_interrupt(CPUState *env)
         static int count;
         const char *name;
 
-        if (intno < 0 || intno >= 0x180 || (intno > 0x4f && intno < 0x80))
+        if (intno < 0 || intno >= 0x180)
             name = "Unknown";
         else if (intno >= 0x100)
             name = "Trap Instruction";
@@ -742,14 +744,37 @@ void do_interrupt(CPUState *env)
         return;
     }
 #endif
+    if (env->tl < MAXTL - 1) {
+        env->tl++;
+    } else {
+        env->pstate |= PS_RED;
+        if (env->tl != MAXTL)
+            env->tl++;
+    }
+    env->tsptr = &env->ts[env->tl];
     env->tsptr->tstate = ((uint64_t)GET_CCR(env) << 32) |
         ((env->asi & 0xff) << 24) | ((env->pstate & 0xf3f) << 8) |
         GET_CWP64(env);
     env->tsptr->tpc = env->pc;
     env->tsptr->tnpc = env->npc;
     env->tsptr->tt = intno;
-    change_pstate(PS_PEF | PS_PRIV | PS_AG);
-
+    if (!(env->features & CPU_FEATURE_GL)) {
+        switch (intno) {
+        case TT_IVEC:
+            change_pstate(PS_PEF | PS_PRIV | PS_IG);
+            break;
+        case TT_TFAULT:
+        case TT_TMISS:
+        case TT_DFAULT:
+        case TT_DMISS:
+        case TT_DPROT:
+            change_pstate(PS_PEF | PS_PRIV | PS_MG);
+            break;
+        default:
+            change_pstate(PS_PEF | PS_PRIV | PS_AG);
+            break;
+        }
+    }
     if (intno == TT_CLRWIN)
         cpu_set_cwp(env, cpu_cwp_dec(env, env->cwp - 1));
     else if ((intno & 0x1c0) == TT_SPILL)
@@ -758,14 +783,6 @@ void do_interrupt(CPUState *env)
         cpu_set_cwp(env, cpu_cwp_inc(env, env->cwp + 1));
     env->tbr &= ~0x7fffULL;
     env->tbr |= ((env->tl > 1) ? 1 << 14 : 0) | (intno << 5);
-    if (env->tl < MAXTL - 1) {
-        env->tl++;
-    } else {
-        env->pstate |= PS_RED;
-        if (env->tl != MAXTL)
-            env->tl++;
-    }
-    env->tsptr = &env->ts[env->tl];
     env->pc = env->tbr;
     env->npc = env->pc + 4;
     env->exception_index = 0;
@@ -900,7 +917,7 @@ void cpu_reset(CPUSPARCState *env)
 #ifdef TARGET_SPARC64
     env->pstate = PS_PRIV;
     env->hpstate = HS_PRIV;
-    env->pc = 0x1fff0000000ULL;
+    env->pc = 0x1fff0000020ULL; // XXX should be different for system_reset
     env->tsptr = &env->ts[env->tl];
 #else
     env->pc = 0;
@@ -932,6 +949,7 @@ static int cpu_sparc_register(CPUSPARCState *env, const char *cpu_model)
     env->mmuregs[0] |= def->mmu_version;
     cpu_sparc_set_id(env, 0);
 #else
+    env->mmu_version = def->mmu_version;
     env->version |= def->nwindows - 1;
 #endif
     return 0;
@@ -976,7 +994,7 @@ static const sparc_def_t sparc_defs[] = {
         .iu_version = ((0x04ULL << 48) | (0x02ULL << 32) | (0ULL << 24)
                        | (MAXTL << 8)),
         .fpu_version = 0x00000000,
-        .mmu_version = 0,
+        .mmu_version = mmu_us_12,
         .nwindows = 4,
         .features = CPU_DEFAULT_FEATURES,
     },
@@ -985,7 +1003,7 @@ static const sparc_def_t sparc_defs[] = {
         .iu_version = ((0x04ULL << 48) | (0x03ULL << 32) | (0ULL << 24)
                        | (MAXTL << 8)),
         .fpu_version = 0x00000000,
-        .mmu_version = 0,
+        .mmu_version = mmu_us_12,
         .nwindows = 5,
         .features = CPU_DEFAULT_FEATURES,
     },
@@ -994,7 +1012,7 @@ static const sparc_def_t sparc_defs[] = {
         .iu_version = ((0x04ULL << 48) | (0x04ULL << 32) | (0ULL << 24)
                        | (MAXTL << 8)),
         .fpu_version = 0x00000000,
-        .mmu_version = 0,
+        .mmu_version = mmu_us_12,
         .nwindows = 8,
         .features = CPU_DEFAULT_FEATURES,
     },
@@ -1003,7 +1021,7 @@ static const sparc_def_t sparc_defs[] = {
         .iu_version = ((0x04ULL << 48) | (0x05ULL << 32) | (0x51ULL << 24)
                        | (MAXTL << 8)),
         .fpu_version = 0x00000000,
-        .mmu_version = 0,
+        .mmu_version = mmu_us_12,
         .nwindows = 8,
         .features = CPU_DEFAULT_FEATURES,
     },
@@ -1012,7 +1030,7 @@ static const sparc_def_t sparc_defs[] = {
         .iu_version = ((0x17ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)
                        | (MAXTL << 8)),
         .fpu_version = 0x00000000,
-        .mmu_version = 0,
+        .mmu_version = mmu_us_12,
         .nwindows = 8,
         .features = CPU_DEFAULT_FEATURES,
     },
@@ -1021,7 +1039,7 @@ static const sparc_def_t sparc_defs[] = {
         .iu_version = ((0x17ULL << 48) | (0x11ULL << 32) | (0x20ULL << 24)
                        | (MAXTL << 8)),
         .fpu_version = 0x00000000,
-        .mmu_version = 0,
+        .mmu_version = mmu_us_12,
         .nwindows = 8,
         .features = CPU_DEFAULT_FEATURES,
     },
@@ -1030,7 +1048,7 @@ static const sparc_def_t sparc_defs[] = {
         .iu_version = ((0x17ULL << 48) | (0x12ULL << 32) | (0x91ULL << 24)
                        | (MAXTL << 8)),
         .fpu_version = 0x00000000,
-        .mmu_version = 0,
+        .mmu_version = mmu_us_12,
         .nwindows = 8,
         .features = CPU_DEFAULT_FEATURES,
     },
@@ -1039,7 +1057,7 @@ static const sparc_def_t sparc_defs[] = {
         .iu_version = ((0x17ULL << 48) | (0x13ULL << 32) | (0x14ULL << 24)
                        | (MAXTL << 8)),
         .fpu_version = 0x00000000,
-        .mmu_version = 0,
+        .mmu_version = mmu_us_12,
         .nwindows = 8,
         .features = CPU_DEFAULT_FEATURES,
     },
@@ -1048,7 +1066,7 @@ static const sparc_def_t sparc_defs[] = {
         .iu_version = ((0x3eULL << 48) | (0x14ULL << 32) | (0x34ULL << 24)
                        | (MAXTL << 8)),
         .fpu_version = 0x00000000,
-        .mmu_version = 0,
+        .mmu_version = mmu_us_12,
         .nwindows = 8,
         .features = CPU_DEFAULT_FEATURES,
     },
@@ -1057,7 +1075,7 @@ static const sparc_def_t sparc_defs[] = {
         .iu_version = ((0x3eULL << 48) | (0x15ULL << 32) | (0x41ULL << 24)
                        | (MAXTL << 8)),
         .fpu_version = 0x00000000,
-        .mmu_version = 0,
+        .mmu_version = mmu_us_3,
         .nwindows = 8,
         .features = CPU_DEFAULT_FEATURES,
     },
@@ -1066,7 +1084,7 @@ static const sparc_def_t sparc_defs[] = {
         .iu_version = ((0x3eULL << 48) | (0x16ULL << 32) | (0x34ULL << 24)
                        | (MAXTL << 8)),
         .fpu_version = 0x00000000,
-        .mmu_version = 0,
+        .mmu_version = mmu_us_12,
         .nwindows = 8,
         .features = CPU_DEFAULT_FEATURES,
     },
@@ -1075,7 +1093,7 @@ static const sparc_def_t sparc_defs[] = {
         .iu_version = ((0x3eULL << 48) | (0x18ULL << 32) | (0x31ULL << 24)
                        | (MAXTL << 8)),
         .fpu_version = 0x00000000,
-        .mmu_version = 0,
+        .mmu_version = mmu_us_4,
         .nwindows = 8,
         .features = CPU_DEFAULT_FEATURES,
     },
@@ -1084,25 +1102,47 @@ static const sparc_def_t sparc_defs[] = {
         .iu_version = ((0x3eULL << 48) | (0x19ULL << 32) | (0x22ULL << 24)
                        | (MAXTL << 8)),
         .fpu_version = 0x00000000,
-        .mmu_version = 0,
+        .mmu_version = mmu_us_12,
         .nwindows = 8,
-        .features = CPU_DEFAULT_FEATURES,
+        .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_CMT,
     },
     {
         .name = "Sun UltraSparc IIIi+",
         .iu_version = ((0x3eULL << 48) | (0x22ULL << 32) | (0ULL << 24)
                        | (MAXTL << 8)),
         .fpu_version = 0x00000000,
-        .mmu_version = 0,
+        .mmu_version = mmu_us_3,
         .nwindows = 8,
         .features = CPU_DEFAULT_FEATURES,
     },
     {
+        .name = "Sun UltraSparc T1",
+        // defined in sparc_ifu_fdp.v and ctu.h
+        .iu_version = ((0x3eULL << 48) | (0x23ULL << 32) | (0x02ULL << 24)
+                       | (MAXTL << 8)),
+        .fpu_version = 0x00000000,
+        .mmu_version = mmu_sun4v,
+        .nwindows = 8,
+        .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_HYPV | CPU_FEATURE_CMT
+        | CPU_FEATURE_GL,
+    },
+    {
+        .name = "Sun UltraSparc T2",
+        // defined in tlu_asi_ctl.v and n2_revid_cust.v
+        .iu_version = ((0x3eULL << 48) | (0x24ULL << 32) | (0x02ULL << 24)
+                       | (MAXTL << 8)),
+        .fpu_version = 0x00000000,
+        .mmu_version = mmu_sun4v,
+        .nwindows = 8,
+        .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_HYPV | CPU_FEATURE_CMT
+        | CPU_FEATURE_GL,
+    },
+    {
         .name = "NEC UltraSparc I",
         .iu_version = ((0x22ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)
                        | (MAXTL << 8)),
         .fpu_version = 0x00000000,
-        .mmu_version = 0,
+        .mmu_version = mmu_us_12,
         .nwindows = 8,
         .features = CPU_DEFAULT_FEATURES,
     },
@@ -1415,6 +1455,9 @@ static const char * const feature_name[] = {
     "vis1",
     "vis2",
     "fsmuld",
+    "hypv",
+    "cmt",
+    "gl",
 };
 
 static void print_features(FILE *f,
@@ -1563,11 +1606,14 @@ void sparc_cpu_list(FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
                        sparc_defs[i].features, "+");
         (*cpu_fprintf)(f, "\n");
     }
-    (*cpu_fprintf)(f, "CPU feature flags (+/-): ");
-    print_features(f, cpu_fprintf, -1, NULL);
+    (*cpu_fprintf)(f, "Default CPU feature flags (use '-' to remove): ");
+    print_features(f, cpu_fprintf, CPU_DEFAULT_FEATURES, NULL);
+    (*cpu_fprintf)(f, "\n");
+    (*cpu_fprintf)(f, "Available CPU feature flags (use '+' to add): ");
+    print_features(f, cpu_fprintf, ~CPU_DEFAULT_FEATURES, NULL);
     (*cpu_fprintf)(f, "\n");
-    (*cpu_fprintf)(f, "Numerical features (=): iu_version fpu_version "
-                   "mmu_version nwindows\n");
+    (*cpu_fprintf)(f, "Numerical features (use '=' to set): iu_version "
+                   "fpu_version mmu_version nwindows\n");
 }
 
 #define GET_FLAG(a,b) ((env->psr & a)?b:'-')
@@ -1603,7 +1649,7 @@ void cpu_dump_state(CPUState *env, FILE *f,
     for (i = 0; i < 32; i++) {
         if ((i & 3) == 0)
             cpu_fprintf(f, "%%f%02d:", i);
-        cpu_fprintf(f, " %016lf", env->fpr[i]);
+        cpu_fprintf(f, " %016f", *(float *)&env->fpr[i]);
         if ((i & 3) == 3)
             cpu_fprintf(f, "\n");
     }