//#define DEBUG_FEATURES
//#define DEBUG_PCALL
-typedef struct sparc_def_t sparc_def_t;
-
-struct sparc_def_t {
- const char *name;
- target_ulong iu_version;
- uint32_t fpu_version;
- uint32_t mmu_version;
- uint32_t mmu_bm;
- uint32_t mmu_ctpr_mask;
- uint32_t mmu_cxr_mask;
- uint32_t mmu_sfsr_mask;
- uint32_t mmu_trcr_mask;
- uint32_t features;
- uint32_t nwindows;
-};
-
static int cpu_sparc_find_by_name(sparc_def_t *cpu_def, const char *cpu_model);
/* Sparc MMU emulation */
if ((env->mmuregs[0] & MMU_E) == 0) { /* MMU disabled */
// Boot mode: instruction fetches are taken from PROM
- if (rw == 2 && (env->mmuregs[0] & env->mmu_bm)) {
+ if (rw == 2 && (env->mmuregs[0] & env->def->mmu_bm)) {
*physical = env->prom_addr | (address & 0x7ffffULL);
*prot = PAGE_READ | PAGE_EXEC;
return 0;
#ifdef DEBUG_MMU
printf("DMISS at 0x%" PRIx64 "\n", address);
#endif
+ env->dmmuregs[6] = (address & ~0x1fffULL) | (env->dmmuregs[1] & 0x1fff);
env->exception_index = TT_DMISS;
return 1;
}
#ifdef DEBUG_MMU
printf("TMISS at 0x%" PRIx64 "\n", address);
#endif
+ env->immuregs[6] = (address & ~0x1fffULL) | (env->dmmuregs[1] & 0x1fff);
env->exception_index = TT_TMISS;
return 1;
}
#ifdef TARGET_SPARC64
#ifdef DEBUG_PCALL
-static const char * const excp_names[0x50] = {
+static const char * const excp_names[0x80] = {
[TT_TFAULT] = "Instruction Access Fault",
[TT_TMISS] = "Instruction Access MMU Miss",
[TT_CODE_ACCESS] = "Instruction Access Error",
static int count;
const char *name;
- if (intno < 0 || intno >= 0x180 || (intno > 0x4f && intno < 0x80))
+ if (intno < 0 || intno >= 0x180)
name = "Unknown";
else if (intno >= 0x100)
name = "Trap Instruction";
}
#endif
#if !defined(CONFIG_USER_ONLY)
- if (env->tl == MAXTL) {
- cpu_abort(env, "Trap 0x%04x while trap level is MAXTL, Error state",
- env->exception_index);
+ if (env->tl >= env->maxtl) {
+ cpu_abort(env, "Trap 0x%04x while trap level (%d) >= MAXTL (%d),"
+ " Error state", env->exception_index, env->tl, env->maxtl);
return;
}
#endif
+ if (env->tl < env->maxtl - 1) {
+ env->tl++;
+ } else {
+ env->pstate |= PS_RED;
+ if (env->tl < env->maxtl)
+ env->tl++;
+ }
+ env->tsptr = &env->ts[env->tl & MAXTL_MASK];
env->tsptr->tstate = ((uint64_t)GET_CCR(env) << 32) |
((env->asi & 0xff) << 24) | ((env->pstate & 0xf3f) << 8) |
GET_CWP64(env);
env->tsptr->tpc = env->pc;
env->tsptr->tnpc = env->npc;
env->tsptr->tt = intno;
- change_pstate(PS_PEF | PS_PRIV | PS_AG);
-
+ if (!(env->def->features & CPU_FEATURE_GL)) {
+ switch (intno) {
+ case TT_IVEC:
+ change_pstate(PS_PEF | PS_PRIV | PS_IG);
+ break;
+ case TT_TFAULT:
+ case TT_TMISS:
+ case TT_DFAULT:
+ case TT_DMISS:
+ case TT_DPROT:
+ change_pstate(PS_PEF | PS_PRIV | PS_MG);
+ break;
+ default:
+ change_pstate(PS_PEF | PS_PRIV | PS_AG);
+ break;
+ }
+ }
if (intno == TT_CLRWIN)
cpu_set_cwp(env, cpu_cwp_dec(env, env->cwp - 1));
else if ((intno & 0x1c0) == TT_SPILL)
cpu_set_cwp(env, cpu_cwp_inc(env, env->cwp + 1));
env->tbr &= ~0x7fffULL;
env->tbr |= ((env->tl > 1) ? 1 << 14 : 0) | (intno << 5);
- if (env->tl < MAXTL - 1) {
- env->tl++;
- } else {
- env->pstate |= PS_RED;
- if (env->tl != MAXTL)
- env->tl++;
- }
- env->tsptr = &env->ts[env->tl];
env->pc = env->tbr;
env->npc = env->pc + 4;
env->exception_index = 0;
#ifdef TARGET_SPARC64
env->pstate = PS_PRIV;
env->hpstate = HS_PRIV;
- env->pc = 0x1fff0000000ULL;
- env->tsptr = &env->ts[env->tl];
+ env->pc = 0x1fff0000020ULL; // XXX should be different for system_reset
+ env->tsptr = &env->ts[env->tl & MAXTL_MASK];
#else
env->pc = 0;
env->mmuregs[0] &= ~(MMU_E | MMU_NF);
- env->mmuregs[0] |= env->mmu_bm;
+ env->mmuregs[0] |= env->def->mmu_bm;
#endif
env->npc = env->pc + 4;
#endif
if (cpu_sparc_find_by_name(def, cpu_model) < 0)
return -1;
- env->features = def->features;
+ env->def = qemu_mallocz(sizeof(*def));
+ memcpy(env->def, def, sizeof(*def));
+#if defined(CONFIG_USER_ONLY)
+ if ((env->def->features & CPU_FEATURE_FLOAT))
+ env->def->features |= CPU_FEATURE_FLOAT128;
+#endif
env->cpu_model_str = cpu_model;
env->version = def->iu_version;
env->fsr = def->fpu_version;
env->nwindows = def->nwindows;
#if !defined(TARGET_SPARC64)
- env->mmu_bm = def->mmu_bm;
- env->mmu_ctpr_mask = def->mmu_ctpr_mask;
- env->mmu_cxr_mask = def->mmu_cxr_mask;
- env->mmu_sfsr_mask = def->mmu_sfsr_mask;
- env->mmu_trcr_mask = def->mmu_trcr_mask;
env->mmuregs[0] |= def->mmu_version;
cpu_sparc_set_id(env, 0);
#else
+ env->mmu_version = def->mmu_version;
+ env->maxtl = def->maxtl;
+ env->version |= def->maxtl << 8;
env->version |= def->nwindows - 1;
#endif
return 0;
static void cpu_sparc_close(CPUSPARCState *env)
{
+ free(env->def);
free(env);
}
#ifdef TARGET_SPARC64
{
.name = "Fujitsu Sparc64",
- .iu_version = ((0x04ULL << 48) | (0x02ULL << 32) | (0ULL << 24)
- | (MAXTL << 8)),
+ .iu_version = ((0x04ULL << 48) | (0x02ULL << 32) | (0ULL << 24)),
.fpu_version = 0x00000000,
- .mmu_version = 0,
+ .mmu_version = mmu_us_12,
.nwindows = 4,
+ .maxtl = 4,
.features = CPU_DEFAULT_FEATURES,
},
{
.name = "Fujitsu Sparc64 III",
- .iu_version = ((0x04ULL << 48) | (0x03ULL << 32) | (0ULL << 24)
- | (MAXTL << 8)),
+ .iu_version = ((0x04ULL << 48) | (0x03ULL << 32) | (0ULL << 24)),
.fpu_version = 0x00000000,
- .mmu_version = 0,
+ .mmu_version = mmu_us_12,
.nwindows = 5,
+ .maxtl = 4,
.features = CPU_DEFAULT_FEATURES,
},
{
.name = "Fujitsu Sparc64 IV",
- .iu_version = ((0x04ULL << 48) | (0x04ULL << 32) | (0ULL << 24)
- | (MAXTL << 8)),
+ .iu_version = ((0x04ULL << 48) | (0x04ULL << 32) | (0ULL << 24)),
.fpu_version = 0x00000000,
- .mmu_version = 0,
+ .mmu_version = mmu_us_12,
.nwindows = 8,
+ .maxtl = 5,
.features = CPU_DEFAULT_FEATURES,
},
{
.name = "Fujitsu Sparc64 V",
- .iu_version = ((0x04ULL << 48) | (0x05ULL << 32) | (0x51ULL << 24)
- | (MAXTL << 8)),
+ .iu_version = ((0x04ULL << 48) | (0x05ULL << 32) | (0x51ULL << 24)),
.fpu_version = 0x00000000,
- .mmu_version = 0,
+ .mmu_version = mmu_us_12,
.nwindows = 8,
+ .maxtl = 5,
.features = CPU_DEFAULT_FEATURES,
},
{
.name = "TI UltraSparc I",
- .iu_version = ((0x17ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)
- | (MAXTL << 8)),
+ .iu_version = ((0x17ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)),
.fpu_version = 0x00000000,
- .mmu_version = 0,
+ .mmu_version = mmu_us_12,
.nwindows = 8,
+ .maxtl = 5,
.features = CPU_DEFAULT_FEATURES,
},
{
.name = "TI UltraSparc II",
- .iu_version = ((0x17ULL << 48) | (0x11ULL << 32) | (0x20ULL << 24)
- | (MAXTL << 8)),
+ .iu_version = ((0x17ULL << 48) | (0x11ULL << 32) | (0x20ULL << 24)),
.fpu_version = 0x00000000,
- .mmu_version = 0,
+ .mmu_version = mmu_us_12,
.nwindows = 8,
+ .maxtl = 5,
.features = CPU_DEFAULT_FEATURES,
},
{
.name = "TI UltraSparc IIi",
- .iu_version = ((0x17ULL << 48) | (0x12ULL << 32) | (0x91ULL << 24)
- | (MAXTL << 8)),
+ .iu_version = ((0x17ULL << 48) | (0x12ULL << 32) | (0x91ULL << 24)),
.fpu_version = 0x00000000,
- .mmu_version = 0,
+ .mmu_version = mmu_us_12,
.nwindows = 8,
+ .maxtl = 5,
.features = CPU_DEFAULT_FEATURES,
},
{
.name = "TI UltraSparc IIe",
- .iu_version = ((0x17ULL << 48) | (0x13ULL << 32) | (0x14ULL << 24)
- | (MAXTL << 8)),
+ .iu_version = ((0x17ULL << 48) | (0x13ULL << 32) | (0x14ULL << 24)),
.fpu_version = 0x00000000,
- .mmu_version = 0,
+ .mmu_version = mmu_us_12,
.nwindows = 8,
+ .maxtl = 5,
.features = CPU_DEFAULT_FEATURES,
},
{
.name = "Sun UltraSparc III",
- .iu_version = ((0x3eULL << 48) | (0x14ULL << 32) | (0x34ULL << 24)
- | (MAXTL << 8)),
+ .iu_version = ((0x3eULL << 48) | (0x14ULL << 32) | (0x34ULL << 24)),
.fpu_version = 0x00000000,
- .mmu_version = 0,
+ .mmu_version = mmu_us_12,
.nwindows = 8,
+ .maxtl = 5,
.features = CPU_DEFAULT_FEATURES,
},
{
.name = "Sun UltraSparc III Cu",
- .iu_version = ((0x3eULL << 48) | (0x15ULL << 32) | (0x41ULL << 24)
- | (MAXTL << 8)),
+ .iu_version = ((0x3eULL << 48) | (0x15ULL << 32) | (0x41ULL << 24)),
.fpu_version = 0x00000000,
- .mmu_version = 0,
+ .mmu_version = mmu_us_3,
.nwindows = 8,
+ .maxtl = 5,
.features = CPU_DEFAULT_FEATURES,
},
{
.name = "Sun UltraSparc IIIi",
- .iu_version = ((0x3eULL << 48) | (0x16ULL << 32) | (0x34ULL << 24)
- | (MAXTL << 8)),
+ .iu_version = ((0x3eULL << 48) | (0x16ULL << 32) | (0x34ULL << 24)),
.fpu_version = 0x00000000,
- .mmu_version = 0,
+ .mmu_version = mmu_us_12,
.nwindows = 8,
+ .maxtl = 5,
.features = CPU_DEFAULT_FEATURES,
},
{
.name = "Sun UltraSparc IV",
- .iu_version = ((0x3eULL << 48) | (0x18ULL << 32) | (0x31ULL << 24)
- | (MAXTL << 8)),
+ .iu_version = ((0x3eULL << 48) | (0x18ULL << 32) | (0x31ULL << 24)),
.fpu_version = 0x00000000,
- .mmu_version = 0,
+ .mmu_version = mmu_us_4,
.nwindows = 8,
+ .maxtl = 5,
.features = CPU_DEFAULT_FEATURES,
},
{
.name = "Sun UltraSparc IV+",
- .iu_version = ((0x3eULL << 48) | (0x19ULL << 32) | (0x22ULL << 24)
- | (MAXTL << 8)),
+ .iu_version = ((0x3eULL << 48) | (0x19ULL << 32) | (0x22ULL << 24)),
.fpu_version = 0x00000000,
- .mmu_version = 0,
+ .mmu_version = mmu_us_12,
.nwindows = 8,
- .features = CPU_DEFAULT_FEATURES,
+ .maxtl = 5,
+ .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_CMT,
},
{
.name = "Sun UltraSparc IIIi+",
- .iu_version = ((0x3eULL << 48) | (0x22ULL << 32) | (0ULL << 24)
- | (MAXTL << 8)),
+ .iu_version = ((0x3eULL << 48) | (0x22ULL << 32) | (0ULL << 24)),
.fpu_version = 0x00000000,
- .mmu_version = 0,
+ .mmu_version = mmu_us_3,
.nwindows = 8,
+ .maxtl = 5,
.features = CPU_DEFAULT_FEATURES,
},
{
+ .name = "Sun UltraSparc T1",
+ // defined in sparc_ifu_fdp.v and ctu.h
+ .iu_version = ((0x3eULL << 48) | (0x23ULL << 32) | (0x02ULL << 24)),
+ .fpu_version = 0x00000000,
+ .mmu_version = mmu_sun4v,
+ .nwindows = 8,
+ .maxtl = 6,
+ .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_HYPV | CPU_FEATURE_CMT
+ | CPU_FEATURE_GL,
+ },
+ {
+ .name = "Sun UltraSparc T2",
+ // defined in tlu_asi_ctl.v and n2_revid_cust.v
+ .iu_version = ((0x3eULL << 48) | (0x24ULL << 32) | (0x02ULL << 24)),
+ .fpu_version = 0x00000000,
+ .mmu_version = mmu_sun4v,
+ .nwindows = 8,
+ .maxtl = 6,
+ .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_HYPV | CPU_FEATURE_CMT
+ | CPU_FEATURE_GL,
+ },
+ {
.name = "NEC UltraSparc I",
- .iu_version = ((0x22ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)
- | (MAXTL << 8)),
+ .iu_version = ((0x22ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)),
.fpu_version = 0x00000000,
- .mmu_version = 0,
+ .mmu_version = mmu_us_12,
.nwindows = 8,
+ .maxtl = 5,
.features = CPU_DEFAULT_FEATURES,
},
#else
"vis1",
"vis2",
"fsmuld",
+ "hypv",
+ "cmt",
+ "gl",
};
static void print_features(FILE *f,
sparc_defs[i].features, "+");
(*cpu_fprintf)(f, "\n");
}
- (*cpu_fprintf)(f, "CPU feature flags (+/-): ");
- print_features(f, cpu_fprintf, -1, NULL);
+ (*cpu_fprintf)(f, "Default CPU feature flags (use '-' to remove): ");
+ print_features(f, cpu_fprintf, CPU_DEFAULT_FEATURES, NULL);
+ (*cpu_fprintf)(f, "\n");
+ (*cpu_fprintf)(f, "Available CPU feature flags (use '+' to add): ");
+ print_features(f, cpu_fprintf, ~CPU_DEFAULT_FEATURES, NULL);
(*cpu_fprintf)(f, "\n");
- (*cpu_fprintf)(f, "Numerical features (=): iu_version fpu_version "
- "mmu_version nwindows\n");
+ (*cpu_fprintf)(f, "Numerical features (use '=' to set): iu_version "
+ "fpu_version mmu_version nwindows\n");
}
#define GET_FLAG(a,b) ((env->psr & a)?b:'-')
for (i = 0; i < 32; i++) {
if ((i & 3) == 0)
cpu_fprintf(f, "%%f%02d:", i);
- cpu_fprintf(f, " %016lf", env->fpr[i]);
+ cpu_fprintf(f, " %016f", *(float *)&env->fpr[i]);
if ((i & 3) == 3)
cpu_fprintf(f, "\n");
}
projects / qemu / blobdiff