//#define DEBUG_PCALL
//#define DEBUG_MMU
+//#define DEBUG_UNALIGNED
+//#define DEBUG_UNASSIGNED
void raise_exception(int tt)
{
env->exception_index = tt;
cpu_loop_exit();
-}
+}
+
+void check_ieee_exceptions()
+{
+ T0 = get_float_exception_flags(&env->fp_status);
+ if (T0)
+ {
+ /* Copy IEEE 754 flags into FSR */
+ if (T0 & float_flag_invalid)
+ env->fsr |= FSR_NVC;
+ if (T0 & float_flag_overflow)
+ env->fsr |= FSR_OFC;
+ if (T0 & float_flag_underflow)
+ env->fsr |= FSR_UFC;
+ if (T0 & float_flag_divbyzero)
+ env->fsr |= FSR_DZC;
+ if (T0 & float_flag_inexact)
+ env->fsr |= FSR_NXC;
+
+ if ((env->fsr & FSR_CEXC_MASK) & ((env->fsr & FSR_TEM_MASK) >> 23))
+ {
+ /* Unmasked exception, generate a trap */
+ env->fsr |= FSR_FTT_IEEE_EXCP;
+ raise_exception(TT_FP_EXCP);
+ }
+ else
+ {
+ /* Accumulate exceptions */
+ env->fsr |= (env->fsr & FSR_CEXC_MASK) << 5;
+ }
+ }
+}
#ifdef USE_INT_TO_FLOAT_HELPERS
void do_fitos(void)
{
- FT0 = (float) *((int32_t *)&FT1);
+ set_float_exception_flags(0, &env->fp_status);
+ FT0 = int32_to_float32(*((int32_t *)&FT1), &env->fp_status);
+ check_ieee_exceptions();
}
void do_fitod(void)
{
- DT0 = (double) *((int32_t *)&FT1);
+ DT0 = int32_to_float64(*((int32_t *)&FT1), &env->fp_status);
}
#endif
void do_fsqrts(void)
{
+ set_float_exception_flags(0, &env->fp_status);
FT0 = float32_sqrt(FT1, &env->fp_status);
+ check_ieee_exceptions();
}
void do_fsqrtd(void)
{
+ set_float_exception_flags(0, &env->fp_status);
DT0 = float64_sqrt(DT1, &env->fp_status);
+ check_ieee_exceptions();
}
-#define FS 0
-void do_fcmps (void)
-{
- env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS);
- if (isnan(FT0) || isnan(FT1)) {
- T0 = (FSR_FCC1 | FSR_FCC0) << FS;
- if (env->fsr & FSR_NVM) {
- env->fsr |= T0;
- raise_exception(TT_FP_EXCP);
- } else {
- env->fsr |= FSR_NVA;
- }
- } else if (FT0 < FT1) {
- T0 = FSR_FCC0 << FS;
- } else if (FT0 > FT1) {
- T0 = FSR_FCC1 << FS;
- } else {
- T0 = 0;
+#define GEN_FCMP(name, size, reg1, reg2, FS, TRAP) \
+ void glue(do_, name) (void) \
+ { \
+ env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
+ switch (glue(size, _compare) (reg1, reg2, &env->fp_status)) { \
+ case float_relation_unordered: \
+ T0 = (FSR_FCC1 | FSR_FCC0) << FS; \
+ if ((env->fsr & FSR_NVM) || TRAP) { \
+ env->fsr |= T0; \
+ env->fsr |= FSR_NVC; \
+ env->fsr |= FSR_FTT_IEEE_EXCP; \
+ raise_exception(TT_FP_EXCP); \
+ } else { \
+ env->fsr |= FSR_NVA; \
+ } \
+ break; \
+ case float_relation_less: \
+ T0 = FSR_FCC0 << FS; \
+ break; \
+ case float_relation_greater: \
+ T0 = FSR_FCC1 << FS; \
+ break; \
+ default: \
+ T0 = 0; \
+ break; \
+ } \
+ env->fsr |= T0; \
}
- env->fsr |= T0;
-}
-void do_fcmpd (void)
-{
- env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS);
- if (isnan(DT0) || isnan(DT1)) {
- T0 = (FSR_FCC1 | FSR_FCC0) << FS;
- if (env->fsr & FSR_NVM) {
- env->fsr |= T0;
- raise_exception(TT_FP_EXCP);
- } else {
- env->fsr |= FSR_NVA;
- }
- } else if (DT0 < DT1) {
- T0 = FSR_FCC0 << FS;
- } else if (DT0 > DT1) {
- T0 = FSR_FCC1 << FS;
- } else {
- T0 = 0;
- }
- env->fsr |= T0;
-}
+GEN_FCMP(fcmps, float32, FT0, FT1, 0, 0);
+GEN_FCMP(fcmpd, float64, DT0, DT1, 0, 0);
+
+GEN_FCMP(fcmpes, float32, FT0, FT1, 0, 1);
+GEN_FCMP(fcmped, float64, DT0, DT1, 0, 1);
#ifdef TARGET_SPARC64
-#undef FS
-#define FS 22
-void do_fcmps_fcc1 (void)
-{
- env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS);
- if (isnan(FT0) || isnan(FT1)) {
- T0 = (FSR_FCC1 | FSR_FCC0) << FS;
- if (env->fsr & FSR_NVM) {
- env->fsr |= T0;
- raise_exception(TT_FP_EXCP);
- } else {
- env->fsr |= FSR_NVA;
- }
- } else if (FT0 < FT1) {
- T0 = FSR_FCC0 << FS;
- } else if (FT0 > FT1) {
- T0 = FSR_FCC1 << FS;
- } else {
- T0 = 0;
- }
- env->fsr |= T0;
-}
+GEN_FCMP(fcmps_fcc1, float32, FT0, FT1, 22, 0);
+GEN_FCMP(fcmpd_fcc1, float64, DT0, DT1, 22, 0);
-void do_fcmpd_fcc1 (void)
-{
- env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS);
- if (isnan(DT0) || isnan(DT1)) {
- T0 = (FSR_FCC1 | FSR_FCC0) << FS;
- if (env->fsr & FSR_NVM) {
- env->fsr |= T0;
- raise_exception(TT_FP_EXCP);
- } else {
- env->fsr |= FSR_NVA;
- }
- } else if (DT0 < DT1) {
- T0 = FSR_FCC0 << FS;
- } else if (DT0 > DT1) {
- T0 = FSR_FCC1 << FS;
- } else {
- T0 = 0;
- }
- env->fsr |= T0;
-}
+GEN_FCMP(fcmps_fcc2, float32, FT0, FT1, 24, 0);
+GEN_FCMP(fcmpd_fcc2, float64, DT0, DT1, 24, 0);
-#undef FS
-#define FS 24
-void do_fcmps_fcc2 (void)
-{
- env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS);
- if (isnan(FT0) || isnan(FT1)) {
- T0 = (FSR_FCC1 | FSR_FCC0) << FS;
- if (env->fsr & FSR_NVM) {
- env->fsr |= T0;
- raise_exception(TT_FP_EXCP);
- } else {
- env->fsr |= FSR_NVA;
- }
- } else if (FT0 < FT1) {
- T0 = FSR_FCC0 << FS;
- } else if (FT0 > FT1) {
- T0 = FSR_FCC1 << FS;
- } else {
- T0 = 0;
- }
- env->fsr |= T0;
-}
+GEN_FCMP(fcmps_fcc3, float32, FT0, FT1, 26, 0);
+GEN_FCMP(fcmpd_fcc3, float64, DT0, DT1, 26, 0);
-void do_fcmpd_fcc2 (void)
-{
- env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS);
- if (isnan(DT0) || isnan(DT1)) {
- T0 = (FSR_FCC1 | FSR_FCC0) << FS;
- if (env->fsr & FSR_NVM) {
- env->fsr |= T0;
- raise_exception(TT_FP_EXCP);
- } else {
- env->fsr |= FSR_NVA;
- }
- } else if (DT0 < DT1) {
- T0 = FSR_FCC0 << FS;
- } else if (DT0 > DT1) {
- T0 = FSR_FCC1 << FS;
- } else {
- T0 = 0;
- }
- env->fsr |= T0;
-}
+GEN_FCMP(fcmpes_fcc1, float32, FT0, FT1, 22, 1);
+GEN_FCMP(fcmped_fcc1, float64, DT0, DT1, 22, 1);
-#undef FS
-#define FS 26
-void do_fcmps_fcc3 (void)
-{
- env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS);
- if (isnan(FT0) || isnan(FT1)) {
- T0 = (FSR_FCC1 | FSR_FCC0) << FS;
- if (env->fsr & FSR_NVM) {
- env->fsr |= T0;
- raise_exception(TT_FP_EXCP);
- } else {
- env->fsr |= FSR_NVA;
- }
- } else if (FT0 < FT1) {
- T0 = FSR_FCC0 << FS;
- } else if (FT0 > FT1) {
- T0 = FSR_FCC1 << FS;
- } else {
- T0 = 0;
- }
- env->fsr |= T0;
-}
+GEN_FCMP(fcmpes_fcc2, float32, FT0, FT1, 24, 1);
+GEN_FCMP(fcmped_fcc2, float64, DT0, DT1, 24, 1);
-void do_fcmpd_fcc3 (void)
-{
- env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS);
- if (isnan(DT0) || isnan(DT1)) {
- T0 = (FSR_FCC1 | FSR_FCC0) << FS;
- if (env->fsr & FSR_NVM) {
- env->fsr |= T0;
- raise_exception(TT_FP_EXCP);
- } else {
- env->fsr |= FSR_NVA;
- }
- } else if (DT0 < DT1) {
- T0 = FSR_FCC0 << FS;
- } else if (DT0 > DT1) {
- T0 = FSR_FCC1 << FS;
- } else {
- T0 = 0;
- }
- env->fsr |= T0;
-}
-#undef FS
+GEN_FCMP(fcmpes_fcc3, float32, FT0, FT1, 26, 1);
+GEN_FCMP(fcmped_fcc3, float64, DT0, DT1, 26, 1);
#endif
-#if defined(CONFIG_USER_ONLY)
+#if defined(CONFIG_USER_ONLY)
void helper_ld_asi(int asi, int size, int sign)
{
}
uint32_t ret = 0;
switch (asi) {
+ case 2: /* SuperSparc MXCC registers */
+ break;
case 3: /* MMU probe */
{
int mmulev;
case 4: /* read MMU regs */
{
int reg = (T0 >> 8) & 0xf;
-
+
ret = env->mmuregs[reg];
if (reg == 3) /* Fault status cleared on read */
env->mmuregs[reg] = 0;
#endif
}
break;
- case 0x20 ... 0x2f: /* MMU passthrough */
+ case 9: /* Supervisor code access */
+ switch(size) {
+ case 1:
+ ret = ldub_code(T0);
+ break;
+ case 2:
+ ret = lduw_code(T0 & ~1);
+ break;
+ default:
+ case 4:
+ ret = ldl_code(T0 & ~3);
+ break;
+ case 8:
+ ret = ldl_code(T0 & ~3);
+ T0 = ldl_code((T0 + 4) & ~3);
+ break;
+ }
+ break;
+ case 0xc: /* I-cache tag */
+ case 0xd: /* I-cache data */
+ case 0xe: /* D-cache tag */
+ case 0xf: /* D-cache data */
+ break;
+ case 0x20: /* MMU passthrough */
switch(size) {
case 1:
ret = ldub_phys(T0);
break;
}
break;
+ case 0x2e: /* MMU passthrough, 0xexxxxxxxx */
+ case 0x2f: /* MMU passthrough, 0xfxxxxxxxx */
+ switch(size) {
+ case 1:
+ ret = ldub_phys((target_phys_addr_t)T0
+ | ((target_phys_addr_t)(asi & 0xf) << 32));
+ break;
+ case 2:
+ ret = lduw_phys((target_phys_addr_t)(T0 & ~1)
+ | ((target_phys_addr_t)(asi & 0xf) << 32));
+ break;
+ default:
+ case 4:
+ ret = ldl_phys((target_phys_addr_t)(T0 & ~3)
+ | ((target_phys_addr_t)(asi & 0xf) << 32));
+ break;
+ case 8:
+ ret = ldl_phys((target_phys_addr_t)(T0 & ~3)
+ | ((target_phys_addr_t)(asi & 0xf) << 32));
+ T0 = ldl_phys((target_phys_addr_t)((T0 + 4) & ~3)
+ | ((target_phys_addr_t)(asi & 0xf) << 32));
+ break;
+ }
+ break;
+ case 0x21 ... 0x2d: /* MMU passthrough, unassigned */
default:
+ do_unassigned_access(T0, 0, 0, 1);
ret = 0;
break;
}
void helper_st_asi(int asi, int size, int sign)
{
switch(asi) {
+ case 2: /* SuperSparc MXCC registers */
+ break;
case 3: /* MMU flush */
{
int mmulev;
{
int reg = (T0 >> 8) & 0xf;
uint32_t oldreg;
-
+
oldreg = env->mmuregs[reg];
switch(reg) {
case 0:
#endif
return;
}
+ case 0xc: /* I-cache tag */
+ case 0xd: /* I-cache data */
+ case 0xe: /* D-cache tag */
+ case 0xf: /* D-cache data */
+ case 0x10: /* I/D-cache flush page */
+ case 0x11: /* I/D-cache flush segment */
+ case 0x12: /* I/D-cache flush region */
+ case 0x13: /* I/D-cache flush context */
+ case 0x14: /* I/D-cache flush user */
+ break;
case 0x17: /* Block copy, sta access */
{
// value (T1) = src
// address (T0) = dst
// copy 32 bytes
- uint32_t src = T1, dst = T0;
- uint8_t temp[32];
-
- tswap32s(&src);
+ unsigned int i;
+ uint32_t src = T1 & ~3, dst = T0 & ~3, temp;
- cpu_physical_memory_read(src, (void *) &temp, 32);
- cpu_physical_memory_write(dst, (void *) &temp, 32);
+ for (i = 0; i < 32; i += 4, src += 4, dst += 4) {
+ temp = ldl_kernel(src);
+ stl_kernel(dst, temp);
+ }
}
return;
case 0x1f: /* Block fill, stda access */
// value (T1, T2)
// address (T0) = dst
// fill 32 bytes
- int i;
- uint32_t dst = T0;
- uint64_t val;
-
- val = (((uint64_t)T1) << 32) | T2;
- tswap64s(&val);
-
- for (i = 0; i < 32; i += 8, dst += 8) {
- cpu_physical_memory_write(dst, (void *) &val, 8);
- }
+ unsigned int i;
+ uint32_t dst = T0 & 7;
+ uint64_t val;
+
+ val = (((uint64_t)T1) << 32) | T2;
+
+ for (i = 0; i < 32; i += 8, dst += 8)
+ stq_kernel(dst, val);
}
return;
- case 0x20 ... 0x2f: /* MMU passthrough */
+ case 0x20: /* MMU passthrough */
{
switch(size) {
case 1:
}
}
return;
+ case 0x2e: /* MMU passthrough, 0xexxxxxxxx */
+ case 0x2f: /* MMU passthrough, 0xfxxxxxxxx */
+ {
+ switch(size) {
+ case 1:
+ stb_phys((target_phys_addr_t)T0
+ | ((target_phys_addr_t)(asi & 0xf) << 32), T1);
+ break;
+ case 2:
+ stw_phys((target_phys_addr_t)(T0 & ~1)
+ | ((target_phys_addr_t)(asi & 0xf) << 32), T1);
+ break;
+ case 4:
+ default:
+ stl_phys((target_phys_addr_t)(T0 & ~3)
+ | ((target_phys_addr_t)(asi & 0xf) << 32), T1);
+ break;
+ case 8:
+ stl_phys((target_phys_addr_t)(T0 & ~3)
+ | ((target_phys_addr_t)(asi & 0xf) << 32), T1);
+ stl_phys((target_phys_addr_t)((T0 + 4) & ~3)
+ | ((target_phys_addr_t)(asi & 0xf) << 32), T1);
+ break;
+ }
+ }
+ return;
+ case 0x31: /* Ross RT620 I-cache flush */
+ case 0x36: /* I-cache flash clear */
+ case 0x37: /* D-cache flash clear */
+ break;
+ case 9: /* Supervisor code access, XXX */
+ case 0x21 ... 0x2d: /* MMU passthrough, unassigned */
default:
+ do_unassigned_access(T0, 1, 0, 1);
return;
}
}
case 0x56: // I-MMU tag read
{
unsigned int i;
-
+
for (i = 0; i < 64; i++) {
// Valid, ctx match, vaddr match
if ((env->itlb_tte[i] & 0x8000000000000000ULL) != 0 &&
case 0x5e: // D-MMU tag read
{
unsigned int i;
-
+
for (i = 0; i < 64; i++) {
// Valid, ctx match, vaddr match
if ((env->dtlb_tte[i] & 0x8000000000000000ULL) != 0 &&
case 0x5f: // D-MMU demap, WO
case 0x77: // Interrupt vector, WO
default:
+ do_unassigned_access(T0, 0, 0, 1);
ret = 0;
break;
}
// invalid in normal mode
if (oldreg != env->lsu) {
#ifdef DEBUG_MMU
- printf("LSU change: 0x%llx -> 0x%llx\n", oldreg, env->lsu);
+ printf("LSU change: 0x%" PRIx64 " -> 0x%" PRIx64 "\n", oldreg, env->lsu);
dump_mmu(env);
#endif
tlb_flush(env, 1);
{
int reg = (T0 >> 3) & 0xf;
uint64_t oldreg;
-
+
oldreg = env->immuregs[reg];
switch(reg) {
case 0: // RO
env->immuregs[reg] = T1;
#ifdef DEBUG_MMU
if (oldreg != env->immuregs[reg]) {
- printf("mmu change reg[%d]: 0x%08llx -> 0x%08llx\n", reg, oldreg, env->immuregs[reg]);
+ printf("mmu change reg[%d]: 0x%08" PRIx64 " -> 0x%08" PRIx64 "\n", reg, oldreg, env->immuregs[reg]);
}
dump_mmu(env);
#endif
{
int reg = (T0 >> 3) & 0xf;
uint64_t oldreg;
-
+
oldreg = env->dmmuregs[reg];
switch(reg) {
case 0: // RO
env->dmmuregs[reg] = T1;
#ifdef DEBUG_MMU
if (oldreg != env->dmmuregs[reg]) {
- printf("mmu change reg[%d]: 0x%08llx -> 0x%08llx\n", reg, oldreg, env->dmmuregs[reg]);
+ printf("mmu change reg[%d]: 0x%08" PRIx64 " -> 0x%08" PRIx64 "\n", reg, oldreg, env->dmmuregs[reg]);
}
dump_mmu(env);
#endif
case 0x8a: // Primary no-fault LE, RO
case 0x8b: // Secondary no-fault LE, RO
default:
+ do_unassigned_access(T0, 1, 0, 1);
return;
}
}
{
unsigned int cwp;
+ if (env->psret == 1)
+ raise_exception(TT_ILL_INSN);
+
env->psret = 1;
- cwp = (env->cwp + 1) & (NWINDOWS - 1);
+ cwp = (env->cwp + 1) & (NWINDOWS - 1);
if (env->wim & (1 << cwp)) {
raise_exception(TT_WIN_UNF);
}
set_float_rounding_mode(rnd_mode, &env->fp_status);
}
-void cpu_get_fp64(uint64_t *pmant, uint16_t *pexp, double f)
-{
- int exptemp;
-
- *pmant = ldexp(frexp(f, &exptemp), 53);
- *pexp = exptemp;
-}
-
-double cpu_put_fp64(uint64_t mant, uint16_t exp)
-{
- return ldexp((double) mant, exp - 53);
-}
-
void helper_debug()
{
env->exception_index = EXCP_DEBUG;
#ifndef TARGET_SPARC64
void do_wrpsr()
{
- PUT_PSR(env, T0);
+ if ((T0 & PSR_CWP) >= NWINDOWS)
+ raise_exception(TT_ILL_INSN);
+ else
+ PUT_PSR(env, T0);
}
void do_rdpsr()
}
}
-void do_wrpstate()
+static inline void change_pstate(uint64_t new_pstate)
{
- uint64_t new_pstate, pstate_regs, new_pstate_regs;
+ uint64_t pstate_regs, new_pstate_regs;
uint64_t *src, *dst;
- new_pstate = T0 & 0xf3f;
pstate_regs = env->pstate & 0xc01;
new_pstate_regs = new_pstate & 0xc01;
if (new_pstate_regs != pstate_regs) {
env->pstate = new_pstate;
}
+void do_wrpstate(void)
+{
+ change_pstate(T0 & 0xf3f);
+}
+
void do_done(void)
{
env->tl--;
env->npc = env->tnpc[env->tl] + 4;
PUT_CCR(env, env->tstate[env->tl] >> 32);
env->asi = (env->tstate[env->tl] >> 24) & 0xff;
- env->pstate = (env->tstate[env->tl] >> 8) & 0xfff;
- set_cwp(env->tstate[env->tl] & 0xff);
+ change_pstate((env->tstate[env->tl] >> 8) & 0xf3f);
+ PUT_CWP64(env, env->tstate[env->tl] & 0xff);
}
void do_retry(void)
env->npc = env->tnpc[env->tl];
PUT_CCR(env, env->tstate[env->tl] >> 32);
env->asi = (env->tstate[env->tl] >> 24) & 0xff;
- env->pstate = (env->tstate[env->tl] >> 8) & 0xfff;
- set_cwp(env->tstate[env->tl] & 0xff);
+ change_pstate((env->tstate[env->tl] >> 8) & 0xf3f);
+ PUT_CWP64(env, env->tstate[env->tl] & 0xff);
}
#endif
#ifdef DEBUG_PCALL
if (loglevel & CPU_LOG_INT) {
static int count;
- fprintf(logfile, "%6d: v=%04x pc=%016llx npc=%016llx SP=%016llx\n",
+ fprintf(logfile, "%6d: v=%04x pc=%016" PRIx64 " npc=%016" PRIx64 " SP=%016" PRIx64 "\n",
count, intno,
env->pc,
env->npc, env->regwptr[6]);
count++;
}
#endif
-#if !defined(CONFIG_USER_ONLY)
+#if !defined(CONFIG_USER_ONLY)
if (env->tl == MAXTL) {
cpu_abort(env, "Trap 0x%04x while trap level is MAXTL, Error state", env->exception_index);
return;
}
#endif
env->tstate[env->tl] = ((uint64_t)GET_CCR(env) << 32) | ((env->asi & 0xff) << 24) |
- ((env->pstate & 0xfff) << 8) | (env->cwp & 0xff);
+ ((env->pstate & 0xf3f) << 8) | GET_CWP64(env);
env->tpc[env->tl] = env->pc;
env->tnpc[env->tl] = env->npc;
env->tt[env->tl] = intno;
- env->pstate = PS_PEF | PS_PRIV | PS_AG;
+ change_pstate(PS_PEF | PS_PRIV | PS_AG);
+
+ if (intno == TT_CLRWIN)
+ set_cwp((env->cwp - 1) & (NWINDOWS - 1));
+ else if ((intno & 0x1c0) == TT_SPILL)
+ set_cwp((env->cwp - env->cansave - 2) & (NWINDOWS - 1));
+ else if ((intno & 0x1c0) == TT_FILL)
+ set_cwp((env->cwp + 1) & (NWINDOWS - 1));
env->tbr &= ~0x7fffULL;
env->tbr |= ((env->tl > 1) ? 1 << 14 : 0) | (intno << 5);
if (env->tl < MAXTL - 1) {
count++;
}
#endif
-#if !defined(CONFIG_USER_ONLY)
+#if !defined(CONFIG_USER_ONLY)
if (env->psret == 0) {
cpu_abort(env, "Trap 0x%02x while interrupts disabled, Error state", env->exception_index);
return;
}
#endif
env->psret = 0;
- cwp = (env->cwp - 1) & (NWINDOWS - 1);
+ cwp = (env->cwp - 1) & (NWINDOWS - 1);
set_cwp(cwp);
env->regwptr[9] = env->pc;
env->regwptr[10] = env->npc;
}
#endif
-#if !defined(CONFIG_USER_ONLY)
+#if !defined(CONFIG_USER_ONLY)
+
+static void do_unaligned_access(target_ulong addr, int is_write, int is_user,
+ void *retaddr);
#define MMUSUFFIX _mmu
+#define ALIGNED_ONLY
#define GETPC() (__builtin_return_address(0))
#define SHIFT 0
#define SHIFT 3
#include "softmmu_template.h"
+static void do_unaligned_access(target_ulong addr, int is_write, int is_user,
+ void *retaddr)
+{
+#ifdef DEBUG_UNALIGNED
+ printf("Unaligned access to 0x%x from 0x%x\n", addr, env->pc);
+#endif
+ raise_exception(TT_UNALIGNED);
+}
/* try to fill the TLB and return an exception if error. If retaddr is
NULL, it means that the function was called in C code (i.e. not
}
#endif
+
+#ifndef TARGET_SPARC64
+void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
+ int is_asi)
+{
+ CPUState *saved_env;
+
+ /* XXX: hack to restore env in all cases, even if not called from
+ generated code */
+ saved_env = env;
+ env = cpu_single_env;
+ if (env->mmuregs[3]) /* Fault status register */
+ env->mmuregs[3] = 1; /* overflow (not read before another fault) */
+ if (is_asi)
+ env->mmuregs[3] |= 1 << 16;
+ if (env->psrs)
+ env->mmuregs[3] |= 1 << 5;
+ if (is_exec)
+ env->mmuregs[3] |= 1 << 6;
+ if (is_write)
+ env->mmuregs[3] |= 1 << 7;
+ env->mmuregs[3] |= (5 << 2) | 2;
+ env->mmuregs[4] = addr; /* Fault address register */
+ if ((env->mmuregs[0] & MMU_E) && !(env->mmuregs[0] & MMU_NF)) {
+#ifdef DEBUG_UNASSIGNED
+ printf("Unassigned mem access to " TARGET_FMT_plx " from " TARGET_FMT_lx
+ "\n", addr, env->pc);
+#endif
+ if (is_exec)
+ raise_exception(TT_CODE_ACCESS);
+ else
+ raise_exception(TT_DATA_ACCESS);
+ }
+ env = saved_env;
+}
+#else
+void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
+ int is_asi)
+{
+#ifdef DEBUG_UNASSIGNED
+ CPUState *saved_env;
+
+ /* XXX: hack to restore env in all cases, even if not called from
+ generated code */
+ saved_env = env;
+ env = cpu_single_env;
+ printf("Unassigned mem access to " TARGET_FMT_plx " from " TARGET_FMT_lx "\n",
+ addr, env->pc);
+ env = saved_env;
+#endif
+ if (is_exec)
+ raise_exception(TT_CODE_ACCESS);
+ else
+ raise_exception(TT_DATA_ACCESS);
+}
+#endif
+
+#ifdef TARGET_SPARC64
+void do_tick_set_count(void *opaque, uint64_t count)
+{
+#if !defined(CONFIG_USER_ONLY)
+ ptimer_set_count(opaque, -count);
+#endif
+}
+
+uint64_t do_tick_get_count(void *opaque)
+{
+#if !defined(CONFIG_USER_ONLY)
+ return -ptimer_get_count(opaque);
+#else
+ return 0;
+#endif
+}
+
+void do_tick_set_limit(void *opaque, uint64_t limit)
+{
+#if !defined(CONFIG_USER_ONLY)
+ ptimer_set_limit(opaque, -limit, 0);
+#endif
+}
+#endif
projects / qemu / blobdiff