#endif
}
-void raise_exception(int tt)
+static void raise_exception(int tt)
{
env->exception_index = tt;
cpu_loop_exit();
}
+void HELPER(raise_exception)(int tt)
+{
+ raise_exception(tt);
+}
+
static inline void set_cwp(int new_cwp)
{
cpu_set_cwp(env, new_cwp);
s.l = (uint32_t)(*(uint64_t *)&DT0 & 0xffffffff);
d.d = DT1;
- d.VIS_L64(0) = s.VIS_W32(0) << 4;
- d.VIS_L64(1) = s.VIS_W32(1) << 4;
- d.VIS_L64(2) = s.VIS_W32(2) << 4;
- d.VIS_L64(3) = s.VIS_W32(3) << 4;
+ d.VIS_W64(0) = s.VIS_B32(0) << 4;
+ d.VIS_W64(1) = s.VIS_B32(1) << 4;
+ d.VIS_W64(2) = s.VIS_B32(2) << 4;
+ d.VIS_W64(3) = s.VIS_B32(3) << 4;
DT0 = d.d;
}
case 0x39: /* data cache diagnostic register */
ret = 0;
break;
+ case 0x38: /* SuperSPARC MMU Breakpoint Control Registers */
+ {
+ int reg = (addr >> 8) & 3;
+
+ switch(reg) {
+ case 0: /* Breakpoint Value (Addr) */
+ ret = env->mmubpregs[reg];
+ break;
+ case 1: /* Breakpoint Mask */
+ ret = env->mmubpregs[reg];
+ break;
+ case 2: /* Breakpoint Control */
+ ret = env->mmubpregs[reg];
+ break;
+ case 3: /* Breakpoint Status */
+ ret = env->mmubpregs[reg];
+ env->mmubpregs[reg] = 0ULL;
+ break;
+ }
+ DPRINTF_MMU("read breakpoint reg[%d] 0x%016llx\n", reg, ret);
+ }
+ break;
case 8: /* User code access, XXX */
default:
- do_unassigned_access(addr, 0, 0, asi);
+ do_unassigned_access(addr, 0, 0, asi, size);
ret = 0;
break;
}
// descriptor diagnostic
case 0x36: /* I-cache flash clear */
case 0x37: /* D-cache flash clear */
- case 0x38: /* breakpoint diagnostics */
case 0x4c: /* breakpoint action */
break;
+ case 0x38: /* SuperSPARC MMU Breakpoint Control Registers*/
+ {
+ int reg = (addr >> 8) & 3;
+
+ switch(reg) {
+ case 0: /* Breakpoint Value (Addr) */
+ env->mmubpregs[reg] = (val & 0xfffffffffULL);
+ break;
+ case 1: /* Breakpoint Mask */
+ env->mmubpregs[reg] = (val & 0xfffffffffULL);
+ break;
+ case 2: /* Breakpoint Control */
+ env->mmubpregs[reg] = (val & 0x7fULL);
+ break;
+ case 3: /* Breakpoint Status */
+ env->mmubpregs[reg] = (val & 0xfULL);
+ break;
+ }
+ DPRINTF_MMU("write breakpoint reg[%d] 0x%016llx\n", reg,
+ env->mmuregs[reg]);
+ }
+ break;
case 8: /* User code access, XXX */
case 9: /* Supervisor code access, XXX */
default:
- do_unassigned_access(addr, 1, 0, asi);
+ do_unassigned_access(addr, 1, 0, asi, size);
break;
}
#ifdef DEBUG_ASI
case 0x8a: // Primary no-fault LE, RO
case 0x8b: // Secondary no-fault LE, RO
default:
- do_unassigned_access(addr, 1, 0, 1);
+ do_unassigned_access(addr, 1, 0, 1, size);
return;
}
}
case 0x5f: // D-MMU demap, WO
case 0x77: // Interrupt vector, WO
default:
- do_unassigned_access(addr, 0, 0, 1);
+ do_unassigned_access(addr, 0, 0, 1, size);
ret = 0;
break;
}
case 0x8a: // Primary no-fault LE, RO
case 0x8b: // Secondary no-fault LE, RO
default:
- do_unassigned_access(addr, 1, 0, 1);
+ do_unassigned_access(addr, 1, 0, 1, size);
return;
}
}
name = "Unknown";
}
- fprintf(logfile, "%6d: %s (v=%04x) pc=%016" PRIx64 " npc=%016" PRIx64
+ qemu_log("%6d: %s (v=%04x) pc=%016" PRIx64 " npc=%016" PRIx64
" SP=%016" PRIx64 "\n",
count, name, intno,
env->pc,
env->npc, env->regwptr[6]);
- cpu_dump_state(env, logfile, fprintf, 0);
+ log_cpu_state(env, 0);
#if 0
{
int i;
uint8_t *ptr;
- fprintf(logfile, " code=");
+ qemu_log(" code=");
ptr = (uint8_t *)env->pc;
for(i = 0; i < 16; i++) {
- fprintf(logfile, " %02x", ldub(ptr + i));
+ qemu_log(" %02x", ldub(ptr + i));
}
- fprintf(logfile, "\n");
+ qemu_log("\n");
}
#endif
count++;
name = "Unknown";
}
- fprintf(logfile, "%6d: %s (v=%02x) pc=%08x npc=%08x SP=%08x\n",
+ qemu_log("%6d: %s (v=%02x) pc=%08x npc=%08x SP=%08x\n",
count, name, intno,
env->pc,
env->npc, env->regwptr[6]);
- cpu_dump_state(env, logfile, fprintf, 0);
+ log_cpu_state(env, 0);
#if 0
{
int i;
uint8_t *ptr;
- fprintf(logfile, " code=");
+ qemu_log(" code=");
ptr = (uint8_t *)env->pc;
for(i = 0; i < 16; i++) {
- fprintf(logfile, " %02x", ldub(ptr + i));
+ qemu_log(" %02x", ldub(ptr + i));
}
- fprintf(logfile, "\n");
+ qemu_log("\n");
}
#endif
count++;
#ifndef TARGET_SPARC64
void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
- int is_asi)
+ int is_asi, int size)
{
CPUState *saved_env;
env = cpu_single_env;
#ifdef DEBUG_UNASSIGNED
if (is_asi)
- printf("Unassigned mem %s access to " TARGET_FMT_plx
+ printf("Unassigned mem %s access of %d byte%s to " TARGET_FMT_plx
" asi 0x%02x from " TARGET_FMT_lx "\n",
- is_exec ? "exec" : is_write ? "write" : "read", addr, is_asi,
- env->pc);
+ is_exec ? "exec" : is_write ? "write" : "read", size,
+ size == 1 ? "" : "s", addr, is_asi, env->pc);
else
- printf("Unassigned mem %s access to " TARGET_FMT_plx " from "
- TARGET_FMT_lx "\n",
- is_exec ? "exec" : is_write ? "write" : "read", addr, env->pc);
+ printf("Unassigned mem %s access of %d byte%s to " TARGET_FMT_plx
+ " from " TARGET_FMT_lx "\n",
+ is_exec ? "exec" : is_write ? "write" : "read", size,
+ size == 1 ? "" : "s", addr, env->pc);
#endif
if (env->mmuregs[3]) /* Fault status register */
env->mmuregs[3] = 1; /* overflow (not read before another fault) */
}
#else
void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
- int is_asi)
+ int is_asi, int size)
{
#ifdef DEBUG_UNASSIGNED
CPUState *saved_env;
}
#endif
+#ifdef TARGET_SPARC64
+void helper_tick_set_count(void *opaque, uint64_t count)
+{
+#if !defined(CONFIG_USER_ONLY)
+ cpu_tick_set_count(opaque, count);
+#endif
+}
+
+uint64_t helper_tick_get_count(void *opaque)
+{
+#if !defined(CONFIG_USER_ONLY)
+ return cpu_tick_get_count(opaque);
+#else
+ return 0;
+#endif
+}
+
+void helper_tick_set_limit(void *opaque, uint64_t limit)
+{
+#if !defined(CONFIG_USER_ONLY)
+ cpu_tick_set_limit(opaque, limit);
+#endif
+}
+#endif
projects / qemu / blobdiff