//#define DEBUG_UNALIGNED
//#define DEBUG_UNASSIGNED
//#define DEBUG_ASI
+//#define DEBUG_PCALL
#ifdef DEBUG_MMU
#define DPRINTF_MMU(fmt, args...) \
#endif
}
-void raise_exception(int tt)
+static void raise_exception(int tt)
{
env->exception_index = tt;
cpu_loop_exit();
}
-void helper_trap(target_ulong nb_trap)
+void HELPER(raise_exception)(int tt)
{
- env->exception_index = TT_TRAP + (nb_trap & 0x7f);
- cpu_loop_exit();
-}
-
-void helper_trapcc(target_ulong nb_trap, target_ulong do_trap)
-{
- if (do_trap) {
- env->exception_index = TT_TRAP + (nb_trap & 0x7f);
- cpu_loop_exit();
- }
+ raise_exception(tt);
}
static inline void set_cwp(int new_cwp)
#define F_HELPER(name, p) void helper_f##name##p(void)
#define F_BINOP(name) \
- F_HELPER(name, s) \
+ float32 helper_f ## name ## s (float32 src1, float32 src2) \
{ \
- FT0 = float32_ ## name (FT0, FT1, &env->fp_status); \
+ return float32_ ## name (src1, src2, &env->fp_status); \
} \
F_HELPER(name, d) \
{ \
F_BINOP(div);
#undef F_BINOP
-void helper_fsmuld(void)
+void helper_fsmuld(float32 src1, float32 src2)
{
- DT0 = float64_mul(float32_to_float64(FT0, &env->fp_status),
- float32_to_float64(FT1, &env->fp_status),
+ DT0 = float64_mul(float32_to_float64(src1, &env->fp_status),
+ float32_to_float64(src2, &env->fp_status),
&env->fp_status);
}
&env->fp_status);
}
-F_HELPER(neg, s)
+float32 helper_fnegs(float32 src)
{
- FT0 = float32_chs(FT1);
+ return float32_chs(src);
}
#ifdef TARGET_SPARC64
#endif
/* Integer to float conversion. */
-F_HELPER(ito, s)
+float32 helper_fitos(int32_t src)
{
- FT0 = int32_to_float32(*((int32_t *)&FT1), &env->fp_status);
+ return int32_to_float32(src, &env->fp_status);
}
-F_HELPER(ito, d)
+void helper_fitod(int32_t src)
{
- DT0 = int32_to_float64(*((int32_t *)&FT1), &env->fp_status);
+ DT0 = int32_to_float64(src, &env->fp_status);
}
-F_HELPER(ito, q)
+void helper_fitoq(int32_t src)
{
- QT0 = int32_to_float128(*((int32_t *)&FT1), &env->fp_status);
+ QT0 = int32_to_float128(src, &env->fp_status);
}
#ifdef TARGET_SPARC64
-F_HELPER(xto, s)
+float32 helper_fxtos(void)
{
- FT0 = int64_to_float32(*((int64_t *)&DT1), &env->fp_status);
+ return int64_to_float32(*((int64_t *)&DT1), &env->fp_status);
}
F_HELPER(xto, d)
#undef F_HELPER
/* floating point conversion */
-void helper_fdtos(void)
+float32 helper_fdtos(void)
{
- FT0 = float64_to_float32(DT1, &env->fp_status);
+ return float64_to_float32(DT1, &env->fp_status);
}
-void helper_fstod(void)
+void helper_fstod(float32 src)
{
- DT0 = float32_to_float64(FT1, &env->fp_status);
+ DT0 = float32_to_float64(src, &env->fp_status);
}
-void helper_fqtos(void)
+float32 helper_fqtos(void)
{
- FT0 = float128_to_float32(QT1, &env->fp_status);
+ return float128_to_float32(QT1, &env->fp_status);
}
-void helper_fstoq(void)
+void helper_fstoq(float32 src)
{
- QT0 = float32_to_float128(FT1, &env->fp_status);
+ QT0 = float32_to_float128(src, &env->fp_status);
}
void helper_fqtod(void)
}
/* Float to integer conversion. */
-void helper_fstoi(void)
+int32_t helper_fstoi(float32 src)
{
- *((int32_t *)&FT0) = float32_to_int32_round_to_zero(FT1, &env->fp_status);
+ return float32_to_int32_round_to_zero(src, &env->fp_status);
}
-void helper_fdtoi(void)
+int32_t helper_fdtoi(void)
{
- *((int32_t *)&FT0) = float64_to_int32_round_to_zero(DT1, &env->fp_status);
+ return float64_to_int32_round_to_zero(DT1, &env->fp_status);
}
-void helper_fqtoi(void)
+int32_t helper_fqtoi(void)
{
- *((int32_t *)&FT0) = float128_to_int32_round_to_zero(QT1, &env->fp_status);
+ return float128_to_int32_round_to_zero(QT1, &env->fp_status);
}
#ifdef TARGET_SPARC64
-void helper_fstox(void)
+void helper_fstox(float32 src)
{
- *((int64_t *)&DT0) = float32_to_int64_round_to_zero(FT1, &env->fp_status);
+ *((int64_t *)&DT0) = float32_to_int64_round_to_zero(src, &env->fp_status);
}
void helper_fdtox(void)
*((uint64_t *)&DT0) = tmp;
}
-void helper_movl_FT0_0(void)
-{
- *((uint32_t *)&FT0) = 0;
-}
-
-void helper_movl_DT0_0(void)
-{
- *((uint64_t *)&DT0) = 0;
-}
-
-void helper_movl_FT0_1(void)
-{
- *((uint32_t *)&FT0) = 0xffffffff;
-}
-
-void helper_movl_DT0_1(void)
-{
- *((uint64_t *)&DT0) = 0xffffffffffffffffULL;
-}
-
-void helper_fnot(void)
-{
- *(uint64_t *)&DT0 = ~*(uint64_t *)&DT1;
-}
-
-void helper_fnots(void)
-{
- *(uint32_t *)&FT0 = ~*(uint32_t *)&FT1;
-}
-
-void helper_fnor(void)
-{
- *(uint64_t *)&DT0 = ~(*(uint64_t *)&DT0 | *(uint64_t *)&DT1);
-}
-
-void helper_fnors(void)
-{
- *(uint32_t *)&FT0 = ~(*(uint32_t *)&FT0 | *(uint32_t *)&FT1);
-}
-
-void helper_for(void)
-{
- *(uint64_t *)&DT0 |= *(uint64_t *)&DT1;
-}
-
-void helper_fors(void)
-{
- *(uint32_t *)&FT0 |= *(uint32_t *)&FT1;
-}
-
-void helper_fxor(void)
-{
- *(uint64_t *)&DT0 ^= *(uint64_t *)&DT1;
-}
-
-void helper_fxors(void)
-{
- *(uint32_t *)&FT0 ^= *(uint32_t *)&FT1;
-}
-
-void helper_fand(void)
-{
- *(uint64_t *)&DT0 &= *(uint64_t *)&DT1;
-}
-
-void helper_fands(void)
-{
- *(uint32_t *)&FT0 &= *(uint32_t *)&FT1;
-}
-
-void helper_fornot(void)
-{
- *(uint64_t *)&DT0 = *(uint64_t *)&DT0 | ~*(uint64_t *)&DT1;
-}
-
-void helper_fornots(void)
-{
- *(uint32_t *)&FT0 = *(uint32_t *)&FT0 | ~*(uint32_t *)&FT1;
-}
-
-void helper_fandnot(void)
-{
- *(uint64_t *)&DT0 = *(uint64_t *)&DT0 & ~*(uint64_t *)&DT1;
-}
-
-void helper_fandnots(void)
-{
- *(uint32_t *)&FT0 = *(uint32_t *)&FT0 & ~*(uint32_t *)&FT1;
-}
-
-void helper_fnand(void)
-{
- *(uint64_t *)&DT0 = ~(*(uint64_t *)&DT0 & *(uint64_t *)&DT1);
-}
-
-void helper_fnands(void)
-{
- *(uint32_t *)&FT0 = ~(*(uint32_t *)&FT0 & *(uint32_t *)&FT1);
-}
-
-void helper_fxnor(void)
-{
- *(uint64_t *)&DT0 ^= ~*(uint64_t *)&DT1;
-}
-
-void helper_fxnors(void)
-{
- *(uint32_t *)&FT0 ^= ~*(uint32_t *)&FT1;
-}
-
#ifdef WORDS_BIGENDIAN
#define VIS_B64(n) b[7 - (n)]
#define VIS_W64(n) w[3 - (n)]
s.l = (uint32_t)(*(uint64_t *)&DT0 & 0xffffffff);
d.d = DT1;
- d.VIS_L64(0) = s.VIS_W32(0) << 4;
- d.VIS_L64(1) = s.VIS_W32(1) << 4;
- d.VIS_L64(2) = s.VIS_W32(2) << 4;
- d.VIS_L64(3) = s.VIS_W32(3) << 4;
+ d.VIS_W64(0) = s.VIS_B32(0) << 4;
+ d.VIS_W64(1) = s.VIS_B32(1) << 4;
+ d.VIS_W64(2) = s.VIS_B32(2) << 4;
+ d.VIS_W64(3) = s.VIS_B32(3) << 4;
DT0 = d.d;
}
DT0 = d.d; \
} \
\
- void name##16s(void) \
+ uint32_t name##16s(uint32_t src1, uint32_t src2) \
{ \
vis32 s, d; \
\
- s.f = FT0; \
- d.f = FT1; \
+ s.l = src1; \
+ d.l = src2; \
\
d.VIS_W32(0) = F(d.VIS_W32(0), s.VIS_W32(0)); \
d.VIS_W32(1) = F(d.VIS_W32(1), s.VIS_W32(1)); \
\
- FT0 = d.f; \
+ return d.l; \
} \
\
void name##32(void) \
DT0 = d.d; \
} \
\
- void name##32s(void) \
+ uint32_t name##32s(uint32_t src1, uint32_t src2) \
{ \
vis32 s, d; \
\
- s.f = FT0; \
- d.f = FT1; \
+ s.l = src1; \
+ d.l = src2; \
\
d.l = F(d.l, s.l); \
\
- FT0 = d.f; \
+ return d.l; \
}
#define FADD(a, b) ((a) + (b))
set_float_exception_flags(0, &env->fp_status);
}
-void helper_fabss(void)
+float32 helper_fabss(float32 src)
{
- FT0 = float32_abs(FT1);
+ return float32_abs(src);
}
#ifdef TARGET_SPARC64
}
#endif
-void helper_fsqrts(void)
+float32 helper_fsqrts(float32 src)
{
- FT0 = float32_sqrt(FT1, &env->fp_status);
+ return float32_sqrt(src, &env->fp_status);
}
void helper_fsqrtd(void)
} \
env->fsr |= new_fsr; \
}
+#define GEN_FCMPS(name, size, FS, TRAP) \
+ void glue(helper_, name)(float32 src1, float32 src2) \
+ { \
+ target_ulong new_fsr; \
+ \
+ env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
+ switch (glue(size, _compare) (src1, src2, &env->fp_status)) { \
+ case float_relation_unordered: \
+ new_fsr = (FSR_FCC1 | FSR_FCC0) << FS; \
+ if ((env->fsr & FSR_NVM) || TRAP) { \
+ env->fsr |= new_fsr; \
+ env->fsr |= FSR_NVC; \
+ env->fsr |= FSR_FTT_IEEE_EXCP; \
+ raise_exception(TT_FP_EXCP); \
+ } else { \
+ env->fsr |= FSR_NVA; \
+ } \
+ break; \
+ case float_relation_less: \
+ new_fsr = FSR_FCC0 << FS; \
+ break; \
+ case float_relation_greater: \
+ new_fsr = FSR_FCC1 << FS; \
+ break; \
+ default: \
+ new_fsr = 0; \
+ break; \
+ } \
+ env->fsr |= new_fsr; \
+ }
-GEN_FCMP(fcmps, float32, FT0, FT1, 0, 0);
+GEN_FCMPS(fcmps, float32, 0, 0);
GEN_FCMP(fcmpd, float64, DT0, DT1, 0, 0);
-GEN_FCMP(fcmpes, float32, FT0, FT1, 0, 1);
+GEN_FCMPS(fcmpes, float32, 0, 1);
GEN_FCMP(fcmped, float64, DT0, DT1, 0, 1);
GEN_FCMP(fcmpq, float128, QT0, QT1, 0, 0);
GEN_FCMP(fcmpeq, float128, QT0, QT1, 0, 1);
#ifdef TARGET_SPARC64
-GEN_FCMP(fcmps_fcc1, float32, FT0, FT1, 22, 0);
+GEN_FCMPS(fcmps_fcc1, float32, 22, 0);
GEN_FCMP(fcmpd_fcc1, float64, DT0, DT1, 22, 0);
GEN_FCMP(fcmpq_fcc1, float128, QT0, QT1, 22, 0);
-GEN_FCMP(fcmps_fcc2, float32, FT0, FT1, 24, 0);
+GEN_FCMPS(fcmps_fcc2, float32, 24, 0);
GEN_FCMP(fcmpd_fcc2, float64, DT0, DT1, 24, 0);
GEN_FCMP(fcmpq_fcc2, float128, QT0, QT1, 24, 0);
-GEN_FCMP(fcmps_fcc3, float32, FT0, FT1, 26, 0);
+GEN_FCMPS(fcmps_fcc3, float32, 26, 0);
GEN_FCMP(fcmpd_fcc3, float64, DT0, DT1, 26, 0);
GEN_FCMP(fcmpq_fcc3, float128, QT0, QT1, 26, 0);
-GEN_FCMP(fcmpes_fcc1, float32, FT0, FT1, 22, 1);
+GEN_FCMPS(fcmpes_fcc1, float32, 22, 1);
GEN_FCMP(fcmped_fcc1, float64, DT0, DT1, 22, 1);
GEN_FCMP(fcmpeq_fcc1, float128, QT0, QT1, 22, 1);
-GEN_FCMP(fcmpes_fcc2, float32, FT0, FT1, 24, 1);
+GEN_FCMPS(fcmpes_fcc2, float32, 24, 1);
GEN_FCMP(fcmped_fcc2, float64, DT0, DT1, 24, 1);
GEN_FCMP(fcmpeq_fcc2, float128, QT0, QT1, 24, 1);
-GEN_FCMP(fcmpes_fcc3, float32, FT0, FT1, 26, 1);
+GEN_FCMPS(fcmpes_fcc3, float32, 26, 1);
GEN_FCMP(fcmped_fcc3, float64, DT0, DT1, 26, 1);
GEN_FCMP(fcmpeq_fcc3, float128, QT0, QT1, 26, 1);
#endif
+#undef GEN_FCMPS
#if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) && \
defined(DEBUG_MXCC)
break;
}
DPRINTF_MXCC("asi = %d, size = %d, sign = %d, "
- "addr = %08x -> ret = %08x,"
+ "addr = %08x -> ret = %" PRIx64 ","
"addr = %08x\n", asi, size, sign, last_addr, ret, addr);
#ifdef DEBUG_MXCC
dump_mxcc(env);
case 0x39: /* data cache diagnostic register */
ret = 0;
break;
+ case 0x38: /* SuperSPARC MMU Breakpoint Control Registers */
+ {
+ int reg = (addr >> 8) & 3;
+
+ switch(reg) {
+ case 0: /* Breakpoint Value (Addr) */
+ ret = env->mmubpregs[reg];
+ break;
+ case 1: /* Breakpoint Mask */
+ ret = env->mmubpregs[reg];
+ break;
+ case 2: /* Breakpoint Control */
+ ret = env->mmubpregs[reg];
+ break;
+ case 3: /* Breakpoint Status */
+ ret = env->mmubpregs[reg];
+ env->mmubpregs[reg] = 0ULL;
+ break;
+ }
+ DPRINTF_MMU("read breakpoint reg[%d] 0x%016llx\n", reg, ret);
+ }
+ break;
case 8: /* User code access, XXX */
default:
- do_unassigned_access(addr, 0, 0, asi);
+ do_unassigned_access(addr, 0, 0, asi, size);
ret = 0;
break;
}
break;
case 0x01c00a04: /* MXCC control register */
if (size == 4)
- env->mxccregs[3] = (env->mxccregs[0xa] & 0xffffffff00000000ULL)
+ env->mxccregs[3] = (env->mxccregs[3] & 0xffffffff00000000ULL)
| val;
else
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
size);
break;
}
- DPRINTF_MXCC("asi = %d, size = %d, addr = %08x, val = %08x\n", asi,
- size, addr, val);
+ DPRINTF_MXCC("asi = %d, size = %d, addr = %08x, val = %" PRIx64 "\n",
+ asi, size, addr, val);
#ifdef DEBUG_MXCC
dump_mxcc(env);
#endif
// descriptor diagnostic
case 0x36: /* I-cache flash clear */
case 0x37: /* D-cache flash clear */
- case 0x38: /* breakpoint diagnostics */
case 0x4c: /* breakpoint action */
break;
+ case 0x38: /* SuperSPARC MMU Breakpoint Control Registers*/
+ {
+ int reg = (addr >> 8) & 3;
+
+ switch(reg) {
+ case 0: /* Breakpoint Value (Addr) */
+ env->mmubpregs[reg] = (val & 0xfffffffffULL);
+ break;
+ case 1: /* Breakpoint Mask */
+ env->mmubpregs[reg] = (val & 0xfffffffffULL);
+ break;
+ case 2: /* Breakpoint Control */
+ env->mmubpregs[reg] = (val & 0x7fULL);
+ break;
+ case 3: /* Breakpoint Status */
+ env->mmubpregs[reg] = (val & 0xfULL);
+ break;
+ }
+ DPRINTF_MMU("write breakpoint reg[%d] 0x%016llx\n", reg,
+ env->mmuregs[reg]);
+ }
+ break;
case 8: /* User code access, XXX */
case 9: /* Supervisor code access, XXX */
default:
- do_unassigned_access(addr, 1, 0, asi);
+ do_unassigned_access(addr, 1, 0, asi, size);
break;
}
#ifdef DEBUG_ASI
address_mask(env, &addr);
switch (asi) {
- case 0x80: // Primary
case 0x82: // Primary no-fault
- case 0x88: // Primary LE
case 0x8a: // Primary no-fault LE
+ if (page_check_range(addr, size, PAGE_READ) == -1) {
+#ifdef DEBUG_ASI
+ dump_asi("read ", last_addr, asi, size, ret);
+#endif
+ return 0;
+ }
+ // Fall through
+ case 0x80: // Primary
+ case 0x88: // Primary LE
{
switch(size) {
case 1:
}
}
break;
- case 0x81: // Secondary
case 0x83: // Secondary no-fault
- case 0x89: // Secondary LE
case 0x8b: // Secondary no-fault LE
+ if (page_check_range(addr, size, PAGE_READ) == -1) {
+#ifdef DEBUG_ASI
+ dump_asi("read ", last_addr, asi, size, ret);
+#endif
+ return 0;
+ }
+ // Fall through
+ case 0x81: // Secondary
+ case 0x89: // Secondary LE
// XXX
break;
default:
case 0x8a: // Primary no-fault LE, RO
case 0x8b: // Secondary no-fault LE, RO
default:
- do_unassigned_access(addr, 1, 0, 1);
+ do_unassigned_access(addr, 1, 0, 1, size);
return;
}
}
helper_check_align(addr, size - 1);
switch (asi) {
+ case 0x82: // Primary no-fault
+ case 0x8a: // Primary no-fault LE
+ if (cpu_get_phys_page_debug(env, addr) == -1ULL) {
+#ifdef DEBUG_ASI
+ dump_asi("read ", last_addr, asi, size, ret);
+#endif
+ return 0;
+ }
+ // Fall through
case 0x10: // As if user primary
case 0x18: // As if user primary LE
case 0x80: // Primary
- case 0x82: // Primary no-fault
case 0x88: // Primary LE
- case 0x8a: // Primary no-fault LE
+ case 0xe2: // UA2007 Primary block init
+ case 0xe3: // UA2007 Secondary block init
if ((asi & 0x80) && (env->pstate & PS_PRIV)) {
if ((env->def->features & CPU_FEATURE_HYPV)
&& env->hpstate & HS_PRIV) {
// Only ldda allowed
raise_exception(TT_ILL_INSN);
return 0;
+ case 0x83: // Secondary no-fault
+ case 0x8b: // Secondary no-fault LE
+ if (cpu_get_phys_page_debug(env, addr) == -1ULL) {
+#ifdef DEBUG_ASI
+ dump_asi("read ", last_addr, asi, size, ret);
+#endif
+ return 0;
+ }
+ // Fall through
case 0x04: // Nucleus
case 0x0c: // Nucleus Little Endian (LE)
case 0x11: // As if user secondary
case 0x19: // As if user secondary LE
case 0x4a: // UPA config
case 0x81: // Secondary
- case 0x83: // Secondary no-fault
case 0x89: // Secondary LE
- case 0x8b: // Secondary no-fault LE
// XXX
break;
case 0x45: // LSU
case 0x5f: // D-MMU demap, WO
case 0x77: // Interrupt vector, WO
default:
- do_unassigned_access(addr, 0, 0, 1);
+ do_unassigned_access(addr, 0, 0, 1, size);
ret = 0;
break;
}
case 0x18: // As if user primary LE
case 0x80: // Primary
case 0x88: // Primary LE
+ case 0xe2: // UA2007 Primary block init
+ case 0xe3: // UA2007 Secondary block init
if ((asi & 0x80) && (env->pstate & PS_PRIV)) {
if ((env->def->features & CPU_FEATURE_HYPV)
&& env->hpstate & HS_PRIV) {
}
case 0x55: // I-MMU data access
{
+ // TODO: auto demap
+
unsigned int i = (addr >> 3) & 0x3f;
env->itlb_tag[i] = env->immuregs[6];
return;
}
case 0x57: // I-MMU demap
- // XXX
+ {
+ unsigned int i;
+
+ for (i = 0; i < 64; i++) {
+ if ((env->itlb_tte[i] & 0x8000000000000000ULL) != 0) {
+ target_ulong mask = 0xffffffffffffe000ULL;
+
+ mask <<= 3 * ((env->itlb_tte[i] >> 61) & 3);
+ if ((val & mask) == (env->itlb_tag[i] & mask)) {
+ env->itlb_tag[i] = 0;
+ env->itlb_tte[i] = 0;
+ }
+ return;
+ }
+ }
+ }
return;
case 0x58: // D-MMU regs
{
return;
}
case 0x5f: // D-MMU demap
+ {
+ unsigned int i;
+
+ for (i = 0; i < 64; i++) {
+ if ((env->dtlb_tte[i] & 0x8000000000000000ULL) != 0) {
+ target_ulong mask = 0xffffffffffffe000ULL;
+
+ mask <<= 3 * ((env->dtlb_tte[i] >> 61) & 3);
+ if ((val & mask) == (env->dtlb_tag[i] & mask)) {
+ env->dtlb_tag[i] = 0;
+ env->dtlb_tte[i] = 0;
+ }
+ return;
+ }
+ }
+ }
+ return;
case 0x49: // Interrupt data receive
// XXX
return;
case 0x8a: // Primary no-fault LE, RO
case 0x8b: // Secondary no-fault LE, RO
default:
- do_unassigned_access(addr, 1, 0, 1);
+ do_unassigned_access(addr, 1, 0, 1, size);
return;
}
}
switch(size) {
default:
case 4:
- *((uint32_t *)&FT0) = val;
+ *((uint32_t *)&env->fpr[rd]) = val;
break;
case 8:
*((int64_t *)&DT0) = val;
helper_check_align(addr, 3);
switch (asi) {
+ case 0xe0: // UA2007 Block commit store primary (cache flush)
+ case 0xe1: // UA2007 Block commit store secondary (cache flush)
case 0xf0: // Block store primary
case 0xf1: // Block store secondary
case 0xf8: // Block store primary LE
switch(size) {
default:
case 4:
- val = *((uint32_t *)&FT0);
+ val = *((uint32_t *)&env->fpr[rd]);
break;
case 8:
val = *((int64_t *)&DT0);
{
target_ulong ret;
- val1 &= 0xffffffffUL;
+ val2 &= 0xffffffffUL;
ret = helper_ld_asi(addr, asi, 4, 0);
ret &= 0xffffffffUL;
- if (val1 == ret)
- helper_st_asi(addr, val2 & 0xffffffffUL, asi, 4);
+ if (val2 == ret)
+ helper_st_asi(addr, val1 & 0xffffffffUL, asi, 4);
return ret;
}
target_ulong ret;
ret = helper_ld_asi(addr, asi, 8, 0);
- if (val1 == ret)
- helper_st_asi(addr, val2, asi, 8);
+ if (val2 == ret)
+ helper_st_asi(addr, val1, asi, 8);
return ret;
}
#endif /* TARGET_SPARC64 */
}
}
-uint64_t helper_pack64(target_ulong high, target_ulong low)
-{
- return ((uint64_t)high << 32) | (uint64_t)(low & 0xffffffff);
-}
-
void helper_stdf(target_ulong addr, int mem_idx)
{
helper_check_align(addr, 7);
#endif
}
-void helper_ldfsr(void)
+static inline void set_fsr(void)
{
int rnd_mode;
- PUT_FSR32(env, *((uint32_t *) &FT0));
switch (env->fsr & FSR_RD_MASK) {
case FSR_RD_NEAREST:
rnd_mode = float_round_nearest_even;
set_float_rounding_mode(rnd_mode, &env->fp_status);
}
-void helper_stfsr(void)
+void helper_ldfsr(uint32_t new_fsr)
{
- *((uint32_t *) &FT0) = GET_FSR32(env);
+ env->fsr = (new_fsr & FSR_LDFSR_MASK) | (env->fsr & FSR_LDFSR_OLDMASK);
+ set_fsr();
}
+#ifdef TARGET_SPARC64
+void helper_ldxfsr(uint64_t new_fsr)
+{
+ env->fsr = (new_fsr & FSR_LDXFSR_MASK) | (env->fsr & FSR_LDXFSR_OLDMASK);
+ set_fsr();
+}
+#endif
+
void helper_debug(void)
{
env->exception_index = EXCP_DEBUG;
env->tl--;
env->tsptr = &env->ts[env->tl & MAXTL_MASK];
}
+
+void helper_set_softint(uint64_t value)
+{
+ env->softint |= (uint32_t)value;
+}
+
+void helper_clear_softint(uint64_t value)
+{
+ env->softint &= (uint32_t)~value;
+}
+
+void helper_write_softint(uint64_t value)
+{
+ env->softint = (uint32_t)value;
+}
#endif
void helper_flush(target_ulong addr)
name = "Unknown";
}
- fprintf(logfile, "%6d: %s (v=%04x) pc=%016" PRIx64 " npc=%016" PRIx64
+ qemu_log("%6d: %s (v=%04x) pc=%016" PRIx64 " npc=%016" PRIx64
" SP=%016" PRIx64 "\n",
count, name, intno,
env->pc,
env->npc, env->regwptr[6]);
- cpu_dump_state(env, logfile, fprintf, 0);
+ log_cpu_state(env, 0);
#if 0
{
int i;
uint8_t *ptr;
- fprintf(logfile, " code=");
+ qemu_log(" code=");
ptr = (uint8_t *)env->pc;
for(i = 0; i < 16; i++) {
- fprintf(logfile, " %02x", ldub(ptr + i));
+ qemu_log(" %02x", ldub(ptr + i));
}
- fprintf(logfile, "\n");
+ qemu_log("\n");
}
#endif
count++;
name = "Unknown";
}
- fprintf(logfile, "%6d: %s (v=%02x) pc=%08x npc=%08x SP=%08x\n",
+ qemu_log("%6d: %s (v=%02x) pc=%08x npc=%08x SP=%08x\n",
count, name, intno,
env->pc,
env->npc, env->regwptr[6]);
- cpu_dump_state(env, logfile, fprintf, 0);
+ log_cpu_state(env, 0);
#if 0
{
int i;
uint8_t *ptr;
- fprintf(logfile, " code=");
+ qemu_log(" code=");
ptr = (uint8_t *)env->pc;
for(i = 0; i < 16; i++) {
- fprintf(logfile, " %02x", ldub(ptr + i));
+ qemu_log(" %02x", ldub(ptr + i));
}
- fprintf(logfile, "\n");
+ qemu_log("\n");
}
#endif
count++;
#ifndef TARGET_SPARC64
void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
- int is_asi)
+ int is_asi, int size)
{
CPUState *saved_env;
env = cpu_single_env;
#ifdef DEBUG_UNASSIGNED
if (is_asi)
- printf("Unassigned mem %s access to " TARGET_FMT_plx
+ printf("Unassigned mem %s access of %d byte%s to " TARGET_FMT_plx
" asi 0x%02x from " TARGET_FMT_lx "\n",
- is_exec ? "exec" : is_write ? "write" : "read", addr, is_asi,
- env->pc);
+ is_exec ? "exec" : is_write ? "write" : "read", size,
+ size == 1 ? "" : "s", addr, is_asi, env->pc);
else
- printf("Unassigned mem %s access to " TARGET_FMT_plx " from "
- TARGET_FMT_lx "\n",
- is_exec ? "exec" : is_write ? "write" : "read", addr, env->pc);
+ printf("Unassigned mem %s access of %d byte%s to " TARGET_FMT_plx
+ " from " TARGET_FMT_lx "\n",
+ is_exec ? "exec" : is_write ? "write" : "read", size,
+ size == 1 ? "" : "s", addr, env->pc);
#endif
if (env->mmuregs[3]) /* Fault status register */
env->mmuregs[3] = 1; /* overflow (not read before another fault) */
}
#else
void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
- int is_asi)
+ int is_asi, int size)
{
#ifdef DEBUG_UNASSIGNED
CPUState *saved_env;
}
#endif
+#ifdef TARGET_SPARC64
+void helper_tick_set_count(void *opaque, uint64_t count)
+{
+#if !defined(CONFIG_USER_ONLY)
+ cpu_tick_set_count(opaque, count);
+#endif
+}
+
+uint64_t helper_tick_get_count(void *opaque)
+{
+#if !defined(CONFIG_USER_ONLY)
+ return cpu_tick_get_count(opaque);
+#else
+ return 0;
+#endif
+}
+
+void helper_tick_set_limit(void *opaque, uint64_t limit)
+{
+#if !defined(CONFIG_USER_ONLY)
+ cpu_tick_set_limit(opaque, limit);
+#endif
+}
+#endif
projects / qemu / blobdiff