#ifdef DEBUG_ASI
#define DPRINTF_ASI(fmt, args...) \
do { printf("ASI: " fmt , ##args); } while (0)
-#else
-#define DPRINTF_ASI(fmt, args...) do {} while (0)
#endif
#ifdef TARGET_SPARC64
#endif
#endif
+#if defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
+// Calculates TSB pointer value for fault page size 8k or 64k
+static uint64_t ultrasparc_tsb_pointer(uint64_t tsb_register,
+ uint64_t tag_access_register,
+ int page_size)
+{
+ uint64_t tsb_base = tsb_register & ~0x1fffULL;
+ int tsb_split = (env->dmmuregs[5] & 0x1000ULL) ? 1 : 0;
+ int tsb_size = env->dmmuregs[5] & 0xf;
+
+ // discard lower 13 bits which hold tag access context
+ uint64_t tag_access_va = tag_access_register & ~0x1fffULL;
+
+ // now reorder bits
+ uint64_t tsb_base_mask = ~0x1fffULL;
+ uint64_t va = tag_access_va;
+
+ // move va bits to correct position
+ if (page_size == 8*1024) {
+ va >>= 9;
+ } else if (page_size == 64*1024) {
+ va >>= 12;
+ }
+
+ if (tsb_size) {
+ tsb_base_mask <<= tsb_size;
+ }
+
+ // calculate tsb_base mask and adjust va if split is in use
+ if (tsb_split) {
+ if (page_size == 8*1024) {
+ va &= ~(1ULL << (13 + tsb_size));
+ } else if (page_size == 64*1024) {
+ va |= (1ULL << (13 + tsb_size));
+ }
+ tsb_base_mask <<= 1;
+ }
+
+ return ((tsb_base & tsb_base_mask) | (va & ~tsb_base_mask)) & ~0xfULL;
+}
+
+// Calculates tag target register value by reordering bits
+// in tag access register
+static uint64_t ultrasparc_tag_target(uint64_t tag_access_register)
+{
+ return ((tag_access_register & 0x1fff) << 48) | (tag_access_register >> 22);
+}
+
+#endif
+
static inline void address_mask(CPUState *env1, target_ulong *addr)
{
#ifdef TARGET_SPARC64
GEN_FCMP(fcmpq, float128, QT0, QT1, 0, 0);
GEN_FCMP(fcmpeq, float128, QT0, QT1, 0, 1);
+static uint32_t compute_all_flags(void)
+{
+ return env->psr & PSR_ICC;
+}
+
+static uint32_t compute_C_flags(void)
+{
+ return env->psr & PSR_CARRY;
+}
+
+#ifdef TARGET_SPARC64
+static uint32_t compute_all_flags_xcc(void)
+{
+ return env->xcc & PSR_ICC;
+}
+
+static uint32_t compute_C_flags_xcc(void)
+{
+ return env->xcc & PSR_CARRY;
+}
+
+#endif
+
+typedef struct CCTable {
+ uint32_t (*compute_all)(void); /* return all the flags */
+ uint32_t (*compute_c)(void); /* return the C flag */
+} CCTable;
+
+static const CCTable icc_table[CC_OP_NB] = {
+ /* CC_OP_DYNAMIC should never happen */
+ [CC_OP_FLAGS] = { compute_all_flags, compute_C_flags },
+};
+
+#ifdef TARGET_SPARC64
+static const CCTable xcc_table[CC_OP_NB] = {
+ /* CC_OP_DYNAMIC should never happen */
+ [CC_OP_FLAGS] = { compute_all_flags_xcc, compute_C_flags_xcc },
+};
+#endif
+
+void helper_compute_psr(void)
+{
+ uint32_t new_psr;
+
+ new_psr = icc_table[CC_OP].compute_all();
+ env->psr = new_psr;
+#ifdef TARGET_SPARC64
+ new_psr = xcc_table[CC_OP].compute_all();
+ env->xcc = new_psr;
+#endif
+ CC_OP = CC_OP_FLAGS;
+}
+
+uint32_t helper_compute_C_icc(void)
+{
+ uint32_t ret;
+
+ ret = icc_table[CC_OP].compute_c() >> PSR_CARRY_SHIFT;
+ return ret;
+}
+
#ifdef TARGET_SPARC64
GEN_FCMPS(fcmps_fcc1, float32, 22, 0);
GEN_FCMP(fcmpd_fcc1, float64, DT0, DT1, 22, 0);
case 0x39: /* data cache diagnostic register */
ret = 0;
break;
+ case 0x38: /* SuperSPARC MMU Breakpoint Control Registers */
+ {
+ int reg = (addr >> 8) & 3;
+
+ switch(reg) {
+ case 0: /* Breakpoint Value (Addr) */
+ ret = env->mmubpregs[reg];
+ break;
+ case 1: /* Breakpoint Mask */
+ ret = env->mmubpregs[reg];
+ break;
+ case 2: /* Breakpoint Control */
+ ret = env->mmubpregs[reg];
+ break;
+ case 3: /* Breakpoint Status */
+ ret = env->mmubpregs[reg];
+ env->mmubpregs[reg] = 0ULL;
+ break;
+ }
+ DPRINTF_MMU("read breakpoint reg[%d] 0x%016llx\n", reg, ret);
+ }
+ break;
case 8: /* User code access, XXX */
default:
do_unassigned_access(addr, 0, 0, asi, size);
// descriptor diagnostic
case 0x36: /* I-cache flash clear */
case 0x37: /* D-cache flash clear */
- case 0x38: /* breakpoint diagnostics */
case 0x4c: /* breakpoint action */
break;
+ case 0x38: /* SuperSPARC MMU Breakpoint Control Registers*/
+ {
+ int reg = (addr >> 8) & 3;
+
+ switch(reg) {
+ case 0: /* Breakpoint Value (Addr) */
+ env->mmubpregs[reg] = (val & 0xfffffffffULL);
+ break;
+ case 1: /* Breakpoint Mask */
+ env->mmubpregs[reg] = (val & 0xfffffffffULL);
+ break;
+ case 2: /* Breakpoint Control */
+ env->mmubpregs[reg] = (val & 0x7fULL);
+ break;
+ case 3: /* Breakpoint Status */
+ env->mmubpregs[reg] = (val & 0xfULL);
+ break;
+ }
+ DPRINTF_MMU("write breakpoint reg[%d] 0x%016llx\n", reg,
+ env->mmuregs[reg]);
+ }
+ break;
case 8: /* User code access, XXX */
case 9: /* Supervisor code access, XXX */
default:
{
int reg = (addr >> 3) & 0xf;
- ret = env->immuregs[reg];
+ if (reg == 0) {
+ // I-TSB Tag Target register
+ ret = ultrasparc_tag_target(env->immuregs[6]);
+ } else {
+ ret = env->immuregs[reg];
+ }
+
break;
}
case 0x51: // I-MMU 8k TSB pointer
+ {
+ // env->immuregs[5] holds I-MMU TSB register value
+ // env->immuregs[6] holds I-MMU Tag Access register value
+ ret = ultrasparc_tsb_pointer(env->immuregs[5], env->immuregs[6],
+ 8*1024);
+ break;
+ }
case 0x52: // I-MMU 64k TSB pointer
- // XXX
- break;
+ {
+ // env->immuregs[5] holds I-MMU TSB register value
+ // env->immuregs[6] holds I-MMU Tag Access register value
+ ret = ultrasparc_tsb_pointer(env->immuregs[5], env->immuregs[6],
+ 64*1024);
+ break;
+ }
case 0x55: // I-MMU data access
{
int reg = (addr >> 3) & 0x3f;
{
int reg = (addr >> 3) & 0xf;
- ret = env->dmmuregs[reg];
+ if (reg == 0) {
+ // D-TSB Tag Target register
+ ret = ultrasparc_tag_target(env->dmmuregs[6]);
+ } else {
+ ret = env->dmmuregs[reg];
+ }
+ break;
+ }
+ case 0x59: // D-MMU 8k TSB pointer
+ {
+ // env->dmmuregs[5] holds D-MMU TSB register value
+ // env->dmmuregs[6] holds D-MMU Tag Access register value
+ ret = ultrasparc_tsb_pointer(env->dmmuregs[5], env->dmmuregs[6],
+ 8*1024);
+ break;
+ }
+ case 0x5a: // D-MMU 64k TSB pointer
+ {
+ // env->dmmuregs[5] holds D-MMU TSB register value
+ // env->dmmuregs[6] holds D-MMU Tag Access register value
+ ret = ultrasparc_tsb_pointer(env->dmmuregs[5], env->dmmuregs[6],
+ 64*1024);
break;
}
case 0x5d: // D-MMU data access
case 0x76: // E-cache tag
case 0x7e: // E-cache tag
break;
- case 0x59: // D-MMU 8k TSB pointer
- case 0x5a: // D-MMU 64k TSB pointer
case 0x5b: // D-MMU data pointer
case 0x48: // Interrupt dispatch, RO
case 0x49: // Interrupt data receive
int intno = env->exception_index;
#ifdef DEBUG_PCALL
- if (loglevel & CPU_LOG_INT) {
+ if (qemu_loglevel_mask(CPU_LOG_INT)) {
static int count;
const char *name;
name = "Unknown";
}
- fprintf(logfile, "%6d: %s (v=%04x) pc=%016" PRIx64 " npc=%016" PRIx64
+ qemu_log("%6d: %s (v=%04x) pc=%016" PRIx64 " npc=%016" PRIx64
" SP=%016" PRIx64 "\n",
count, name, intno,
env->pc,
env->npc, env->regwptr[6]);
- cpu_dump_state(env, logfile, fprintf, 0);
+ log_cpu_state(env, 0);
#if 0
{
int i;
uint8_t *ptr;
- fprintf(logfile, " code=");
+ qemu_log(" code=");
ptr = (uint8_t *)env->pc;
for(i = 0; i < 16; i++) {
- fprintf(logfile, " %02x", ldub(ptr + i));
+ qemu_log(" %02x", ldub(ptr + i));
}
- fprintf(logfile, "\n");
+ qemu_log("\n");
}
#endif
count++;
int cwp, intno = env->exception_index;
#ifdef DEBUG_PCALL
- if (loglevel & CPU_LOG_INT) {
+ if (qemu_loglevel_mask(CPU_LOG_INT)) {
static int count;
const char *name;
name = "Unknown";
}
- fprintf(logfile, "%6d: %s (v=%02x) pc=%08x npc=%08x SP=%08x\n",
+ qemu_log("%6d: %s (v=%02x) pc=%08x npc=%08x SP=%08x\n",
count, name, intno,
env->pc,
env->npc, env->regwptr[6]);
- cpu_dump_state(env, logfile, fprintf, 0);
+ log_cpu_state(env, 0);
#if 0
{
int i;
uint8_t *ptr;
- fprintf(logfile, " code=");
+ qemu_log(" code=");
ptr = (uint8_t *)env->pc;
for(i = 0; i < 16; i++) {
- fprintf(logfile, " %02x", ldub(ptr + i));
+ qemu_log(" %02x", ldub(ptr + i));
}
- fprintf(logfile, "\n");
+ qemu_log("\n");
}
#endif
count++;
projects / qemu / blobdiff