Break up vl.h.

[qemu] / target-sparc / op_helper.c

diff --git a/target-sparc/op_helper.c b/target-sparc/op_helper.c
index 7b1b08e..699a305 100644 (file)
--- a/target-sparc/op_helper.c
+++ b/target-sparc/op_helper.c
@@ -1,4 +1,5 @@
 #include "exec.h"
+#include "host-utils.h"
 
 //#define DEBUG_PCALL
 //#define DEBUG_MMU
@@ -206,6 +207,14 @@ void helper_ld_asi(int asi, int size, int sign)
             else
                 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
             break;
+        case 0x01c00c00: /* Module reset register */
+            if (size == 8) {
+                ret = env->mxccregs[5] >> 32;
+                T0 = env->mxccregs[5];
+                // should we do something here?
+            } else
+                DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
+            break;
         case 0x01c00f00: /* MBus port address register */
             if (size == 8) {
                 ret = env->mxccregs[7];
@@ -262,7 +271,7 @@ void helper_ld_asi(int asi, int size, int sign)
         case 8:
             tmp = ldq_code(T0 & ~7);
             ret = tmp >> 32;
-            T0 = tmp & 0xffffffff;
+            T0 = tmp;
             break;
         }
         break;
@@ -281,7 +290,7 @@ void helper_ld_asi(int asi, int size, int sign)
         case 8:
             tmp = ldq_user(T0 & ~7);
             ret = tmp >> 32;
-            T0 = tmp & 0xffffffff;
+            T0 = tmp;
             break;
         }
         break;
@@ -300,7 +309,7 @@ void helper_ld_asi(int asi, int size, int sign)
         case 8:
             tmp = ldq_kernel(T0 & ~7);
             ret = tmp >> 32;
-            T0 = tmp & 0xffffffff;
+            T0 = tmp;
             break;
         }
         break;
@@ -324,7 +333,7 @@ void helper_ld_asi(int asi, int size, int sign)
         case 8:
             tmp = ldq_phys(T0 & ~7);
             ret = tmp >> 32;
-            T0 = tmp & 0xffffffff;
+            T0 = tmp;
             break;
         }
         break;
@@ -348,7 +357,7 @@ void helper_ld_asi(int asi, int size, int sign)
             tmp = ldq_phys((target_phys_addr_t)(T0 & ~7)
                            | ((target_phys_addr_t)(asi & 0xf) << 32));
             ret = tmp >> 32;
-            T0 = tmp & 0xffffffff;
+            T0 = tmp;
             break;
         }
         break;
@@ -432,18 +441,16 @@ void helper_st_asi(int asi, int size)
             break;
         case 0x01c00a04: /* MXCC control register */
             if (size == 4)
-                env->mxccregs[3] = (env->mxccregs[0xa] & 0xffffffff00000000) | T1;
+                env->mxccregs[3] = (env->mxccregs[0xa] & 0xffffffff00000000ULL) | T1;
             else
                 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
             break;
         case 0x01c00e00: /* MXCC error register  */
+            // writing a 1 bit clears the error
             if (size == 8)
-                env->mxccregs[6] = ((uint64_t)T1 << 32) | T2;
+                env->mxccregs[6] &= ~(((uint64_t)T1 << 32) | T2);
             else
                 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
-            if (env->mxccregs[6] == 0xffffffffffffffffULL) {
-                // this is probably a reset
-            }
             break;
         case 0x01c00f00: /* MBus port address register */
             if (size == 8)
@@ -492,8 +499,8 @@ void helper_st_asi(int asi, int size)
             oldreg = env->mmuregs[reg];
             switch(reg) {
             case 0:
-                env->mmuregs[reg] &= ~(MMU_E | MMU_NF | MMU_BM);
-                env->mmuregs[reg] |= T1 & (MMU_E | MMU_NF | MMU_BM);
+                env->mmuregs[reg] &= ~(MMU_E | MMU_NF | env->mmu_bm);
+                env->mmuregs[reg] |= T1 & (MMU_E | MMU_NF | env->mmu_bm);
                 // Mappings generated during no-fault mode or MMU
                 // disabled mode are invalid in normal mode
                 if (oldreg != env->mmuregs[reg])
@@ -1469,12 +1476,7 @@ void do_rdpsr()
 
 void do_popc()
 {
-    T0 = (T1 & 0x5555555555555555ULL) + ((T1 >> 1) & 0x5555555555555555ULL);
-    T0 = (T0 & 0x3333333333333333ULL) + ((T0 >> 2) & 0x3333333333333333ULL);
-    T0 = (T0 & 0x0f0f0f0f0f0f0f0fULL) + ((T0 >> 4) & 0x0f0f0f0f0f0f0f0fULL);
-    T0 = (T0 & 0x00ff00ff00ff00ffULL) + ((T0 >> 8) & 0x00ff00ff00ff00ffULL);
-    T0 = (T0 & 0x0000ffff0000ffffULL) + ((T0 >> 16) & 0x0000ffff0000ffffULL);
-    T0 = (T0 & 0x00000000ffffffffULL) + ((T0 >> 32) & 0x00000000ffffffffULL);
+    T0 = ctpop64(T1);
 }
 
 static inline uint64_t *get_gregset(uint64_t pstate)
@@ -1684,7 +1686,11 @@ static void do_unaligned_access(target_ulong addr, int is_write, int is_user,
 
 #define MMUSUFFIX _mmu
 #define ALIGNED_ONLY
-#define GETPC() (__builtin_return_address(0))
+#ifdef __s390__
+# define GETPC() ((void*)((unsigned long)__builtin_return_address(0) & 0x7fffffffUL))
+#else
+# define GETPC() (__builtin_return_address(0))
+#endif
 
 #define SHIFT 0
 #include "softmmu_template.h"
@@ -1798,27 +1804,3 @@ void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
 }
 #endif
 
-#ifdef TARGET_SPARC64
-void do_tick_set_count(void *opaque, uint64_t count)
-{
-#if !defined(CONFIG_USER_ONLY)
-    ptimer_set_count(opaque, -count);
-#endif
-}
-
-uint64_t do_tick_get_count(void *opaque)
-{
-#if !defined(CONFIG_USER_ONLY)
-    return -ptimer_get_count(opaque);
-#else
-    return 0;
-#endif
-}
-
-void do_tick_set_limit(void *opaque, uint64_t limit)
-{
-#if !defined(CONFIG_USER_ONLY)
-    ptimer_set_limit(opaque, -limit, 0);
-#endif
-}
-#endif