#endif
/* local register indexes (only used inside old micro ops) */
static TCGv cpu_tmp0, cpu_tmp32, cpu_tmp64;
+/* Floating point registers */
+static TCGv cpu_fpr[TARGET_FPREGS];
#include "gen-icount.h"
#define IS_IMM (insn & (1<<13))
/* floating point registers moves */
-static void gen_op_load_fpr_FT0(unsigned int src)
-{
- tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
- tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ft0));
-}
-
-static void gen_op_load_fpr_FT1(unsigned int src)
-{
- tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
- tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ft1));
-}
-
-static void gen_op_store_FT0_fpr(unsigned int dst)
-{
- tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ft0));
- tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst]));
-}
-
static void gen_op_load_fpr_DT0(unsigned int src)
{
- tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
- tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) +
+ tcg_gen_st_i32(cpu_fpr[src], cpu_env, offsetof(CPUSPARCState, dt0) +
offsetof(CPU_DoubleU, l.upper));
- tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
- tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) +
+ tcg_gen_st_i32(cpu_fpr[src + 1], cpu_env, offsetof(CPUSPARCState, dt0) +
offsetof(CPU_DoubleU, l.lower));
}
static void gen_op_load_fpr_DT1(unsigned int src)
{
- tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
- tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt1) +
+ tcg_gen_st_i32(cpu_fpr[src], cpu_env, offsetof(CPUSPARCState, dt1) +
offsetof(CPU_DoubleU, l.upper));
- tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
- tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt1) +
+ tcg_gen_st_i32(cpu_fpr[src + 1], cpu_env, offsetof(CPUSPARCState, dt1) +
offsetof(CPU_DoubleU, l.lower));
}
static void gen_op_store_DT0_fpr(unsigned int dst)
{
- tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) +
+ tcg_gen_ld_i32(cpu_fpr[dst], cpu_env, offsetof(CPUSPARCState, dt0) +
offsetof(CPU_DoubleU, l.upper));
- tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst]));
- tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) +
+ tcg_gen_ld_i32(cpu_fpr[dst + 1], cpu_env, offsetof(CPUSPARCState, dt0) +
offsetof(CPU_DoubleU, l.lower));
- tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 1]));
}
static void gen_op_load_fpr_QT0(unsigned int src)
{
- tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
- tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
+ tcg_gen_st_i32(cpu_fpr[src], cpu_env, offsetof(CPUSPARCState, qt0) +
offsetof(CPU_QuadU, l.upmost));
- tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
- tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
+ tcg_gen_st_i32(cpu_fpr[src + 1], cpu_env, offsetof(CPUSPARCState, qt0) +
offsetof(CPU_QuadU, l.upper));
- tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 2]));
- tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
+ tcg_gen_st_i32(cpu_fpr[src + 2], cpu_env, offsetof(CPUSPARCState, qt0) +
offsetof(CPU_QuadU, l.lower));
- tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 3]));
- tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
+ tcg_gen_st_i32(cpu_fpr[src + 3], cpu_env, offsetof(CPUSPARCState, qt0) +
offsetof(CPU_QuadU, l.lowest));
}
static void gen_op_load_fpr_QT1(unsigned int src)
{
- tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
- tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) +
+ tcg_gen_st_i32(cpu_fpr[src], cpu_env, offsetof(CPUSPARCState, qt1) +
offsetof(CPU_QuadU, l.upmost));
- tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
- tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) +
+ tcg_gen_st_i32(cpu_fpr[src + 1], cpu_env, offsetof(CPUSPARCState, qt1) +
offsetof(CPU_QuadU, l.upper));
- tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 2]));
- tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) +
+ tcg_gen_st_i32(cpu_fpr[src + 2], cpu_env, offsetof(CPUSPARCState, qt1) +
offsetof(CPU_QuadU, l.lower));
- tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 3]));
- tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) +
+ tcg_gen_st_i32(cpu_fpr[src + 3], cpu_env, offsetof(CPUSPARCState, qt1) +
offsetof(CPU_QuadU, l.lowest));
}
static void gen_op_store_QT0_fpr(unsigned int dst)
{
- tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
+ tcg_gen_ld_i32(cpu_fpr[dst], cpu_env, offsetof(CPUSPARCState, qt0) +
offsetof(CPU_QuadU, l.upmost));
- tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst]));
- tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
+ tcg_gen_ld_i32(cpu_fpr[dst + 1], cpu_env, offsetof(CPUSPARCState, qt0) +
offsetof(CPU_QuadU, l.upper));
- tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 1]));
- tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
+ tcg_gen_ld_i32(cpu_fpr[dst + 2], cpu_env, offsetof(CPUSPARCState, qt0) +
offsetof(CPU_QuadU, l.lower));
- tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 2]));
- tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
+ tcg_gen_ld_i32(cpu_fpr[dst + 3], cpu_env, offsetof(CPUSPARCState, qt0) +
offsetof(CPU_QuadU, l.lowest));
- tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 3]));
}
/* moves */
}
}
-static GenOpFunc * const gen_fcmps[4] = {
- helper_fcmps,
- helper_fcmps_fcc1,
- helper_fcmps_fcc2,
- helper_fcmps_fcc3,
-};
-
static GenOpFunc * const gen_fcmpd[4] = {
helper_fcmpd,
helper_fcmpd_fcc1,
helper_fcmpq_fcc3,
};
-static GenOpFunc * const gen_fcmpes[4] = {
- helper_fcmpes,
- helper_fcmpes_fcc1,
- helper_fcmpes_fcc2,
- helper_fcmpes_fcc3,
-};
-
static GenOpFunc * const gen_fcmped[4] = {
helper_fcmped,
helper_fcmped_fcc1,
helper_fcmpeq_fcc3,
};
-static inline void gen_op_fcmps(int fccno)
+static inline void gen_op_fcmps(int fccno, TCGv r_rs1, TCGv r_rs2)
{
- tcg_gen_helper_0_0(gen_fcmps[fccno]);
+ switch (fccno) {
+ case 0:
+ tcg_gen_helper_0_2(helper_fcmps, r_rs1, r_rs2);
+ break;
+ case 1:
+ tcg_gen_helper_0_2(helper_fcmps_fcc1, r_rs1, r_rs2);
+ break;
+ case 2:
+ tcg_gen_helper_0_2(helper_fcmps_fcc2, r_rs1, r_rs2);
+ break;
+ case 3:
+ tcg_gen_helper_0_2(helper_fcmps_fcc3, r_rs1, r_rs2);
+ break;
+ }
}
static inline void gen_op_fcmpd(int fccno)
tcg_gen_helper_0_0(gen_fcmpq[fccno]);
}
-static inline void gen_op_fcmpes(int fccno)
+static inline void gen_op_fcmpes(int fccno, TCGv r_rs1, TCGv r_rs2)
{
- tcg_gen_helper_0_0(gen_fcmpes[fccno]);
+ switch (fccno) {
+ case 0:
+ tcg_gen_helper_0_2(helper_fcmpes, r_rs1, r_rs2);
+ break;
+ case 1:
+ tcg_gen_helper_0_2(helper_fcmpes_fcc1, r_rs1, r_rs2);
+ break;
+ case 2:
+ tcg_gen_helper_0_2(helper_fcmpes_fcc2, r_rs1, r_rs2);
+ break;
+ case 3:
+ tcg_gen_helper_0_2(helper_fcmpes_fcc3, r_rs1, r_rs2);
+ break;
+ }
}
static inline void gen_op_fcmped(int fccno)
#else
-static inline void gen_op_fcmps(int fccno)
+static inline void gen_op_fcmps(int fccno, TCGv r_rs1, TCGv r_rs2)
{
- tcg_gen_helper_0_0(helper_fcmps);
+ tcg_gen_helper_0_2(helper_fcmps, r_rs1, r_rs2);
}
static inline void gen_op_fcmpd(int fccno)
tcg_gen_helper_0_0(helper_fcmpq);
}
-static inline void gen_op_fcmpes(int fccno)
+static inline void gen_op_fcmpes(int fccno, TCGv r_rs1, TCGv r_rs2)
{
- tcg_gen_helper_0_0(helper_fcmpes);
+ tcg_gen_helper_0_2(helper_fcmpes, r_rs1, r_rs2);
}
static inline void gen_op_fcmped(int fccno)
xop = GET_FIELD(insn, 18, 26);
switch (xop) {
case 0x1: /* fmovs */
- gen_op_load_fpr_FT0(rs2);
- gen_op_store_FT0_fpr(rd);
+ tcg_gen_mov_i32(cpu_fpr[rd], cpu_fpr[rs2]);
break;
case 0x5: /* fnegs */
- gen_op_load_fpr_FT1(rs2);
- tcg_gen_helper_0_0(helper_fnegs);
- gen_op_store_FT0_fpr(rd);
+ tcg_gen_helper_1_1(helper_fnegs, cpu_fpr[rd],
+ cpu_fpr[rs2]);
break;
case 0x9: /* fabss */
- gen_op_load_fpr_FT1(rs2);
- tcg_gen_helper_0_0(helper_fabss);
- gen_op_store_FT0_fpr(rd);
+ tcg_gen_helper_1_1(helper_fabss, cpu_fpr[rd],
+ cpu_fpr[rs2]);
break;
case 0x29: /* fsqrts */
CHECK_FPU_FEATURE(dc, FSQRT);
- gen_op_load_fpr_FT1(rs2);
gen_clear_float_exceptions();
- tcg_gen_helper_0_0(helper_fsqrts);
+ tcg_gen_helper_1_1(helper_fsqrts, cpu_tmp32,
+ cpu_fpr[rs2]);
tcg_gen_helper_0_0(helper_check_ieee_exceptions);
- gen_op_store_FT0_fpr(rd);
+ tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);
break;
case 0x2a: /* fsqrtd */
CHECK_FPU_FEATURE(dc, FSQRT);
tcg_gen_helper_0_0(helper_check_ieee_exceptions);
gen_op_store_QT0_fpr(QFPREG(rd));
break;
- case 0x41:
- gen_op_load_fpr_FT0(rs1);
- gen_op_load_fpr_FT1(rs2);
+ case 0x41: /* fadds */
gen_clear_float_exceptions();
- tcg_gen_helper_0_0(helper_fadds);
+ tcg_gen_helper_1_2(helper_fadds, cpu_tmp32,
+ cpu_fpr[rs1], cpu_fpr[rs2]);
tcg_gen_helper_0_0(helper_check_ieee_exceptions);
- gen_op_store_FT0_fpr(rd);
+ tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);
break;
case 0x42:
gen_op_load_fpr_DT0(DFPREG(rs1));
tcg_gen_helper_0_0(helper_check_ieee_exceptions);
gen_op_store_QT0_fpr(QFPREG(rd));
break;
- case 0x45:
- gen_op_load_fpr_FT0(rs1);
- gen_op_load_fpr_FT1(rs2);
+ case 0x45: /* fsubs */
gen_clear_float_exceptions();
- tcg_gen_helper_0_0(helper_fsubs);
+ tcg_gen_helper_1_2(helper_fsubs, cpu_tmp32,
+ cpu_fpr[rs1], cpu_fpr[rs2]);
tcg_gen_helper_0_0(helper_check_ieee_exceptions);
- gen_op_store_FT0_fpr(rd);
+ tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);
break;
case 0x46:
gen_op_load_fpr_DT0(DFPREG(rs1));
break;
case 0x49: /* fmuls */
CHECK_FPU_FEATURE(dc, FMUL);
- gen_op_load_fpr_FT0(rs1);
- gen_op_load_fpr_FT1(rs2);
gen_clear_float_exceptions();
- tcg_gen_helper_0_0(helper_fmuls);
+ tcg_gen_helper_1_2(helper_fmuls, cpu_tmp32,
+ cpu_fpr[rs1], cpu_fpr[rs2]);
tcg_gen_helper_0_0(helper_check_ieee_exceptions);
- gen_op_store_FT0_fpr(rd);
+ tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);
break;
case 0x4a: /* fmuld */
CHECK_FPU_FEATURE(dc, FMUL);
tcg_gen_helper_0_0(helper_check_ieee_exceptions);
gen_op_store_QT0_fpr(QFPREG(rd));
break;
- case 0x4d:
- gen_op_load_fpr_FT0(rs1);
- gen_op_load_fpr_FT1(rs2);
+ case 0x4d: /* fdivs */
gen_clear_float_exceptions();
- tcg_gen_helper_0_0(helper_fdivs);
+ tcg_gen_helper_1_2(helper_fdivs, cpu_tmp32,
+ cpu_fpr[rs1], cpu_fpr[rs2]);
tcg_gen_helper_0_0(helper_check_ieee_exceptions);
- gen_op_store_FT0_fpr(rd);
+ tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);
break;
case 0x4e:
gen_op_load_fpr_DT0(DFPREG(rs1));
tcg_gen_helper_0_0(helper_check_ieee_exceptions);
gen_op_store_QT0_fpr(QFPREG(rd));
break;
- case 0x69:
+ case 0x69: /* fsmuld */
CHECK_FPU_FEATURE(dc, FSMULD);
- gen_op_load_fpr_FT0(rs1);
- gen_op_load_fpr_FT1(rs2);
gen_clear_float_exceptions();
- tcg_gen_helper_0_0(helper_fsmuld);
+ tcg_gen_helper_0_2(helper_fsmuld, cpu_fpr[rs1],
+ cpu_fpr[rs2]);
tcg_gen_helper_0_0(helper_check_ieee_exceptions);
gen_op_store_DT0_fpr(DFPREG(rd));
break;
tcg_gen_helper_0_0(helper_check_ieee_exceptions);
gen_op_store_QT0_fpr(QFPREG(rd));
break;
- case 0xc4:
- gen_op_load_fpr_FT1(rs2);
+ case 0xc4: /* fitos */
gen_clear_float_exceptions();
- tcg_gen_helper_0_0(helper_fitos);
+ tcg_gen_helper_1_1(helper_fitos, cpu_tmp32,
+ cpu_fpr[rs2]);
tcg_gen_helper_0_0(helper_check_ieee_exceptions);
- gen_op_store_FT0_fpr(rd);
+ tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);
break;
- case 0xc6:
+ case 0xc6: /* fdtos */
gen_op_load_fpr_DT1(DFPREG(rs2));
gen_clear_float_exceptions();
- tcg_gen_helper_0_0(helper_fdtos);
+ tcg_gen_helper_1_0(helper_fdtos, cpu_tmp32);
tcg_gen_helper_0_0(helper_check_ieee_exceptions);
- gen_op_store_FT0_fpr(rd);
+ tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);
break;
case 0xc7: /* fqtos */
CHECK_FPU_FEATURE(dc, FLOAT128);
gen_op_load_fpr_QT1(QFPREG(rs2));
gen_clear_float_exceptions();
- tcg_gen_helper_0_0(helper_fqtos);
+ tcg_gen_helper_1_0(helper_fqtos, cpu_tmp32);
tcg_gen_helper_0_0(helper_check_ieee_exceptions);
- gen_op_store_FT0_fpr(rd);
+ tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);
break;
- case 0xc8:
- gen_op_load_fpr_FT1(rs2);
- tcg_gen_helper_0_0(helper_fitod);
+ case 0xc8: /* fitod */
+ tcg_gen_helper_0_1(helper_fitod, cpu_fpr[rs2]);
gen_op_store_DT0_fpr(DFPREG(rd));
break;
- case 0xc9:
- gen_op_load_fpr_FT1(rs2);
- tcg_gen_helper_0_0(helper_fstod);
+ case 0xc9: /* fstod */
+ tcg_gen_helper_0_1(helper_fstod, cpu_fpr[rs2]);
gen_op_store_DT0_fpr(DFPREG(rd));
break;
case 0xcb: /* fqtod */
break;
case 0xcc: /* fitoq */
CHECK_FPU_FEATURE(dc, FLOAT128);
- gen_op_load_fpr_FT1(rs2);
- tcg_gen_helper_0_0(helper_fitoq);
+ tcg_gen_helper_0_1(helper_fitoq, cpu_fpr[rs2]);
gen_op_store_QT0_fpr(QFPREG(rd));
break;
case 0xcd: /* fstoq */
CHECK_FPU_FEATURE(dc, FLOAT128);
- gen_op_load_fpr_FT1(rs2);
- tcg_gen_helper_0_0(helper_fstoq);
+ tcg_gen_helper_0_1(helper_fstoq, cpu_fpr[rs2]);
gen_op_store_QT0_fpr(QFPREG(rd));
break;
case 0xce: /* fdtoq */
tcg_gen_helper_0_0(helper_fdtoq);
gen_op_store_QT0_fpr(QFPREG(rd));
break;
- case 0xd1:
- gen_op_load_fpr_FT1(rs2);
+ case 0xd1: /* fstoi */
gen_clear_float_exceptions();
- tcg_gen_helper_0_0(helper_fstoi);
+ tcg_gen_helper_1_1(helper_fstoi, cpu_tmp32,
+ cpu_fpr[rs2]);
tcg_gen_helper_0_0(helper_check_ieee_exceptions);
- gen_op_store_FT0_fpr(rd);
+ tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);
break;
- case 0xd2:
+ case 0xd2: /* fdtoi */
gen_op_load_fpr_DT1(DFPREG(rs2));
gen_clear_float_exceptions();
- tcg_gen_helper_0_0(helper_fdtoi);
+ tcg_gen_helper_1_0(helper_fdtoi, cpu_tmp32);
tcg_gen_helper_0_0(helper_check_ieee_exceptions);
- gen_op_store_FT0_fpr(rd);
+ tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);
break;
case 0xd3: /* fqtoi */
CHECK_FPU_FEATURE(dc, FLOAT128);
gen_op_load_fpr_QT1(QFPREG(rs2));
gen_clear_float_exceptions();
- tcg_gen_helper_0_0(helper_fqtoi);
+ tcg_gen_helper_1_0(helper_fqtoi, cpu_tmp32);
tcg_gen_helper_0_0(helper_check_ieee_exceptions);
- gen_op_store_FT0_fpr(rd);
+ tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);
break;
#ifdef TARGET_SPARC64
case 0x2: /* V9 fmovd */
- gen_op_load_fpr_DT0(DFPREG(rs2));
- gen_op_store_DT0_fpr(DFPREG(rd));
+ tcg_gen_mov_i32(cpu_fpr[DFPREG(rd)],
+ cpu_fpr[DFPREG(rs2)]);
+ tcg_gen_mov_i32(cpu_fpr[DFPREG(rd) + 1],
+ cpu_fpr[DFPREG(rs2) + 1]);
break;
case 0x3: /* V9 fmovq */
CHECK_FPU_FEATURE(dc, FLOAT128);
- gen_op_load_fpr_QT0(QFPREG(rs2));
- gen_op_store_QT0_fpr(QFPREG(rd));
+ tcg_gen_mov_i32(cpu_fpr[QFPREG(rd)],
+ cpu_fpr[QFPREG(rs2)]);
+ tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 1],
+ cpu_fpr[QFPREG(rs2) + 1]);
+ tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 2],
+ cpu_fpr[QFPREG(rs2) + 2]);
+ tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 3],
+ cpu_fpr[QFPREG(rs2) + 3]);
break;
case 0x6: /* V9 fnegd */
gen_op_load_fpr_DT1(DFPREG(rs2));
gen_op_store_QT0_fpr(QFPREG(rd));
break;
case 0x81: /* V9 fstox */
- gen_op_load_fpr_FT1(rs2);
gen_clear_float_exceptions();
- tcg_gen_helper_0_0(helper_fstox);
+ tcg_gen_helper_0_1(helper_fstox, cpu_fpr[rs2]);
tcg_gen_helper_0_0(helper_check_ieee_exceptions);
gen_op_store_DT0_fpr(DFPREG(rd));
break;
case 0x84: /* V9 fxtos */
gen_op_load_fpr_DT1(DFPREG(rs2));
gen_clear_float_exceptions();
- tcg_gen_helper_0_0(helper_fxtos);
+ tcg_gen_helper_1_0(helper_fxtos, cpu_tmp32);
tcg_gen_helper_0_0(helper_check_ieee_exceptions);
- gen_op_store_FT0_fpr(rd);
+ tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);
break;
case 0x88: /* V9 fxtod */
gen_op_load_fpr_DT1(DFPREG(rs2));
cpu_src1 = get_src1(insn, cpu_src1);
tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], cpu_src1,
0, l1);
- gen_op_load_fpr_FT0(rs2);
- gen_op_store_FT0_fpr(rd);
+ tcg_gen_mov_i32(cpu_fpr[rd], cpu_fpr[rs2]);
gen_set_label(l1);
break;
} else if ((xop & 0x11f) == 0x006) { // V9 fmovdr
cpu_src1 = get_src1(insn, cpu_src1);
tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], cpu_src1,
0, l1);
- gen_op_load_fpr_DT0(DFPREG(rs2));
- gen_op_store_DT0_fpr(DFPREG(rd));
+ tcg_gen_mov_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs2)]);
+ tcg_gen_mov_i32(cpu_fpr[DFPREG(rd) + 1], cpu_fpr[DFPREG(rs2) + 1]);
gen_set_label(l1);
break;
} else if ((xop & 0x11f) == 0x007) { // V9 fmovqr
cpu_src1 = get_src1(insn, cpu_src1);
tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], cpu_src1,
0, l1);
- gen_op_load_fpr_QT0(QFPREG(rs2));
- gen_op_store_QT0_fpr(QFPREG(rd));
+ tcg_gen_mov_i32(cpu_fpr[QFPREG(rd)], cpu_fpr[QFPREG(rs2)]);
+ tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 1], cpu_fpr[QFPREG(rs2) + 1]);
+ tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 2], cpu_fpr[QFPREG(rs2) + 2]);
+ tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 3], cpu_fpr[QFPREG(rs2) + 3]);
gen_set_label(l1);
break;
}
#endif
switch (xop) {
#ifdef TARGET_SPARC64
-#define FMOVCC(size_FDQ, fcc) \
+#define FMOVSCC(fcc) \
{ \
TCGv r_cond; \
int l1; \
gen_fcond(r_cond, fcc, cond); \
tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \
0, l1); \
- glue(glue(gen_op_load_fpr_, size_FDQ), T0) \
- (glue(size_FDQ, FPREG(rs2))); \
- glue(glue(gen_op_store_, size_FDQ), T0_fpr) \
- (glue(size_FDQ, FPREG(rd))); \
+ tcg_gen_mov_i32(cpu_fpr[rd], cpu_fpr[rs2]); \
+ gen_set_label(l1); \
+ tcg_temp_free(r_cond); \
+ }
+#define FMOVDCC(fcc) \
+ { \
+ TCGv r_cond; \
+ int l1; \
+ \
+ l1 = gen_new_label(); \
+ r_cond = tcg_temp_new(TCG_TYPE_TL); \
+ cond = GET_FIELD_SP(insn, 14, 17); \
+ gen_fcond(r_cond, fcc, cond); \
+ tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \
+ 0, l1); \
+ tcg_gen_mov_i32(cpu_fpr[DFPREG(rd)], \
+ cpu_fpr[DFPREG(rs2)]); \
+ tcg_gen_mov_i32(cpu_fpr[DFPREG(rd) + 1], \
+ cpu_fpr[DFPREG(rs2) + 1]); \
+ gen_set_label(l1); \
+ tcg_temp_free(r_cond); \
+ }
+#define FMOVQCC(fcc) \
+ { \
+ TCGv r_cond; \
+ int l1; \
+ \
+ l1 = gen_new_label(); \
+ r_cond = tcg_temp_new(TCG_TYPE_TL); \
+ cond = GET_FIELD_SP(insn, 14, 17); \
+ gen_fcond(r_cond, fcc, cond); \
+ tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \
+ 0, l1); \
+ tcg_gen_mov_i32(cpu_fpr[QFPREG(rd)], \
+ cpu_fpr[QFPREG(rs2)]); \
+ tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 1], \
+ cpu_fpr[QFPREG(rs2) + 1]); \
+ tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 2], \
+ cpu_fpr[QFPREG(rs2) + 2]); \
+ tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 3], \
+ cpu_fpr[QFPREG(rs2) + 3]); \
gen_set_label(l1); \
tcg_temp_free(r_cond); \
}
case 0x001: /* V9 fmovscc %fcc0 */
- FMOVCC(F, 0);
+ FMOVSCC(0);
break;
case 0x002: /* V9 fmovdcc %fcc0 */
- FMOVCC(D, 0);
+ FMOVDCC(0);
break;
case 0x003: /* V9 fmovqcc %fcc0 */
CHECK_FPU_FEATURE(dc, FLOAT128);
- FMOVCC(Q, 0);
+ FMOVQCC(0);
break;
case 0x041: /* V9 fmovscc %fcc1 */
- FMOVCC(F, 1);
+ FMOVSCC(1);
break;
case 0x042: /* V9 fmovdcc %fcc1 */
- FMOVCC(D, 1);
+ FMOVDCC(1);
break;
case 0x043: /* V9 fmovqcc %fcc1 */
CHECK_FPU_FEATURE(dc, FLOAT128);
- FMOVCC(Q, 1);
+ FMOVQCC(1);
break;
case 0x081: /* V9 fmovscc %fcc2 */
- FMOVCC(F, 2);
+ FMOVSCC(2);
break;
case 0x082: /* V9 fmovdcc %fcc2 */
- FMOVCC(D, 2);
+ FMOVDCC(2);
break;
case 0x083: /* V9 fmovqcc %fcc2 */
CHECK_FPU_FEATURE(dc, FLOAT128);
- FMOVCC(Q, 2);
+ FMOVQCC(2);
break;
case 0x0c1: /* V9 fmovscc %fcc3 */
- FMOVCC(F, 3);
+ FMOVSCC(3);
break;
case 0x0c2: /* V9 fmovdcc %fcc3 */
- FMOVCC(D, 3);
+ FMOVDCC(3);
break;
case 0x0c3: /* V9 fmovqcc %fcc3 */
CHECK_FPU_FEATURE(dc, FLOAT128);
- FMOVCC(Q, 3);
+ FMOVQCC(3);
break;
-#undef FMOVCC
+#undef FMOVSCC
+#undef FMOVDCC
+#undef FMOVQCC
#define FMOVCC(size_FDQ, icc) \
{ \
TCGv r_cond; \
gen_set_label(l1); \
tcg_temp_free(r_cond); \
}
+#define FMOVSCC(icc) \
+ { \
+ TCGv r_cond; \
+ int l1; \
+ \
+ l1 = gen_new_label(); \
+ r_cond = tcg_temp_new(TCG_TYPE_TL); \
+ cond = GET_FIELD_SP(insn, 14, 17); \
+ gen_cond(r_cond, icc, cond); \
+ tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \
+ 0, l1); \
+ tcg_gen_mov_i32(cpu_fpr[rd], cpu_fpr[rs2]); \
+ gen_set_label(l1); \
+ tcg_temp_free(r_cond); \
+ }
+#define FMOVDCC(icc) \
+ { \
+ TCGv r_cond; \
+ int l1; \
+ \
+ l1 = gen_new_label(); \
+ r_cond = tcg_temp_new(TCG_TYPE_TL); \
+ cond = GET_FIELD_SP(insn, 14, 17); \
+ gen_cond(r_cond, icc, cond); \
+ tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \
+ 0, l1); \
+ tcg_gen_mov_i32(cpu_fpr[DFPREG(rd)], \
+ cpu_fpr[DFPREG(rs2)]); \
+ tcg_gen_mov_i32(cpu_fpr[DFPREG(rd) + 1], \
+ cpu_fpr[DFPREG(rs2) + 1]); \
+ gen_set_label(l1); \
+ tcg_temp_free(r_cond); \
+ }
+#define FMOVQCC(icc) \
+ { \
+ TCGv r_cond; \
+ int l1; \
+ \
+ l1 = gen_new_label(); \
+ r_cond = tcg_temp_new(TCG_TYPE_TL); \
+ cond = GET_FIELD_SP(insn, 14, 17); \
+ gen_cond(r_cond, icc, cond); \
+ tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \
+ 0, l1); \
+ tcg_gen_mov_i32(cpu_fpr[QFPREG(rd)], \
+ cpu_fpr[QFPREG(rs2)]); \
+ tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 1], \
+ cpu_fpr[QFPREG(rs2) + 1]); \
+ tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 2], \
+ cpu_fpr[QFPREG(rs2) + 2]); \
+ tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 3], \
+ cpu_fpr[QFPREG(rs2) + 3]); \
+ gen_set_label(l1); \
+ tcg_temp_free(r_cond); \
+ }
case 0x101: /* V9 fmovscc %icc */
- FMOVCC(F, 0);
+ FMOVSCC(0);
break;
case 0x102: /* V9 fmovdcc %icc */
- FMOVCC(D, 0);
+ FMOVDCC(0);
case 0x103: /* V9 fmovqcc %icc */
CHECK_FPU_FEATURE(dc, FLOAT128);
- FMOVCC(Q, 0);
+ FMOVQCC(0);
break;
case 0x181: /* V9 fmovscc %xcc */
- FMOVCC(F, 1);
+ FMOVSCC(1);
break;
case 0x182: /* V9 fmovdcc %xcc */
- FMOVCC(D, 1);
+ FMOVDCC(1);
break;
case 0x183: /* V9 fmovqcc %xcc */
CHECK_FPU_FEATURE(dc, FLOAT128);
- FMOVCC(Q, 1);
+ FMOVQCC(1);
break;
-#undef FMOVCC
+#undef FMOVSCC
+#undef FMOVDCC
+#undef FMOVQCC
#endif
case 0x51: /* fcmps, V9 %fcc */
- gen_op_load_fpr_FT0(rs1);
- gen_op_load_fpr_FT1(rs2);
- gen_op_fcmps(rd & 3);
+ gen_op_fcmps(rd & 3, cpu_fpr[rs1], cpu_fpr[rs2]);
break;
case 0x52: /* fcmpd, V9 %fcc */
gen_op_load_fpr_DT0(DFPREG(rs1));
gen_op_fcmpq(rd & 3);
break;
case 0x55: /* fcmpes, V9 %fcc */
- gen_op_load_fpr_FT0(rs1);
- gen_op_load_fpr_FT1(rs2);
- gen_op_fcmpes(rd & 3);
+ gen_op_fcmpes(rd & 3, cpu_fpr[rs1], cpu_fpr[rs2]);
break;
case 0x56: /* fcmped, V9 %fcc */
gen_op_load_fpr_DT0(DFPREG(rs1));
break;
case 0x051: /* VIS I fpadd16s */
CHECK_FPU_FEATURE(dc, VIS1);
- gen_op_load_fpr_FT0(rs1);
- gen_op_load_fpr_FT1(rs2);
- tcg_gen_helper_0_0(helper_fpadd16s);
- gen_op_store_FT0_fpr(rd);
+ tcg_gen_helper_1_2(helper_fpadd16s, cpu_fpr[rd],
+ cpu_fpr[rs1], cpu_fpr[rs2]);
break;
case 0x052: /* VIS I fpadd32 */
CHECK_FPU_FEATURE(dc, VIS1);
break;
case 0x053: /* VIS I fpadd32s */
CHECK_FPU_FEATURE(dc, VIS1);
- gen_op_load_fpr_FT0(rs1);
- gen_op_load_fpr_FT1(rs2);
- tcg_gen_helper_0_0(helper_fpadd32s);
- gen_op_store_FT0_fpr(rd);
+ tcg_gen_helper_1_2(helper_fpadd32s, cpu_fpr[rd],
+ cpu_fpr[rs1], cpu_fpr[rs2]);
break;
case 0x054: /* VIS I fpsub16 */
CHECK_FPU_FEATURE(dc, VIS1);
break;
case 0x055: /* VIS I fpsub16s */
CHECK_FPU_FEATURE(dc, VIS1);
- gen_op_load_fpr_FT0(rs1);
- gen_op_load_fpr_FT1(rs2);
- tcg_gen_helper_0_0(helper_fpsub16s);
- gen_op_store_FT0_fpr(rd);
+ tcg_gen_helper_1_2(helper_fpsub16s, cpu_fpr[rd],
+ cpu_fpr[rs1], cpu_fpr[rs2]);
break;
case 0x056: /* VIS I fpsub32 */
CHECK_FPU_FEATURE(dc, VIS1);
gen_op_load_fpr_DT0(DFPREG(rs1));
gen_op_load_fpr_DT1(DFPREG(rs2));
- tcg_gen_helper_0_0(helper_fpadd32);
+ tcg_gen_helper_0_0(helper_fpsub32);
gen_op_store_DT0_fpr(DFPREG(rd));
break;
case 0x057: /* VIS I fpsub32s */
CHECK_FPU_FEATURE(dc, VIS1);
- gen_op_load_fpr_FT0(rs1);
- gen_op_load_fpr_FT1(rs2);
- tcg_gen_helper_0_0(helper_fpsub32s);
- gen_op_store_FT0_fpr(rd);
+ tcg_gen_helper_1_2(helper_fpsub32s, cpu_fpr[rd],
+ cpu_fpr[rs1], cpu_fpr[rs2]);
break;
case 0x060: /* VIS I fzero */
CHECK_FPU_FEATURE(dc, VIS1);
- tcg_gen_helper_0_0(helper_movl_DT0_0);
- gen_op_store_DT0_fpr(DFPREG(rd));
+ tcg_gen_movi_i32(cpu_fpr[DFPREG(rd)], 0);
+ tcg_gen_movi_i32(cpu_fpr[DFPREG(rd) + 1], 0);
break;
case 0x061: /* VIS I fzeros */
CHECK_FPU_FEATURE(dc, VIS1);
- tcg_gen_helper_0_0(helper_movl_FT0_0);
- gen_op_store_FT0_fpr(rd);
+ tcg_gen_movi_i32(cpu_fpr[rd], 0);
break;
case 0x062: /* VIS I fnor */
CHECK_FPU_FEATURE(dc, VIS1);
- gen_op_load_fpr_DT0(DFPREG(rs1));
- gen_op_load_fpr_DT1(DFPREG(rs2));
- tcg_gen_helper_0_0(helper_fnor);
- gen_op_store_DT0_fpr(DFPREG(rd));
+ tcg_gen_or_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1)],
+ cpu_fpr[DFPREG(rs2)]);
+ tcg_gen_xori_i32(cpu_fpr[DFPREG(rd)], cpu_tmp32, -1);
+ tcg_gen_or_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1) + 1],
+ cpu_fpr[DFPREG(rs2) + 1]);
+ tcg_gen_xori_i32(cpu_fpr[DFPREG(rd) + 1], cpu_tmp32, -1);
break;
case 0x063: /* VIS I fnors */
CHECK_FPU_FEATURE(dc, VIS1);
- gen_op_load_fpr_FT0(rs1);
- gen_op_load_fpr_FT1(rs2);
- tcg_gen_helper_0_0(helper_fnors);
- gen_op_store_FT0_fpr(rd);
+ tcg_gen_or_i32(cpu_tmp32, cpu_fpr[rs1], cpu_fpr[rs2]);
+ tcg_gen_xori_i32(cpu_fpr[rd], cpu_tmp32, -1);
break;
case 0x064: /* VIS I fandnot2 */
CHECK_FPU_FEATURE(dc, VIS1);
- gen_op_load_fpr_DT1(DFPREG(rs1));
- gen_op_load_fpr_DT0(DFPREG(rs2));
- tcg_gen_helper_0_0(helper_fandnot);
- gen_op_store_DT0_fpr(DFPREG(rd));
+ tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1)], -1);
+ tcg_gen_and_i32(cpu_fpr[DFPREG(rd)], cpu_tmp32,
+ cpu_fpr[DFPREG(rs2)]);
+ tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1) + 1], -1);
+ tcg_gen_and_i32(cpu_fpr[DFPREG(rd) + 1], cpu_tmp32,
+ cpu_fpr[DFPREG(rs2) + 1]);
break;
case 0x065: /* VIS I fandnot2s */
CHECK_FPU_FEATURE(dc, VIS1);
- gen_op_load_fpr_FT1(rs1);
- gen_op_load_fpr_FT0(rs2);
- tcg_gen_helper_0_0(helper_fandnots);
- gen_op_store_FT0_fpr(rd);
+ tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[rs1], -1);
+ tcg_gen_and_i32(cpu_fpr[rd], cpu_tmp32, cpu_fpr[rs2]);
break;
case 0x066: /* VIS I fnot2 */
CHECK_FPU_FEATURE(dc, VIS1);
- gen_op_load_fpr_DT1(DFPREG(rs2));
- tcg_gen_helper_0_0(helper_fnot);
- gen_op_store_DT0_fpr(DFPREG(rd));
+ tcg_gen_xori_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs2)],
+ -1);
+ tcg_gen_xori_i32(cpu_fpr[DFPREG(rd) + 1],
+ cpu_fpr[DFPREG(rs2) + 1], -1);
break;
case 0x067: /* VIS I fnot2s */
CHECK_FPU_FEATURE(dc, VIS1);
- gen_op_load_fpr_FT1(rs2);
- tcg_gen_helper_0_0(helper_fnot);
- gen_op_store_FT0_fpr(rd);
+ tcg_gen_xori_i32(cpu_fpr[rd], cpu_fpr[rs2], -1);
break;
case 0x068: /* VIS I fandnot1 */
CHECK_FPU_FEATURE(dc, VIS1);
- gen_op_load_fpr_DT0(DFPREG(rs1));
- gen_op_load_fpr_DT1(DFPREG(rs2));
- tcg_gen_helper_0_0(helper_fandnot);
- gen_op_store_DT0_fpr(DFPREG(rd));
+ tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[DFPREG(rs2)], -1);
+ tcg_gen_and_i32(cpu_fpr[DFPREG(rd)], cpu_tmp32,
+ cpu_fpr[DFPREG(rs1)]);
+ tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[DFPREG(rs2)], -1);
+ tcg_gen_and_i32(cpu_fpr[DFPREG(rd) + 1], cpu_tmp32,
+ cpu_fpr[DFPREG(rs1) + 1]);
break;
case 0x069: /* VIS I fandnot1s */
CHECK_FPU_FEATURE(dc, VIS1);
- gen_op_load_fpr_FT0(rs1);
- gen_op_load_fpr_FT1(rs2);
- tcg_gen_helper_0_0(helper_fandnots);
- gen_op_store_FT0_fpr(rd);
+ tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[rs2], -1);
+ tcg_gen_and_i32(cpu_fpr[rd], cpu_tmp32, cpu_fpr[rs1]);
break;
case 0x06a: /* VIS I fnot1 */
CHECK_FPU_FEATURE(dc, VIS1);
- gen_op_load_fpr_DT1(DFPREG(rs1));
- tcg_gen_helper_0_0(helper_fnot);
- gen_op_store_DT0_fpr(DFPREG(rd));
+ tcg_gen_xori_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs1)],
+ -1);
+ tcg_gen_xori_i32(cpu_fpr[DFPREG(rd) + 1],
+ cpu_fpr[DFPREG(rs1) + 1], -1);
break;
case 0x06b: /* VIS I fnot1s */
CHECK_FPU_FEATURE(dc, VIS1);
- gen_op_load_fpr_FT1(rs1);
- tcg_gen_helper_0_0(helper_fnot);
- gen_op_store_FT0_fpr(rd);
+ tcg_gen_xori_i32(cpu_fpr[rd], cpu_fpr[rs1], -1);
break;
case 0x06c: /* VIS I fxor */
CHECK_FPU_FEATURE(dc, VIS1);
- gen_op_load_fpr_DT0(DFPREG(rs1));
- gen_op_load_fpr_DT1(DFPREG(rs2));
- tcg_gen_helper_0_0(helper_fxor);
- gen_op_store_DT0_fpr(DFPREG(rd));
+ tcg_gen_xor_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs1)],
+ cpu_fpr[DFPREG(rs2)]);
+ tcg_gen_xor_i32(cpu_fpr[DFPREG(rd) + 1],
+ cpu_fpr[DFPREG(rs1) + 1],
+ cpu_fpr[DFPREG(rs2) + 1]);
break;
case 0x06d: /* VIS I fxors */
CHECK_FPU_FEATURE(dc, VIS1);
- gen_op_load_fpr_FT0(rs1);
- gen_op_load_fpr_FT1(rs2);
- tcg_gen_helper_0_0(helper_fxors);
- gen_op_store_FT0_fpr(rd);
+ tcg_gen_xor_i32(cpu_fpr[rd], cpu_fpr[rs1], cpu_fpr[rs2]);
break;
case 0x06e: /* VIS I fnand */
CHECK_FPU_FEATURE(dc, VIS1);
- gen_op_load_fpr_DT0(DFPREG(rs1));
- gen_op_load_fpr_DT1(DFPREG(rs2));
- tcg_gen_helper_0_0(helper_fnand);
- gen_op_store_DT0_fpr(DFPREG(rd));
+ tcg_gen_and_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1)],
+ cpu_fpr[DFPREG(rs2)]);
+ tcg_gen_xori_i32(cpu_fpr[DFPREG(rd)], cpu_tmp32, -1);
+ tcg_gen_and_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1) + 1],
+ cpu_fpr[DFPREG(rs2) + 1]);
+ tcg_gen_xori_i32(cpu_fpr[DFPREG(rd) + 1], cpu_tmp32, -1);
break;
case 0x06f: /* VIS I fnands */
CHECK_FPU_FEATURE(dc, VIS1);
- gen_op_load_fpr_FT0(rs1);
- gen_op_load_fpr_FT1(rs2);
- tcg_gen_helper_0_0(helper_fnands);
- gen_op_store_FT0_fpr(rd);
+ tcg_gen_and_i32(cpu_tmp32, cpu_fpr[rs1], cpu_fpr[rs2]);
+ tcg_gen_xori_i32(cpu_fpr[rd], cpu_tmp32, -1);
break;
case 0x070: /* VIS I fand */
CHECK_FPU_FEATURE(dc, VIS1);
- gen_op_load_fpr_DT0(DFPREG(rs1));
- gen_op_load_fpr_DT1(DFPREG(rs2));
- tcg_gen_helper_0_0(helper_fand);
- gen_op_store_DT0_fpr(DFPREG(rd));
+ tcg_gen_and_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs1)],
+ cpu_fpr[DFPREG(rs2)]);
+ tcg_gen_and_i32(cpu_fpr[DFPREG(rd) + 1],
+ cpu_fpr[DFPREG(rs1) + 1],
+ cpu_fpr[DFPREG(rs2) + 1]);
break;
case 0x071: /* VIS I fands */
CHECK_FPU_FEATURE(dc, VIS1);
- gen_op_load_fpr_FT0(rs1);
- gen_op_load_fpr_FT1(rs2);
- tcg_gen_helper_0_0(helper_fands);
- gen_op_store_FT0_fpr(rd);
+ tcg_gen_and_i32(cpu_fpr[rd], cpu_fpr[rs1], cpu_fpr[rs2]);
break;
case 0x072: /* VIS I fxnor */
CHECK_FPU_FEATURE(dc, VIS1);
- gen_op_load_fpr_DT0(DFPREG(rs1));
- gen_op_load_fpr_DT1(DFPREG(rs2));
- tcg_gen_helper_0_0(helper_fxnor);
- gen_op_store_DT0_fpr(DFPREG(rd));
+ tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[DFPREG(rs2)], -1);
+ tcg_gen_xor_i32(cpu_fpr[DFPREG(rd)], cpu_tmp32,
+ cpu_fpr[DFPREG(rs1)]);
+ tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[DFPREG(rs2) + 1], -1);
+ tcg_gen_xor_i32(cpu_fpr[DFPREG(rd) + 1], cpu_tmp32,
+ cpu_fpr[DFPREG(rs1) + 1]);
break;
case 0x073: /* VIS I fxnors */
CHECK_FPU_FEATURE(dc, VIS1);
- gen_op_load_fpr_FT0(rs1);
- gen_op_load_fpr_FT1(rs2);
- tcg_gen_helper_0_0(helper_fxnors);
- gen_op_store_FT0_fpr(rd);
+ tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[rs2], -1);
+ tcg_gen_xor_i32(cpu_fpr[rd], cpu_tmp32, cpu_fpr[rs1]);
break;
case 0x074: /* VIS I fsrc1 */
CHECK_FPU_FEATURE(dc, VIS1);
- gen_op_load_fpr_DT0(DFPREG(rs1));
- gen_op_store_DT0_fpr(DFPREG(rd));
+ tcg_gen_mov_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs1)]);
+ tcg_gen_mov_i32(cpu_fpr[DFPREG(rd) + 1],
+ cpu_fpr[DFPREG(rs1) + 1]);
break;
case 0x075: /* VIS I fsrc1s */
CHECK_FPU_FEATURE(dc, VIS1);
- gen_op_load_fpr_FT0(rs1);
- gen_op_store_FT0_fpr(rd);
+ tcg_gen_mov_i32(cpu_fpr[rd], cpu_fpr[rs1]);
break;
case 0x076: /* VIS I fornot2 */
CHECK_FPU_FEATURE(dc, VIS1);
- gen_op_load_fpr_DT1(DFPREG(rs1));
- gen_op_load_fpr_DT0(DFPREG(rs2));
- tcg_gen_helper_0_0(helper_fornot);
- gen_op_store_DT0_fpr(DFPREG(rd));
+ tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1)], -1);
+ tcg_gen_or_i32(cpu_fpr[DFPREG(rd)], cpu_tmp32,
+ cpu_fpr[DFPREG(rs2)]);
+ tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1) + 1], -1);
+ tcg_gen_or_i32(cpu_fpr[DFPREG(rd) + 1], cpu_tmp32,
+ cpu_fpr[DFPREG(rs2) + 1]);
break;
case 0x077: /* VIS I fornot2s */
CHECK_FPU_FEATURE(dc, VIS1);
- gen_op_load_fpr_FT1(rs1);
- gen_op_load_fpr_FT0(rs2);
- tcg_gen_helper_0_0(helper_fornots);
- gen_op_store_FT0_fpr(rd);
+ tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[rs1], -1);
+ tcg_gen_or_i32(cpu_fpr[rd], cpu_tmp32, cpu_fpr[rs2]);
break;
case 0x078: /* VIS I fsrc2 */
CHECK_FPU_FEATURE(dc, VIS1);
break;
case 0x079: /* VIS I fsrc2s */
CHECK_FPU_FEATURE(dc, VIS1);
- gen_op_load_fpr_FT0(rs2);
- gen_op_store_FT0_fpr(rd);
+ tcg_gen_mov_i32(cpu_fpr[rd], cpu_fpr[rs2]);
break;
case 0x07a: /* VIS I fornot1 */
CHECK_FPU_FEATURE(dc, VIS1);
- gen_op_load_fpr_DT0(DFPREG(rs1));
- gen_op_load_fpr_DT1(DFPREG(rs2));
- tcg_gen_helper_0_0(helper_fornot);
- gen_op_store_DT0_fpr(DFPREG(rd));
+ tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[DFPREG(rs2)], -1);
+ tcg_gen_or_i32(cpu_fpr[DFPREG(rd)], cpu_tmp32,
+ cpu_fpr[DFPREG(rs1)]);
+ tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[DFPREG(rs2) + 1], -1);
+ tcg_gen_or_i32(cpu_fpr[DFPREG(rd) + 1], cpu_tmp32,
+ cpu_fpr[DFPREG(rs1) + 1]);
break;
case 0x07b: /* VIS I fornot1s */
CHECK_FPU_FEATURE(dc, VIS1);
- gen_op_load_fpr_FT0(rs1);
- gen_op_load_fpr_FT1(rs2);
- tcg_gen_helper_0_0(helper_fornots);
- gen_op_store_FT0_fpr(rd);
+ tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[rs2], -1);
+ tcg_gen_or_i32(cpu_fpr[rd], cpu_tmp32, cpu_fpr[rs1]);
break;
case 0x07c: /* VIS I for */
CHECK_FPU_FEATURE(dc, VIS1);
- gen_op_load_fpr_DT0(DFPREG(rs1));
- gen_op_load_fpr_DT1(DFPREG(rs2));
- tcg_gen_helper_0_0(helper_for);
- gen_op_store_DT0_fpr(DFPREG(rd));
+ tcg_gen_or_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs1)],
+ cpu_fpr[DFPREG(rs2)]);
+ tcg_gen_or_i32(cpu_fpr[DFPREG(rd) + 1],
+ cpu_fpr[DFPREG(rs1) + 1],
+ cpu_fpr[DFPREG(rs2) + 1]);
break;
case 0x07d: /* VIS I fors */
CHECK_FPU_FEATURE(dc, VIS1);
- gen_op_load_fpr_FT0(rs1);
- gen_op_load_fpr_FT1(rs2);
- tcg_gen_helper_0_0(helper_fors);
- gen_op_store_FT0_fpr(rd);
+ tcg_gen_or_i32(cpu_fpr[rd], cpu_fpr[rs1], cpu_fpr[rs2]);
break;
case 0x07e: /* VIS I fone */
CHECK_FPU_FEATURE(dc, VIS1);
- tcg_gen_helper_0_0(helper_movl_DT0_1);
- gen_op_store_DT0_fpr(DFPREG(rd));
+ tcg_gen_movi_i32(cpu_fpr[DFPREG(rd)], -1);
+ tcg_gen_movi_i32(cpu_fpr[DFPREG(rd) + 1], -1);
break;
case 0x07f: /* VIS I fones */
CHECK_FPU_FEATURE(dc, VIS1);
- tcg_gen_helper_0_0(helper_movl_FT0_1);
- gen_op_store_FT0_fpr(rd);
+ tcg_gen_movi_i32(cpu_fpr[rd], -1);
break;
case 0x080: /* VIS I shutdown */
case 0x081: /* VIS II siam */
switch (xop) {
case 0x20: /* load fpreg */
gen_address_mask(dc, cpu_addr);
- tcg_gen_qemu_ld32u(cpu_tmp32, cpu_addr, dc->mem_idx);
- tcg_gen_st_i32(cpu_tmp32, cpu_env,
- offsetof(CPUState, fpr[rd]));
+ tcg_gen_qemu_ld32u(cpu_fpr[rd], cpu_addr, dc->mem_idx);
break;
- case 0x21: /* load fsr */
+ case 0x21: /* ldfsr, V9 ldxfsr */
+#ifdef TARGET_SPARC64
gen_address_mask(dc, cpu_addr);
- tcg_gen_qemu_ld32u(cpu_tmp32, cpu_addr, dc->mem_idx);
- tcg_gen_st_i32(cpu_tmp32, cpu_env,
- offsetof(CPUState, ft0));
- tcg_gen_helper_0_0(helper_ldfsr);
+ if (rd == 1) {
+ tcg_gen_qemu_ld64(cpu_tmp64, cpu_addr, dc->mem_idx);
+ tcg_gen_helper_0_1(helper_ldxfsr, cpu_tmp64);
+ } else
+#else
+ {
+ tcg_gen_qemu_ld32u(cpu_tmp32, cpu_addr, dc->mem_idx);
+ tcg_gen_helper_0_1(helper_ldfsr, cpu_tmp32);
+ }
+#endif
break;
case 0x22: /* load quad fpreg */
{
switch (xop) {
case 0x24: /* store fpreg */
gen_address_mask(dc, cpu_addr);
- tcg_gen_ld_i32(cpu_tmp32, cpu_env,
- offsetof(CPUState, fpr[rd]));
- tcg_gen_qemu_st32(cpu_tmp32, cpu_addr, dc->mem_idx);
+ tcg_gen_qemu_st32(cpu_fpr[rd], cpu_addr, dc->mem_idx);
break;
case 0x25: /* stfsr, V9 stxfsr */
+#ifdef TARGET_SPARC64
gen_address_mask(dc, cpu_addr);
- tcg_gen_helper_0_0(helper_stfsr);
- tcg_gen_ld_i32(cpu_tmp32, cpu_env,
- offsetof(CPUState, ft0));
+ tcg_gen_ld_i64(cpu_tmp64, cpu_env, offsetof(CPUState, fsr));
+ if (rd == 1)
+ tcg_gen_qemu_st64(cpu_tmp64, cpu_addr, dc->mem_idx);
+ else {
+ tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp64);
+ tcg_gen_qemu_st32(cpu_tmp32, cpu_addr, dc->mem_idx);
+ }
+#else
+ tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUState, fsr));
tcg_gen_qemu_st32(cpu_tmp32, cpu_addr, dc->mem_idx);
+#endif
break;
case 0x26:
#ifdef TARGET_SPARC64
switch (xop) {
#ifdef TARGET_SPARC64
case 0x34: /* V9 stfa */
- gen_op_load_fpr_FT0(rd);
gen_stf_asi(cpu_addr, insn, 4, rd);
break;
case 0x36: /* V9 stqfa */
"g6",
"g7",
};
+ static const char * const fregnames[64] = {
+ "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
+ "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
+ "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
+ "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
+ "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39",
+ "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47",
+ "f48", "f49", "f50", "f51", "f52", "f53", "f54", "f55",
+ "f56", "f57", "f58", "f59", "f60", "f61", "f62", "f63",
+ };
/* init various static tables */
if (!inited) {
cpu_gregs[i] = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
offsetof(CPUState, gregs[i]),
gregnames[i]);
+ for (i = 0; i < TARGET_FPREGS; i++)
+ cpu_fpr[i] = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
+ offsetof(CPUState, fpr[i]),
+ fregnames[i]);
+
/* register helpers */
#undef DEF_HELPER
projects / qemu / blobdiff