#ifdef TARGET_SPARC64
static TCGv cpu_xcc, cpu_asi, cpu_fprs, cpu_gsr;
static TCGv cpu_tick_cmpr, cpu_stick_cmpr, cpu_hstick_cmpr;
-static TCGv cpu_hintp, cpu_htba, cpu_hver, cpu_ssr, cpu_ver;
+static TCGv cpu_hintp, cpu_htba, cpu_hver, cpu_ssr, cpu_ver, cpu_softint;
#else
static TCGv cpu_wim;
#endif
#define QFPREG(r) (r & 0x1c)
#endif
+#define UA2005_HTRAP_MASK 0xff
+#define V8_TRAP_MASK 0x7f
+
static int sign_extend(int x, int len)
{
len = 32 - len;
#define IS_IMM (insn & (1<<13))
/* floating point registers moves */
-static void gen_op_load_fpr_FT0(unsigned int src)
-{
- tcg_gen_st_i32(cpu_fpr[src], cpu_env, offsetof(CPUSPARCState, ft0));
-}
-
-static void gen_op_load_fpr_FT1(unsigned int src)
-{
- tcg_gen_st_i32(cpu_fpr[src], cpu_env, offsetof(CPUSPARCState, ft1));
-}
-
-static void gen_op_store_FT0_fpr(unsigned int dst)
-{
- tcg_gen_ld_i32(cpu_fpr[dst], cpu_env, offsetof(CPUSPARCState, ft0));
-}
-
static void gen_op_load_fpr_DT0(unsigned int src)
{
tcg_gen_st_i32(cpu_fpr[src], cpu_env, offsetof(CPUSPARCState, dt0) +
tcg_gen_brcondi_tl(TCG_COND_NE, r_temp, 0, l1);
tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_ZERO);
gen_set_label(l1);
- tcg_gen_ext_i32_tl(r_temp, dst);
+ tcg_gen_ext32s_tl(r_temp, dst);
tcg_gen_brcondi_tl(TCG_COND_GE, r_temp, 0, l2);
tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_NEG);
gen_set_label(l2);
if (!(env->y & 1))
T1 = 0;
*/
- tcg_gen_mov_tl(cpu_cc_src, src1);
+ tcg_gen_andi_tl(cpu_cc_src, src1, 0xffffffff);
tcg_gen_andi_tl(r_temp, cpu_y, 0x1);
- tcg_gen_mov_tl(cpu_cc_src2, src2);
+ tcg_gen_andi_tl(cpu_cc_src2, src2, 0xffffffff);
tcg_gen_brcondi_tl(TCG_COND_NE, r_temp, 0, l1);
tcg_gen_movi_tl(cpu_cc_src2, 0);
gen_set_label(l1);
tcg_gen_andi_tl(r_temp, cpu_cc_src, 0x1);
tcg_gen_shli_tl(r_temp, r_temp, 31);
tcg_gen_shri_tl(cpu_tmp0, cpu_y, 1);
- tcg_gen_or_tl(cpu_y, cpu_tmp0, r_temp);
+ tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0x7fffffff);
+ tcg_gen_or_tl(cpu_tmp0, cpu_tmp0, r_temp);
+ tcg_gen_andi_tl(cpu_y, cpu_tmp0, 0xffffffff);
// b1 = N ^ V;
gen_mov_reg_N(cpu_tmp0, cpu_psr);
r_temp = tcg_temp_new(TCG_TYPE_I64);
r_temp2 = tcg_temp_new(TCG_TYPE_I64);
- tcg_gen_extu_i32_i64(r_temp, src2);
- tcg_gen_extu_i32_i64(r_temp2, src1);
+ tcg_gen_extu_tl_i64(r_temp, src2);
+ tcg_gen_extu_tl_i64(r_temp2, src1);
tcg_gen_mul_i64(r_temp2, r_temp, r_temp2);
tcg_gen_shri_i64(r_temp, r_temp2, 32);
r_temp = tcg_temp_new(TCG_TYPE_I64);
r_temp2 = tcg_temp_new(TCG_TYPE_I64);
- tcg_gen_ext_i32_i64(r_temp, src2);
- tcg_gen_ext_i32_i64(r_temp2, src1);
+ tcg_gen_ext_tl_i64(r_temp, src2);
+ tcg_gen_ext_tl_i64(r_temp2, src1);
tcg_gen_mul_i64(r_temp2, r_temp, r_temp2);
tcg_gen_shri_i64(r_temp, r_temp2, 32);
static inline void gen_stda_asi(TCGv hi, TCGv addr, int insn, int rd)
{
- TCGv r_temp, r_asi, r_size;
+ TCGv r_asi, r_size;
- r_temp = tcg_temp_new(TCG_TYPE_TL);
- gen_movl_reg_TN(rd + 1, r_temp);
- tcg_gen_helper_1_2(helper_pack64, cpu_tmp64, hi,
- r_temp);
- tcg_temp_free(r_temp);
+ gen_movl_reg_TN(rd + 1, cpu_tmp0);
+ tcg_gen_concat_tl_i64(cpu_tmp64, cpu_tmp0, hi);
r_asi = gen_get_asi(insn, addr);
r_size = tcg_const_i32(8);
tcg_gen_helper_0_4(helper_st_asi, addr, cpu_tmp64, r_asi, r_size);
static inline void gen_stda_asi(TCGv hi, TCGv addr, int insn, int rd)
{
- TCGv r_temp, r_asi, r_size;
+ TCGv r_asi, r_size;
- r_temp = tcg_temp_new(TCG_TYPE_TL);
- gen_movl_reg_TN(rd + 1, r_temp);
- tcg_gen_helper_1_2(helper_pack64, cpu_tmp64, hi, r_temp);
- tcg_temp_free(r_temp);
+ gen_movl_reg_TN(rd + 1, cpu_tmp0);
+ tcg_gen_concat_tl_i64(cpu_tmp64, cpu_tmp0, hi);
r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
r_size = tcg_const_i32(8);
tcg_gen_helper_0_4(helper_st_asi, addr, cpu_tmp64, r_asi, r_size);
cond = GET_FIELD(insn, 3, 6);
if (cond == 0x8) {
save_state(dc, cpu_cond);
- tcg_gen_helper_0_1(helper_trap, cpu_dst);
+ if ((dc->def->features & CPU_FEATURE_HYPV) &&
+ supervisor(dc))
+ tcg_gen_andi_tl(cpu_dst, cpu_dst, UA2005_HTRAP_MASK);
+ else
+ tcg_gen_andi_tl(cpu_dst, cpu_dst, V8_TRAP_MASK);
+ tcg_gen_addi_tl(cpu_dst, cpu_dst, TT_TRAP);
+ tcg_gen_helper_0_1(raise_exception, cpu_dst);
} else if (cond != 0) {
TCGv r_cond = tcg_temp_new(TCG_TYPE_TL);
+ int l1;
#ifdef TARGET_SPARC64
/* V9 icc/xcc */
int cc = GET_FIELD_SP(insn, 11, 12);
save_state(dc, cpu_cond);
gen_cond(r_cond, 0, cond);
#endif
- tcg_gen_helper_0_2(helper_trapcc, cpu_dst, r_cond);
+ l1 = gen_new_label();
+ tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
+
+ if ((dc->def->features & CPU_FEATURE_HYPV) &&
+ supervisor(dc))
+ tcg_gen_andi_tl(cpu_dst, cpu_dst, UA2005_HTRAP_MASK);
+ else
+ tcg_gen_andi_tl(cpu_dst, cpu_dst, V8_TRAP_MASK);
+ tcg_gen_addi_tl(cpu_dst, cpu_dst, TT_TRAP);
+ tcg_gen_helper_0_1(raise_exception, cpu_dst);
+
+ gen_set_label(l1);
tcg_temp_free(r_cond);
}
gen_op_next_insn();
goto jmp_insn;
gen_movl_TN_reg(rd, cpu_gsr);
break;
+ case 0x16: /* Softint */
+ tcg_gen_ext_i32_tl(cpu_dst, cpu_softint);
+ gen_movl_TN_reg(rd, cpu_dst);
+ break;
case 0x17: /* Tick compare */
gen_movl_TN_reg(rd, cpu_tick_cmpr);
break;
case 0x12: /* Dispatch Control */
case 0x14: /* Softint set, WO */
case 0x15: /* Softint clear, WO */
- case 0x16: /* Softint write */
#endif
default:
goto illegal_insn;
r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
tcg_gen_ld_ptr(r_tsptr, cpu_env,
offsetof(CPUState, tsptr));
- tcg_gen_ld_tl(cpu_tmp0, r_tsptr,
+ tcg_gen_ld_tl(cpu_tmp32, r_tsptr,
offsetof(trap_state, tpc));
tcg_temp_free(r_tsptr);
+ tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
}
break;
case 1: // tnpc
CHECK_IU_FEATURE(dc, HYPV);
if (!hypervisor(dc))
goto priv_insn;
- tcg_gen_ext_i32_tl(cpu_tmp0, cpu_ssr);
+ tcg_gen_mov_tl(cpu_tmp0, cpu_ssr);
break;
case 31: // ver
tcg_gen_mov_tl(cpu_tmp0, cpu_ver);
tcg_gen_helper_0_0(helper_check_ieee_exceptions);
gen_op_store_QT0_fpr(QFPREG(rd));
break;
- case 0x69:
+ case 0x69: /* fsmuld */
CHECK_FPU_FEATURE(dc, FSMULD);
- gen_op_load_fpr_FT0(rs1);
- gen_op_load_fpr_FT1(rs2);
gen_clear_float_exceptions();
- tcg_gen_helper_0_0(helper_fsmuld);
+ tcg_gen_helper_0_2(helper_fsmuld, cpu_fpr[rs1],
+ cpu_fpr[rs2]);
tcg_gen_helper_0_0(helper_check_ieee_exceptions);
gen_op_store_DT0_fpr(DFPREG(rd));
break;
tcg_gen_helper_0_0(helper_check_ieee_exceptions);
tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);
break;
- case 0xc6:
+ case 0xc6: /* fdtos */
gen_op_load_fpr_DT1(DFPREG(rs2));
gen_clear_float_exceptions();
- tcg_gen_helper_0_0(helper_fdtos);
+ tcg_gen_helper_1_0(helper_fdtos, cpu_tmp32);
tcg_gen_helper_0_0(helper_check_ieee_exceptions);
- gen_op_store_FT0_fpr(rd);
+ tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);
break;
case 0xc7: /* fqtos */
CHECK_FPU_FEATURE(dc, FLOAT128);
gen_op_load_fpr_QT1(QFPREG(rs2));
gen_clear_float_exceptions();
- tcg_gen_helper_0_0(helper_fqtos);
+ tcg_gen_helper_1_0(helper_fqtos, cpu_tmp32);
tcg_gen_helper_0_0(helper_check_ieee_exceptions);
- gen_op_store_FT0_fpr(rd);
+ tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);
break;
- case 0xc8:
- gen_op_load_fpr_FT1(rs2);
- tcg_gen_helper_0_0(helper_fitod);
+ case 0xc8: /* fitod */
+ tcg_gen_helper_0_1(helper_fitod, cpu_fpr[rs2]);
gen_op_store_DT0_fpr(DFPREG(rd));
break;
- case 0xc9:
- gen_op_load_fpr_FT1(rs2);
- tcg_gen_helper_0_0(helper_fstod);
+ case 0xc9: /* fstod */
+ tcg_gen_helper_0_1(helper_fstod, cpu_fpr[rs2]);
gen_op_store_DT0_fpr(DFPREG(rd));
break;
case 0xcb: /* fqtod */
break;
case 0xcc: /* fitoq */
CHECK_FPU_FEATURE(dc, FLOAT128);
- gen_op_load_fpr_FT1(rs2);
- tcg_gen_helper_0_0(helper_fitoq);
+ tcg_gen_helper_0_1(helper_fitoq, cpu_fpr[rs2]);
gen_op_store_QT0_fpr(QFPREG(rd));
break;
case 0xcd: /* fstoq */
CHECK_FPU_FEATURE(dc, FLOAT128);
- gen_op_load_fpr_FT1(rs2);
- tcg_gen_helper_0_0(helper_fstoq);
+ tcg_gen_helper_0_1(helper_fstoq, cpu_fpr[rs2]);
gen_op_store_QT0_fpr(QFPREG(rd));
break;
case 0xce: /* fdtoq */
tcg_gen_helper_0_0(helper_check_ieee_exceptions);
tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);
break;
- case 0xd2:
+ case 0xd2: /* fdtoi */
gen_op_load_fpr_DT1(DFPREG(rs2));
gen_clear_float_exceptions();
- tcg_gen_helper_0_0(helper_fdtoi);
+ tcg_gen_helper_1_0(helper_fdtoi, cpu_tmp32);
tcg_gen_helper_0_0(helper_check_ieee_exceptions);
- gen_op_store_FT0_fpr(rd);
+ tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);
break;
case 0xd3: /* fqtoi */
CHECK_FPU_FEATURE(dc, FLOAT128);
gen_op_load_fpr_QT1(QFPREG(rs2));
gen_clear_float_exceptions();
- tcg_gen_helper_0_0(helper_fqtoi);
+ tcg_gen_helper_1_0(helper_fqtoi, cpu_tmp32);
tcg_gen_helper_0_0(helper_check_ieee_exceptions);
- gen_op_store_FT0_fpr(rd);
+ tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);
break;
#ifdef TARGET_SPARC64
case 0x2: /* V9 fmovd */
gen_op_store_QT0_fpr(QFPREG(rd));
break;
case 0x81: /* V9 fstox */
- gen_op_load_fpr_FT1(rs2);
gen_clear_float_exceptions();
- tcg_gen_helper_0_0(helper_fstox);
+ tcg_gen_helper_0_1(helper_fstox, cpu_fpr[rs2]);
tcg_gen_helper_0_0(helper_check_ieee_exceptions);
gen_op_store_DT0_fpr(DFPREG(rd));
break;
case 0x84: /* V9 fxtos */
gen_op_load_fpr_DT1(DFPREG(rs2));
gen_clear_float_exceptions();
- tcg_gen_helper_0_0(helper_fxtos);
+ tcg_gen_helper_1_0(helper_fxtos, cpu_tmp32);
tcg_gen_helper_0_0(helper_check_ieee_exceptions);
- gen_op_store_FT0_fpr(rd);
+ tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);
break;
case 0x88: /* V9 fxtod */
gen_op_load_fpr_DT1(DFPREG(rs2));
tcg_gen_sari_i64(cpu_dst, cpu_src1, rs2 & 0x3f);
} else {
tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
- tcg_gen_ext_i32_i64(cpu_dst, cpu_dst);
+ tcg_gen_ext32s_i64(cpu_dst, cpu_dst);
tcg_gen_sari_i64(cpu_dst, cpu_dst, rs2 & 0x1f);
}
} else { /* register */
} else {
tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
- tcg_gen_ext_i32_i64(cpu_dst, cpu_dst);
+ tcg_gen_ext32s_i64(cpu_dst, cpu_dst);
tcg_gen_sar_i64(cpu_dst, cpu_dst, cpu_tmp0);
}
}
{
switch(rd) {
case 0: /* wry */
- tcg_gen_xor_tl(cpu_y, cpu_src1, cpu_src2);
+ tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
+ tcg_gen_andi_tl(cpu_y, cpu_tmp0, 0xffffffff);
break;
#ifndef TARGET_SPARC64
case 0x01 ... 0x0f: /* undefined in the
goto jmp_insn;
tcg_gen_xor_tl(cpu_gsr, cpu_src1, cpu_src2);
break;
+ case 0x14: /* Softint set */
+ if (!supervisor(dc))
+ goto illegal_insn;
+ tcg_gen_xor_tl(cpu_tmp64, cpu_src1, cpu_src2);
+ tcg_gen_helper_0_1(helper_set_softint,
+ cpu_tmp64);
+ break;
+ case 0x15: /* Softint clear */
+ if (!supervisor(dc))
+ goto illegal_insn;
+ tcg_gen_xor_tl(cpu_tmp64, cpu_src1, cpu_src2);
+ tcg_gen_helper_0_1(helper_clear_softint,
+ cpu_tmp64);
+ break;
+ case 0x16: /* Softint write */
+ if (!supervisor(dc))
+ goto illegal_insn;
+ tcg_gen_xor_tl(cpu_tmp64, cpu_src1, cpu_src2);
+ tcg_gen_helper_0_1(helper_write_softint,
+ cpu_tmp64);
+ break;
case 0x17: /* Tick compare */
#if !defined(CONFIG_USER_ONLY)
if (!supervisor(dc))
case 0x11: /* Performance Instrumentation
Counter */
case 0x12: /* Dispatch Control */
- case 0x14: /* Softint set */
- case 0x15: /* Softint clear */
- case 0x16: /* Softint write */
#endif
default:
goto illegal_insn;
r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
tcg_gen_ld_ptr(r_tsptr, cpu_env,
offsetof(CPUState, tsptr));
- tcg_gen_st_i32(cpu_tmp0, r_tsptr,
+ tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
+ tcg_gen_st_i32(cpu_tmp32, r_tsptr,
offsetof(trap_state, tt));
tcg_temp_free(r_tsptr);
}
CHECK_IU_FEATURE(dc, HYPV);
if (!hypervisor(dc))
goto priv_insn;
- tcg_gen_trunc_tl_i32(cpu_ssr, cpu_tmp0);
+ tcg_gen_mov_tl(cpu_ssr, cpu_tmp0);
break;
default:
goto illegal_insn;
break;
case 0x062: /* VIS I fnor */
CHECK_FPU_FEATURE(dc, VIS1);
- gen_op_load_fpr_DT0(DFPREG(rs1));
- gen_op_load_fpr_DT1(DFPREG(rs2));
- tcg_gen_helper_0_0(helper_fnor);
- gen_op_store_DT0_fpr(DFPREG(rd));
+ tcg_gen_or_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1)],
+ cpu_fpr[DFPREG(rs2)]);
+ tcg_gen_xori_i32(cpu_fpr[DFPREG(rd)], cpu_tmp32, -1);
+ tcg_gen_or_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1) + 1],
+ cpu_fpr[DFPREG(rs2) + 1]);
+ tcg_gen_xori_i32(cpu_fpr[DFPREG(rd) + 1], cpu_tmp32, -1);
break;
case 0x063: /* VIS I fnors */
CHECK_FPU_FEATURE(dc, VIS1);
break;
case 0x064: /* VIS I fandnot2 */
CHECK_FPU_FEATURE(dc, VIS1);
- gen_op_load_fpr_DT1(DFPREG(rs1));
- gen_op_load_fpr_DT0(DFPREG(rs2));
- tcg_gen_helper_0_0(helper_fandnot);
- gen_op_store_DT0_fpr(DFPREG(rd));
+ tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1)], -1);
+ tcg_gen_and_i32(cpu_fpr[DFPREG(rd)], cpu_tmp32,
+ cpu_fpr[DFPREG(rs2)]);
+ tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1) + 1], -1);
+ tcg_gen_and_i32(cpu_fpr[DFPREG(rd) + 1], cpu_tmp32,
+ cpu_fpr[DFPREG(rs2) + 1]);
break;
case 0x065: /* VIS I fandnot2s */
CHECK_FPU_FEATURE(dc, VIS1);
break;
case 0x066: /* VIS I fnot2 */
CHECK_FPU_FEATURE(dc, VIS1);
- gen_op_load_fpr_DT1(DFPREG(rs2));
- tcg_gen_helper_0_0(helper_fnot);
- gen_op_store_DT0_fpr(DFPREG(rd));
+ tcg_gen_xori_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs2)],
+ -1);
+ tcg_gen_xori_i32(cpu_fpr[DFPREG(rd) + 1],
+ cpu_fpr[DFPREG(rs2) + 1], -1);
break;
case 0x067: /* VIS I fnot2s */
CHECK_FPU_FEATURE(dc, VIS1);
break;
case 0x068: /* VIS I fandnot1 */
CHECK_FPU_FEATURE(dc, VIS1);
- gen_op_load_fpr_DT0(DFPREG(rs1));
- gen_op_load_fpr_DT1(DFPREG(rs2));
- tcg_gen_helper_0_0(helper_fandnot);
- gen_op_store_DT0_fpr(DFPREG(rd));
+ tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[DFPREG(rs2)], -1);
+ tcg_gen_and_i32(cpu_fpr[DFPREG(rd)], cpu_tmp32,
+ cpu_fpr[DFPREG(rs1)]);
+ tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[DFPREG(rs2)], -1);
+ tcg_gen_and_i32(cpu_fpr[DFPREG(rd) + 1], cpu_tmp32,
+ cpu_fpr[DFPREG(rs1) + 1]);
break;
case 0x069: /* VIS I fandnot1s */
CHECK_FPU_FEATURE(dc, VIS1);
break;
case 0x06a: /* VIS I fnot1 */
CHECK_FPU_FEATURE(dc, VIS1);
- gen_op_load_fpr_DT1(DFPREG(rs1));
- tcg_gen_helper_0_0(helper_fnot);
- gen_op_store_DT0_fpr(DFPREG(rd));
+ tcg_gen_xori_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs1)],
+ -1);
+ tcg_gen_xori_i32(cpu_fpr[DFPREG(rd) + 1],
+ cpu_fpr[DFPREG(rs1) + 1], -1);
break;
case 0x06b: /* VIS I fnot1s */
CHECK_FPU_FEATURE(dc, VIS1);
break;
case 0x06c: /* VIS I fxor */
CHECK_FPU_FEATURE(dc, VIS1);
- gen_op_load_fpr_DT0(DFPREG(rs1));
- gen_op_load_fpr_DT1(DFPREG(rs2));
- tcg_gen_helper_0_0(helper_fxor);
- gen_op_store_DT0_fpr(DFPREG(rd));
+ tcg_gen_xor_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs1)],
+ cpu_fpr[DFPREG(rs2)]);
+ tcg_gen_xor_i32(cpu_fpr[DFPREG(rd) + 1],
+ cpu_fpr[DFPREG(rs1) + 1],
+ cpu_fpr[DFPREG(rs2) + 1]);
break;
case 0x06d: /* VIS I fxors */
CHECK_FPU_FEATURE(dc, VIS1);
break;
case 0x06e: /* VIS I fnand */
CHECK_FPU_FEATURE(dc, VIS1);
- gen_op_load_fpr_DT0(DFPREG(rs1));
- gen_op_load_fpr_DT1(DFPREG(rs2));
- tcg_gen_helper_0_0(helper_fnand);
- gen_op_store_DT0_fpr(DFPREG(rd));
+ tcg_gen_and_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1)],
+ cpu_fpr[DFPREG(rs2)]);
+ tcg_gen_xori_i32(cpu_fpr[DFPREG(rd)], cpu_tmp32, -1);
+ tcg_gen_and_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1) + 1],
+ cpu_fpr[DFPREG(rs2) + 1]);
+ tcg_gen_xori_i32(cpu_fpr[DFPREG(rd) + 1], cpu_tmp32, -1);
break;
case 0x06f: /* VIS I fnands */
CHECK_FPU_FEATURE(dc, VIS1);
break;
case 0x070: /* VIS I fand */
CHECK_FPU_FEATURE(dc, VIS1);
- gen_op_load_fpr_DT0(DFPREG(rs1));
- gen_op_load_fpr_DT1(DFPREG(rs2));
- tcg_gen_helper_0_0(helper_fand);
- gen_op_store_DT0_fpr(DFPREG(rd));
+ tcg_gen_and_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs1)],
+ cpu_fpr[DFPREG(rs2)]);
+ tcg_gen_and_i32(cpu_fpr[DFPREG(rd) + 1],
+ cpu_fpr[DFPREG(rs1) + 1],
+ cpu_fpr[DFPREG(rs2) + 1]);
break;
case 0x071: /* VIS I fands */
CHECK_FPU_FEATURE(dc, VIS1);
break;
case 0x072: /* VIS I fxnor */
CHECK_FPU_FEATURE(dc, VIS1);
- gen_op_load_fpr_DT0(DFPREG(rs1));
- gen_op_load_fpr_DT1(DFPREG(rs2));
- tcg_gen_helper_0_0(helper_fxnor);
- gen_op_store_DT0_fpr(DFPREG(rd));
+ tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[DFPREG(rs2)], -1);
+ tcg_gen_xor_i32(cpu_fpr[DFPREG(rd)], cpu_tmp32,
+ cpu_fpr[DFPREG(rs1)]);
+ tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[DFPREG(rs2) + 1], -1);
+ tcg_gen_xor_i32(cpu_fpr[DFPREG(rd) + 1], cpu_tmp32,
+ cpu_fpr[DFPREG(rs1) + 1]);
break;
case 0x073: /* VIS I fxnors */
CHECK_FPU_FEATURE(dc, VIS1);
break;
case 0x076: /* VIS I fornot2 */
CHECK_FPU_FEATURE(dc, VIS1);
- gen_op_load_fpr_DT1(DFPREG(rs1));
- gen_op_load_fpr_DT0(DFPREG(rs2));
- tcg_gen_helper_0_0(helper_fornot);
- gen_op_store_DT0_fpr(DFPREG(rd));
+ tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1)], -1);
+ tcg_gen_or_i32(cpu_fpr[DFPREG(rd)], cpu_tmp32,
+ cpu_fpr[DFPREG(rs2)]);
+ tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1) + 1], -1);
+ tcg_gen_or_i32(cpu_fpr[DFPREG(rd) + 1], cpu_tmp32,
+ cpu_fpr[DFPREG(rs2) + 1]);
break;
case 0x077: /* VIS I fornot2s */
CHECK_FPU_FEATURE(dc, VIS1);
break;
case 0x07a: /* VIS I fornot1 */
CHECK_FPU_FEATURE(dc, VIS1);
- gen_op_load_fpr_DT0(DFPREG(rs1));
- gen_op_load_fpr_DT1(DFPREG(rs2));
- tcg_gen_helper_0_0(helper_fornot);
- gen_op_store_DT0_fpr(DFPREG(rd));
+ tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[DFPREG(rs2)], -1);
+ tcg_gen_or_i32(cpu_fpr[DFPREG(rd)], cpu_tmp32,
+ cpu_fpr[DFPREG(rs1)]);
+ tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[DFPREG(rs2) + 1], -1);
+ tcg_gen_or_i32(cpu_fpr[DFPREG(rd) + 1], cpu_tmp32,
+ cpu_fpr[DFPREG(rs1) + 1]);
break;
case 0x07b: /* VIS I fornot1s */
CHECK_FPU_FEATURE(dc, VIS1);
break;
case 0x07c: /* VIS I for */
CHECK_FPU_FEATURE(dc, VIS1);
- gen_op_load_fpr_DT0(DFPREG(rs1));
- gen_op_load_fpr_DT1(DFPREG(rs2));
- tcg_gen_helper_0_0(helper_for);
- gen_op_store_DT0_fpr(DFPREG(rd));
+ tcg_gen_or_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs1)],
+ cpu_fpr[DFPREG(rs2)]);
+ tcg_gen_or_i32(cpu_fpr[DFPREG(rd) + 1],
+ cpu_fpr[DFPREG(rs1) + 1],
+ cpu_fpr[DFPREG(rs2) + 1]);
break;
case 0x07d: /* VIS I fors */
CHECK_FPU_FEATURE(dc, VIS1);
CHECK_IU_FEATURE(dc, SWAP);
gen_movl_reg_TN(rd, cpu_val);
gen_address_mask(dc, cpu_addr);
- tcg_gen_qemu_ld32u(cpu_tmp32, cpu_addr, dc->mem_idx);
+ tcg_gen_qemu_ld32u(cpu_tmp0, cpu_addr, dc->mem_idx);
tcg_gen_qemu_st32(cpu_val, cpu_addr, dc->mem_idx);
- tcg_gen_extu_i32_tl(cpu_val, cpu_tmp32);
+ tcg_gen_mov_tl(cpu_val, cpu_tmp0);
break;
#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
case 0x10: /* load word alternate */
switch (xop) {
case 0x20: /* load fpreg */
gen_address_mask(dc, cpu_addr);
- tcg_gen_qemu_ld32u(cpu_fpr[rd], cpu_addr, dc->mem_idx);
+ tcg_gen_qemu_ld32u(cpu_tmp0, cpu_addr, dc->mem_idx);
+ tcg_gen_trunc_tl_i32(cpu_fpr[rd], cpu_tmp0);
break;
case 0x21: /* ldfsr, V9 ldxfsr */
#ifdef TARGET_SPARC64
if (rd & 1)
goto illegal_insn;
else {
- TCGv r_low, r_const;
+ TCGv r_const;
save_state(dc, cpu_cond);
gen_address_mask(dc, cpu_addr);
tcg_gen_helper_0_2(helper_check_align, cpu_addr,
r_const); // XXX remove
tcg_temp_free(r_const);
- r_low = tcg_temp_new(TCG_TYPE_TL);
- gen_movl_reg_TN(rd + 1, r_low);
- tcg_gen_helper_1_2(helper_pack64, cpu_tmp64, cpu_val,
- r_low);
- tcg_temp_free(r_low);
+ gen_movl_reg_TN(rd + 1, cpu_tmp0);
+ tcg_gen_concat_tl_i64(cpu_tmp64, cpu_tmp0, cpu_val);
tcg_gen_qemu_st64(cpu_tmp64, cpu_addr, dc->mem_idx);
}
break;
switch (xop) {
case 0x24: /* store fpreg */
gen_address_mask(dc, cpu_addr);
- tcg_gen_qemu_st32(cpu_fpr[rd], cpu_addr, dc->mem_idx);
+ tcg_gen_ext_i32_tl(cpu_tmp0, cpu_fpr[rd]);
+ tcg_gen_qemu_st32(cpu_tmp0, cpu_addr, dc->mem_idx);
break;
case 0x25: /* stfsr, V9 stxfsr */
#ifdef TARGET_SPARC64
tcg_gen_ld_i64(cpu_tmp64, cpu_env, offsetof(CPUState, fsr));
if (rd == 1)
tcg_gen_qemu_st64(cpu_tmp64, cpu_addr, dc->mem_idx);
- else {
- tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp64);
- tcg_gen_qemu_st32(cpu_tmp32, cpu_addr, dc->mem_idx);
- }
+ else
+ tcg_gen_qemu_st32(cpu_tmp64, cpu_addr, dc->mem_idx);
#else
tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUState, fsr));
tcg_gen_qemu_st32(cpu_tmp32, cpu_addr, dc->mem_idx);
offsetof(CPUState, ssr), "ssr");
cpu_ver = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
offsetof(CPUState, version), "ver");
+ cpu_softint = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
+ offsetof(CPUState, softint),
+ "softint");
#else
cpu_wim = tcg_global_mem_new(TCG_TYPE_I32,
TCG_AREG0, offsetof(CPUState, wim),
projects / qemu / blobdiff