Fix a warning in sparc64-linux-user build

[qemu] / target-sparc / translate.c

diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index 77fb723..86319a7 100644 (file)
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.c
@@ -16,7 +16,7 @@
 
    You should have received a copy of the GNU Lesser General Public
    License along with this library; if not, write to the Free Software
-   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+   Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA  02110-1301 USA
  */
 
 #include <stdarg.h>
@@ -92,11 +92,9 @@ typedef struct DisasContext {
 #define GET_FIELD_SPs(x,a,b) sign_extend (GET_FIELD_SP(x,a,b), ((b) - (a) + 1))
 
 #ifdef TARGET_SPARC64
-#define FFPREG(r) (r)
 #define DFPREG(r) (((r & 1) << 5) | (r & 0x1e))
 #define QFPREG(r) (((r & 1) << 5) | (r & 0x1c))
 #else
-#define FFPREG(r) (r)
 #define DFPREG(r) (r & 0x1e)
 #define QFPREG(r) (r & 0x1c)
 #endif
@@ -1933,7 +1931,7 @@ static void disas_sparc_insn(DisasContext * dc)
 {
     unsigned int insn, opc, rs1, rs2, rd;
 
-    if (unlikely(loglevel & CPU_LOG_TB_OP))
+    if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP)))
         tcg_gen_debug_insn_start(dc->pc);
     insn = ldl_code(dc->pc);
     opc = GET_FIELD(insn, 0, 1);
@@ -2846,24 +2844,6 @@ static void disas_sparc_insn(DisasContext * dc)
 #undef FMOVSCC
 #undef FMOVDCC
 #undef FMOVQCC
-#define FMOVCC(size_FDQ, icc)                                           \
-                    {                                                   \
-                        TCGv r_cond;                                    \
-                        int l1;                                         \
-                                                                        \
-                        l1 = gen_new_label();                           \
-                        r_cond = tcg_temp_new();             \
-                        cond = GET_FIELD_SP(insn, 14, 17);              \
-                        gen_cond(r_cond, icc, cond);                    \
-                        tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond,         \
-                                           0, l1);                      \
-                        glue(glue(gen_op_load_fpr_, size_FDQ), T0)      \
-                            (glue(size_FDQ, FPREG(rs2)));               \
-                        glue(glue(gen_op_store_, size_FDQ), T0_fpr)     \
-                            (glue(size_FDQ, FPREG(rd)));                \
-                        gen_set_label(l1);                              \
-                        tcg_temp_free(r_cond);                          \
-                    }
 #define FMOVSCC(icc)                                                    \
                     {                                                   \
                         TCGv r_cond;                                    \
@@ -4778,6 +4758,7 @@ static inline void gen_intermediate_code_internal(TranslationBlock * tb,
     target_ulong pc_start, last_pc;
     uint16_t *gen_opc_end;
     DisasContext dc1, *dc = &dc1;
+    CPUBreakpoint *bp;
     int j, lj = -1;
     int num_insns;
     int max_insns;
@@ -4815,9 +4796,9 @@ static inline void gen_intermediate_code_internal(TranslationBlock * tb,
         max_insns = CF_COUNT_MASK;
     gen_icount_start();
     do {
-        if (env->nb_breakpoints > 0) {
-            for(j = 0; j < env->nb_breakpoints; j++) {
-                if (env->breakpoints[j] == dc->pc) {
+        if (unlikely(!TAILQ_EMPTY(&env->breakpoints))) {
+            TAILQ_FOREACH(bp, &env->breakpoints, entry) {
+                if (bp->pc == dc->pc) {
                     if (dc->pc != pc_start)
                         save_state(dc, cpu_cond);
                     gen_helper_debug();
@@ -4828,8 +4809,7 @@ static inline void gen_intermediate_code_internal(TranslationBlock * tb,
             }
         }
         if (spc) {
-            if (loglevel > 0)
-                fprintf(logfile, "Search PC...\n");
+            qemu_log("Search PC...\n");
             j = gen_opc_ptr - gen_opc_buf;
             if (lj < j) {
                 lj++;
@@ -4858,7 +4838,7 @@ static inline void gen_intermediate_code_internal(TranslationBlock * tb,
             break;
         /* if single step mode, we generate only one instruction and
            generate an exception */
-        if (env->singlestep_enabled) {
+        if (env->singlestep_enabled || singlestep) {
             tcg_gen_movi_tl(cpu_pc, dc->pc);
             tcg_gen_exit_tb(0);
             break;
@@ -4896,9 +4876,7 @@ static inline void gen_intermediate_code_internal(TranslationBlock * tb,
         while (lj <= j)
             gen_opc_instr_start[lj++] = 0;
 #if 0
-        if (loglevel > 0) {
-            page_dump(logfile);
-        }
+        log_page_dump();
 #endif
         gen_opc_jump_pc[0] = dc->jump_pc[0];
         gen_opc_jump_pc[1] = dc->jump_pc[1];
@@ -4907,11 +4885,11 @@ static inline void gen_intermediate_code_internal(TranslationBlock * tb,
         tb->icount = num_insns;
     }
 #ifdef DEBUG_DISAS
-    if (loglevel & CPU_LOG_TB_IN_ASM) {
-        fprintf(logfile, "--------------\n");
-        fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
-        target_disas(logfile, pc_start, last_pc + 4 - pc_start, 0);
-        fprintf(logfile, "\n");
+    if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
+        qemu_log("--------------\n");
+        qemu_log("IN: %s\n", lookup_symbol(pc_start));
+        log_target_disas(pc_start, last_pc + 4 - pc_start, 0);
+        qemu_log("\n");
     }
 #endif
 }