You should have received a copy of the GNU Lesser General Public
License along with this library; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
*/
#include <stdarg.h>
/* global register indexes */
static TCGv_ptr cpu_env, cpu_regwptr;
-static TCGv cpu_cc_src, cpu_cc_src2, cpu_cc_dst;
+static TCGv cpu_cc_src, cpu_cc_src2, cpu_cc_dst, cpu_cc_op;
static TCGv_i32 cpu_psr;
static TCGv cpu_fsr, cpu_pc, cpu_npc, cpu_gregs[8];
static TCGv cpu_y;
int mem_idx;
int fpu_enabled;
int address_mask_32bit;
+ uint32_t cc_op; /* current CC operation */
struct TranslationBlock *tb;
sparc_def_t *def;
} DisasContext;
// This function uses non-native bit order
-#define GET_FIELD(X, FROM, TO) \
- ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1))
+#define GET_FIELD(X, FROM, TO) \
+ ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1))
// This function uses the order in the manuals, i.e. bit 0 is 2^0
-#define GET_FIELD_SP(X, FROM, TO) \
+#define GET_FIELD_SP(X, FROM, TO) \
GET_FIELD(X, 31 - (TO), 31 - (FROM))
#define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1)
#define GET_FIELD_SPs(x,a,b) sign_extend (GET_FIELD_SP(x,a,b), ((b) - (a) + 1))
#ifdef TARGET_SPARC64
-#define FFPREG(r) (r)
#define DFPREG(r) (((r & 1) << 5) | (r & 0x1e))
#define QFPREG(r) (((r & 1) << 5) | (r & 0x1c))
#else
-#define FFPREG(r) (r)
#define DFPREG(r) (r & 0x1e)
#define QFPREG(r) (r & 0x1c)
#endif
gen_set_label(l1);
}
+static inline void gen_op_addi_cc(TCGv dst, TCGv src1, target_long src2)
+{
+ tcg_gen_mov_tl(cpu_cc_src, src1);
+ tcg_gen_movi_tl(cpu_cc_src2, src2);
+ tcg_gen_addi_tl(cpu_cc_dst, cpu_cc_src, src2);
+ tcg_gen_mov_tl(dst, cpu_cc_dst);
+}
+
static inline void gen_op_add_cc(TCGv dst, TCGv src1, TCGv src2)
{
tcg_gen_mov_tl(cpu_cc_src, src1);
tcg_gen_mov_tl(cpu_cc_src2, src2);
tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
- gen_cc_clear_icc();
- gen_cc_NZ_icc(cpu_cc_dst);
- gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
- gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
-#ifdef TARGET_SPARC64
- gen_cc_clear_xcc();
- gen_cc_NZ_xcc(cpu_cc_dst);
- gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
- gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
-#endif
+ tcg_gen_mov_tl(dst, cpu_cc_dst);
+}
+
+static inline void gen_op_addxi_cc(TCGv dst, TCGv src1, target_long src2)
+{
+ tcg_gen_mov_tl(cpu_cc_src, src1);
+ tcg_gen_movi_tl(cpu_cc_src2, src2);
+ gen_mov_reg_C(cpu_tmp0, cpu_psr);
+ tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_tmp0);
+ tcg_gen_addi_tl(cpu_cc_dst, cpu_cc_dst, src2);
tcg_gen_mov_tl(dst, cpu_cc_dst);
}
tcg_gen_mov_tl(cpu_cc_src2, src2);
gen_mov_reg_C(cpu_tmp0, cpu_psr);
tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_tmp0);
- gen_cc_clear_icc();
- gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
-#ifdef TARGET_SPARC64
- gen_cc_clear_xcc();
- gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
-#endif
tcg_gen_add_tl(cpu_cc_dst, cpu_cc_dst, cpu_cc_src2);
- gen_cc_NZ_icc(cpu_cc_dst);
- gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
- gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
-#ifdef TARGET_SPARC64
- gen_cc_NZ_xcc(cpu_cc_dst);
- gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
- gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
-#endif
tcg_gen_mov_tl(dst, cpu_cc_dst);
}
tcg_temp_free(r_temp);
}
+static inline void gen_op_subi_cc(TCGv dst, TCGv src1, target_long src2, DisasContext *dc)
+{
+ tcg_gen_mov_tl(cpu_cc_src, src1);
+ tcg_gen_movi_tl(cpu_cc_src2, src2);
+ if (src2 == 0) {
+ tcg_gen_mov_tl(cpu_cc_dst, src1);
+ tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
+ dc->cc_op = CC_OP_LOGIC;
+ } else {
+ tcg_gen_subi_tl(cpu_cc_dst, cpu_cc_src, src2);
+ tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUB);
+ dc->cc_op = CC_OP_SUB;
+ }
+ tcg_gen_mov_tl(dst, cpu_cc_dst);
+}
+
static inline void gen_op_sub_cc(TCGv dst, TCGv src1, TCGv src2)
{
tcg_gen_mov_tl(cpu_cc_src, src1);
tcg_gen_mov_tl(cpu_cc_src2, src2);
tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
- gen_cc_clear_icc();
- gen_cc_NZ_icc(cpu_cc_dst);
- gen_cc_C_sub_icc(cpu_cc_src, cpu_cc_src2);
- gen_cc_V_sub_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
-#ifdef TARGET_SPARC64
- gen_cc_clear_xcc();
- gen_cc_NZ_xcc(cpu_cc_dst);
- gen_cc_C_sub_xcc(cpu_cc_src, cpu_cc_src2);
- gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
-#endif
+ tcg_gen_mov_tl(dst, cpu_cc_dst);
+}
+
+static inline void gen_op_subxi_cc(TCGv dst, TCGv src1, target_long src2)
+{
+ tcg_gen_mov_tl(cpu_cc_src, src1);
+ tcg_gen_movi_tl(cpu_cc_src2, src2);
+ gen_mov_reg_C(cpu_tmp0, cpu_psr);
+ tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_tmp0);
+ tcg_gen_subi_tl(cpu_cc_dst, cpu_cc_dst, src2);
tcg_gen_mov_tl(dst, cpu_cc_dst);
}
tcg_gen_mov_tl(cpu_cc_src2, src2);
gen_mov_reg_C(cpu_tmp0, cpu_psr);
tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_tmp0);
- gen_cc_clear_icc();
- gen_cc_C_sub_icc(cpu_cc_dst, cpu_cc_src);
-#ifdef TARGET_SPARC64
- gen_cc_clear_xcc();
- gen_cc_C_sub_xcc(cpu_cc_dst, cpu_cc_src);
-#endif
tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_dst, cpu_cc_src2);
- gen_cc_NZ_icc(cpu_cc_dst);
- gen_cc_C_sub_icc(cpu_cc_dst, cpu_cc_src);
- gen_cc_V_sub_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
-#ifdef TARGET_SPARC64
- gen_cc_NZ_xcc(cpu_cc_dst);
- gen_cc_C_sub_xcc(cpu_cc_dst, cpu_cc_src);
- gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
-#endif
tcg_gen_mov_tl(dst, cpu_cc_dst);
}
gen_set_label(l1);
}
-static inline void gen_op_logic_cc(TCGv dst)
-{
- tcg_gen_mov_tl(cpu_cc_dst, dst);
-
- gen_cc_clear_icc();
- gen_cc_NZ_icc(cpu_cc_dst);
-#ifdef TARGET_SPARC64
- gen_cc_clear_xcc();
- gen_cc_NZ_xcc(cpu_cc_dst);
-#endif
-}
-
// 1
static inline void gen_op_eval_ba(TCGv dst)
{
tcg_gen_addi_tl(cpu_npc, cpu_npc, 4);
}
-static inline void gen_cond(TCGv r_dst, unsigned int cc, unsigned int cond)
+static inline void gen_cond(TCGv r_dst, unsigned int cc, unsigned int cond,
+ DisasContext *dc)
{
TCGv_i32 r_src;
#else
r_src = cpu_psr;
#endif
+ switch (dc->cc_op) {
+ case CC_OP_FLAGS:
+ break;
+ default:
+ gen_helper_compute_psr();
+ dc->cc_op = CC_OP_FLAGS;
+ break;
+ }
switch (cond) {
case 0x0:
gen_op_eval_bn(r_dst);
}
} else {
flush_cond(dc, r_cond);
- gen_cond(r_cond, cc, cond);
+ gen_cond(r_cond, cc, cond, dc);
if (a) {
gen_branch_a(dc, target, dc->npc, r_cond);
dc->is_br = 1;
static inline TCGv get_src2(unsigned int insn, TCGv def)
{
TCGv r_rs2 = def;
- unsigned int rs2;
if (IS_IMM) { /* immediate */
- rs2 = GET_FIELDs(insn, 19, 31);
- r_rs2 = tcg_const_tl((int)rs2); // XXX how to free?
+ target_long simm;
+
+ simm = GET_FIELDs(insn, 19, 31);
+ r_rs2 = tcg_const_tl(simm); // XXX how to free?
} else { /* register */
+ unsigned int rs2;
+
rs2 = GET_FIELD(insn, 27, 31);
if (rs2 == 0)
r_rs2 = tcg_const_tl(0); // XXX how to free?
static void disas_sparc_insn(DisasContext * dc)
{
unsigned int insn, opc, rs1, rs2, rd;
+ target_long simm;
- if (unlikely(loglevel & CPU_LOG_TB_OP))
+ if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP)))
tcg_gen_debug_insn_start(dc->pc);
insn = ldl_code(dc->pc);
opc = GET_FIELD(insn, 0, 1);
break;
}
break;
- case 1:
- /*CALL*/ {
+ case 1: /*CALL*/
+ {
target_long target = GET_FIELDs(insn, 2, 31) << 2;
TCGv r_const;
save_state(dc, cpu_cond);
if (cc == 0)
- gen_cond(r_cond, 0, cond);
+ gen_cond(r_cond, 0, cond, dc);
else if (cc == 2)
- gen_cond(r_cond, 1, cond);
+ gen_cond(r_cond, 1, cond, dc);
else
goto illegal_insn;
#else
save_state(dc, cpu_cond);
- gen_cond(r_cond, 0, cond);
+ gen_cond(r_cond, 0, cond, dc);
#endif
l1 = gen_new_label();
tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
break;
#ifdef TARGET_SPARC64
case 0x2: /* V9 rdccr */
+ gen_helper_compute_psr();
gen_helper_rdccr(cpu_dst);
gen_movl_TN_reg(rd, cpu_dst);
break;
#ifndef TARGET_SPARC64
if (!supervisor(dc))
goto priv_insn;
+ gen_helper_compute_psr();
+ dc->cc_op = CC_OP_FLAGS;
gen_helper_rdpsr(cpu_dst);
#else
CHECK_IU_FEATURE(dc, HYPV);
rs2 = GET_FIELD(insn, 27, 31);
xop = GET_FIELD(insn, 18, 26);
switch (xop) {
- case 0x1: /* fmovs */
- tcg_gen_mov_i32(cpu_fpr[rd], cpu_fpr[rs2]);
- break;
- case 0x5: /* fnegs */
- gen_helper_fnegs(cpu_fpr[rd], cpu_fpr[rs2]);
- break;
- case 0x9: /* fabss */
- gen_helper_fabss(cpu_fpr[rd], cpu_fpr[rs2]);
- break;
- case 0x29: /* fsqrts */
- CHECK_FPU_FEATURE(dc, FSQRT);
- gen_clear_float_exceptions();
- gen_helper_fsqrts(cpu_tmp32, cpu_fpr[rs2]);
- gen_helper_check_ieee_exceptions();
- tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);
- break;
- case 0x2a: /* fsqrtd */
- CHECK_FPU_FEATURE(dc, FSQRT);
- gen_op_load_fpr_DT1(DFPREG(rs2));
- gen_clear_float_exceptions();
- gen_helper_fsqrtd();
- gen_helper_check_ieee_exceptions();
- gen_op_store_DT0_fpr(DFPREG(rd));
- break;
- case 0x2b: /* fsqrtq */
- CHECK_FPU_FEATURE(dc, FLOAT128);
- gen_op_load_fpr_QT1(QFPREG(rs2));
- gen_clear_float_exceptions();
- gen_helper_fsqrtq();
- gen_helper_check_ieee_exceptions();
- gen_op_store_QT0_fpr(QFPREG(rd));
- break;
- case 0x41: /* fadds */
- gen_clear_float_exceptions();
- gen_helper_fadds(cpu_tmp32,
- cpu_fpr[rs1], cpu_fpr[rs2]);
- gen_helper_check_ieee_exceptions();
- tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);
- break;
- case 0x42:
- gen_op_load_fpr_DT0(DFPREG(rs1));
- gen_op_load_fpr_DT1(DFPREG(rs2));
- gen_clear_float_exceptions();
- gen_helper_faddd();
- gen_helper_check_ieee_exceptions();
- gen_op_store_DT0_fpr(DFPREG(rd));
- break;
- case 0x43: /* faddq */
- CHECK_FPU_FEATURE(dc, FLOAT128);
- gen_op_load_fpr_QT0(QFPREG(rs1));
- gen_op_load_fpr_QT1(QFPREG(rs2));
- gen_clear_float_exceptions();
- gen_helper_faddq();
- gen_helper_check_ieee_exceptions();
- gen_op_store_QT0_fpr(QFPREG(rd));
- break;
- case 0x45: /* fsubs */
- gen_clear_float_exceptions();
- gen_helper_fsubs(cpu_tmp32,
- cpu_fpr[rs1], cpu_fpr[rs2]);
- gen_helper_check_ieee_exceptions();
- tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);
- break;
- case 0x46:
- gen_op_load_fpr_DT0(DFPREG(rs1));
- gen_op_load_fpr_DT1(DFPREG(rs2));
- gen_clear_float_exceptions();
- gen_helper_fsubd();
- gen_helper_check_ieee_exceptions();
- gen_op_store_DT0_fpr(DFPREG(rd));
- break;
- case 0x47: /* fsubq */
- CHECK_FPU_FEATURE(dc, FLOAT128);
- gen_op_load_fpr_QT0(QFPREG(rs1));
- gen_op_load_fpr_QT1(QFPREG(rs2));
- gen_clear_float_exceptions();
- gen_helper_fsubq();
- gen_helper_check_ieee_exceptions();
- gen_op_store_QT0_fpr(QFPREG(rd));
- break;
- case 0x49: /* fmuls */
- CHECK_FPU_FEATURE(dc, FMUL);
- gen_clear_float_exceptions();
- gen_helper_fmuls(cpu_tmp32,
- cpu_fpr[rs1], cpu_fpr[rs2]);
- gen_helper_check_ieee_exceptions();
- tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);
- break;
- case 0x4a: /* fmuld */
- CHECK_FPU_FEATURE(dc, FMUL);
- gen_op_load_fpr_DT0(DFPREG(rs1));
- gen_op_load_fpr_DT1(DFPREG(rs2));
- gen_clear_float_exceptions();
- gen_helper_fmuld();
- gen_helper_check_ieee_exceptions();
- gen_op_store_DT0_fpr(DFPREG(rd));
- break;
- case 0x4b: /* fmulq */
- CHECK_FPU_FEATURE(dc, FLOAT128);
- CHECK_FPU_FEATURE(dc, FMUL);
- gen_op_load_fpr_QT0(QFPREG(rs1));
- gen_op_load_fpr_QT1(QFPREG(rs2));
- gen_clear_float_exceptions();
- gen_helper_fmulq();
- gen_helper_check_ieee_exceptions();
- gen_op_store_QT0_fpr(QFPREG(rd));
- break;
- case 0x4d: /* fdivs */
- gen_clear_float_exceptions();
- gen_helper_fdivs(cpu_tmp32,
- cpu_fpr[rs1], cpu_fpr[rs2]);
- gen_helper_check_ieee_exceptions();
- tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);
- break;
- case 0x4e:
- gen_op_load_fpr_DT0(DFPREG(rs1));
- gen_op_load_fpr_DT1(DFPREG(rs2));
- gen_clear_float_exceptions();
- gen_helper_fdivd();
- gen_helper_check_ieee_exceptions();
- gen_op_store_DT0_fpr(DFPREG(rd));
- break;
- case 0x4f: /* fdivq */
- CHECK_FPU_FEATURE(dc, FLOAT128);
- gen_op_load_fpr_QT0(QFPREG(rs1));
- gen_op_load_fpr_QT1(QFPREG(rs2));
- gen_clear_float_exceptions();
- gen_helper_fdivq();
- gen_helper_check_ieee_exceptions();
- gen_op_store_QT0_fpr(QFPREG(rd));
- break;
- case 0x69: /* fsmuld */
- CHECK_FPU_FEATURE(dc, FSMULD);
- gen_clear_float_exceptions();
- gen_helper_fsmuld(cpu_fpr[rs1], cpu_fpr[rs2]);
- gen_helper_check_ieee_exceptions();
- gen_op_store_DT0_fpr(DFPREG(rd));
- break;
- case 0x6e: /* fdmulq */
- CHECK_FPU_FEATURE(dc, FLOAT128);
- gen_op_load_fpr_DT0(DFPREG(rs1));
- gen_op_load_fpr_DT1(DFPREG(rs2));
- gen_clear_float_exceptions();
- gen_helper_fdmulq();
- gen_helper_check_ieee_exceptions();
- gen_op_store_QT0_fpr(QFPREG(rd));
- break;
- case 0xc4: /* fitos */
- gen_clear_float_exceptions();
- gen_helper_fitos(cpu_tmp32, cpu_fpr[rs2]);
- gen_helper_check_ieee_exceptions();
- tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);
- break;
- case 0xc6: /* fdtos */
- gen_op_load_fpr_DT1(DFPREG(rs2));
- gen_clear_float_exceptions();
- gen_helper_fdtos(cpu_tmp32);
- gen_helper_check_ieee_exceptions();
- tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);
- break;
- case 0xc7: /* fqtos */
- CHECK_FPU_FEATURE(dc, FLOAT128);
- gen_op_load_fpr_QT1(QFPREG(rs2));
- gen_clear_float_exceptions();
- gen_helper_fqtos(cpu_tmp32);
- gen_helper_check_ieee_exceptions();
- tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);
- break;
- case 0xc8: /* fitod */
- gen_helper_fitod(cpu_fpr[rs2]);
- gen_op_store_DT0_fpr(DFPREG(rd));
- break;
- case 0xc9: /* fstod */
- gen_helper_fstod(cpu_fpr[rs2]);
- gen_op_store_DT0_fpr(DFPREG(rd));
- break;
- case 0xcb: /* fqtod */
- CHECK_FPU_FEATURE(dc, FLOAT128);
- gen_op_load_fpr_QT1(QFPREG(rs2));
- gen_clear_float_exceptions();
- gen_helper_fqtod();
- gen_helper_check_ieee_exceptions();
- gen_op_store_DT0_fpr(DFPREG(rd));
- break;
- case 0xcc: /* fitoq */
- CHECK_FPU_FEATURE(dc, FLOAT128);
- gen_helper_fitoq(cpu_fpr[rs2]);
- gen_op_store_QT0_fpr(QFPREG(rd));
- break;
- case 0xcd: /* fstoq */
- CHECK_FPU_FEATURE(dc, FLOAT128);
- gen_helper_fstoq(cpu_fpr[rs2]);
- gen_op_store_QT0_fpr(QFPREG(rd));
- break;
- case 0xce: /* fdtoq */
- CHECK_FPU_FEATURE(dc, FLOAT128);
- gen_op_load_fpr_DT1(DFPREG(rs2));
- gen_helper_fdtoq();
- gen_op_store_QT0_fpr(QFPREG(rd));
- break;
- case 0xd1: /* fstoi */
- gen_clear_float_exceptions();
- gen_helper_fstoi(cpu_tmp32, cpu_fpr[rs2]);
- gen_helper_check_ieee_exceptions();
- tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);
- break;
- case 0xd2: /* fdtoi */
- gen_op_load_fpr_DT1(DFPREG(rs2));
- gen_clear_float_exceptions();
- gen_helper_fdtoi(cpu_tmp32);
- gen_helper_check_ieee_exceptions();
- tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);
- break;
- case 0xd3: /* fqtoi */
- CHECK_FPU_FEATURE(dc, FLOAT128);
- gen_op_load_fpr_QT1(QFPREG(rs2));
- gen_clear_float_exceptions();
- gen_helper_fqtoi(cpu_tmp32);
- gen_helper_check_ieee_exceptions();
- tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);
- break;
+ case 0x1: /* fmovs */
+ tcg_gen_mov_i32(cpu_fpr[rd], cpu_fpr[rs2]);
+ break;
+ case 0x5: /* fnegs */
+ gen_helper_fnegs(cpu_fpr[rd], cpu_fpr[rs2]);
+ break;
+ case 0x9: /* fabss */
+ gen_helper_fabss(cpu_fpr[rd], cpu_fpr[rs2]);
+ break;
+ case 0x29: /* fsqrts */
+ CHECK_FPU_FEATURE(dc, FSQRT);
+ gen_clear_float_exceptions();
+ gen_helper_fsqrts(cpu_tmp32, cpu_fpr[rs2]);
+ gen_helper_check_ieee_exceptions();
+ tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);
+ break;
+ case 0x2a: /* fsqrtd */
+ CHECK_FPU_FEATURE(dc, FSQRT);
+ gen_op_load_fpr_DT1(DFPREG(rs2));
+ gen_clear_float_exceptions();
+ gen_helper_fsqrtd();
+ gen_helper_check_ieee_exceptions();
+ gen_op_store_DT0_fpr(DFPREG(rd));
+ break;
+ case 0x2b: /* fsqrtq */
+ CHECK_FPU_FEATURE(dc, FLOAT128);
+ gen_op_load_fpr_QT1(QFPREG(rs2));
+ gen_clear_float_exceptions();
+ gen_helper_fsqrtq();
+ gen_helper_check_ieee_exceptions();
+ gen_op_store_QT0_fpr(QFPREG(rd));
+ break;
+ case 0x41: /* fadds */
+ gen_clear_float_exceptions();
+ gen_helper_fadds(cpu_tmp32, cpu_fpr[rs1], cpu_fpr[rs2]);
+ gen_helper_check_ieee_exceptions();
+ tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);
+ break;
+ case 0x42: /* faddd */
+ gen_op_load_fpr_DT0(DFPREG(rs1));
+ gen_op_load_fpr_DT1(DFPREG(rs2));
+ gen_clear_float_exceptions();
+ gen_helper_faddd();
+ gen_helper_check_ieee_exceptions();
+ gen_op_store_DT0_fpr(DFPREG(rd));
+ break;
+ case 0x43: /* faddq */
+ CHECK_FPU_FEATURE(dc, FLOAT128);
+ gen_op_load_fpr_QT0(QFPREG(rs1));
+ gen_op_load_fpr_QT1(QFPREG(rs2));
+ gen_clear_float_exceptions();
+ gen_helper_faddq();
+ gen_helper_check_ieee_exceptions();
+ gen_op_store_QT0_fpr(QFPREG(rd));
+ break;
+ case 0x45: /* fsubs */
+ gen_clear_float_exceptions();
+ gen_helper_fsubs(cpu_tmp32, cpu_fpr[rs1], cpu_fpr[rs2]);
+ gen_helper_check_ieee_exceptions();
+ tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);
+ break;
+ case 0x46: /* fsubd */
+ gen_op_load_fpr_DT0(DFPREG(rs1));
+ gen_op_load_fpr_DT1(DFPREG(rs2));
+ gen_clear_float_exceptions();
+ gen_helper_fsubd();
+ gen_helper_check_ieee_exceptions();
+ gen_op_store_DT0_fpr(DFPREG(rd));
+ break;
+ case 0x47: /* fsubq */
+ CHECK_FPU_FEATURE(dc, FLOAT128);
+ gen_op_load_fpr_QT0(QFPREG(rs1));
+ gen_op_load_fpr_QT1(QFPREG(rs2));
+ gen_clear_float_exceptions();
+ gen_helper_fsubq();
+ gen_helper_check_ieee_exceptions();
+ gen_op_store_QT0_fpr(QFPREG(rd));
+ break;
+ case 0x49: /* fmuls */
+ CHECK_FPU_FEATURE(dc, FMUL);
+ gen_clear_float_exceptions();
+ gen_helper_fmuls(cpu_tmp32, cpu_fpr[rs1], cpu_fpr[rs2]);
+ gen_helper_check_ieee_exceptions();
+ tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);
+ break;
+ case 0x4a: /* fmuld */
+ CHECK_FPU_FEATURE(dc, FMUL);
+ gen_op_load_fpr_DT0(DFPREG(rs1));
+ gen_op_load_fpr_DT1(DFPREG(rs2));
+ gen_clear_float_exceptions();
+ gen_helper_fmuld();
+ gen_helper_check_ieee_exceptions();
+ gen_op_store_DT0_fpr(DFPREG(rd));
+ break;
+ case 0x4b: /* fmulq */
+ CHECK_FPU_FEATURE(dc, FLOAT128);
+ CHECK_FPU_FEATURE(dc, FMUL);
+ gen_op_load_fpr_QT0(QFPREG(rs1));
+ gen_op_load_fpr_QT1(QFPREG(rs2));
+ gen_clear_float_exceptions();
+ gen_helper_fmulq();
+ gen_helper_check_ieee_exceptions();
+ gen_op_store_QT0_fpr(QFPREG(rd));
+ break;
+ case 0x4d: /* fdivs */
+ gen_clear_float_exceptions();
+ gen_helper_fdivs(cpu_tmp32, cpu_fpr[rs1], cpu_fpr[rs2]);
+ gen_helper_check_ieee_exceptions();
+ tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);
+ break;
+ case 0x4e: /* fdivd */
+ gen_op_load_fpr_DT0(DFPREG(rs1));
+ gen_op_load_fpr_DT1(DFPREG(rs2));
+ gen_clear_float_exceptions();
+ gen_helper_fdivd();
+ gen_helper_check_ieee_exceptions();
+ gen_op_store_DT0_fpr(DFPREG(rd));
+ break;
+ case 0x4f: /* fdivq */
+ CHECK_FPU_FEATURE(dc, FLOAT128);
+ gen_op_load_fpr_QT0(QFPREG(rs1));
+ gen_op_load_fpr_QT1(QFPREG(rs2));
+ gen_clear_float_exceptions();
+ gen_helper_fdivq();
+ gen_helper_check_ieee_exceptions();
+ gen_op_store_QT0_fpr(QFPREG(rd));
+ break;
+ case 0x69: /* fsmuld */
+ CHECK_FPU_FEATURE(dc, FSMULD);
+ gen_clear_float_exceptions();
+ gen_helper_fsmuld(cpu_fpr[rs1], cpu_fpr[rs2]);
+ gen_helper_check_ieee_exceptions();
+ gen_op_store_DT0_fpr(DFPREG(rd));
+ break;
+ case 0x6e: /* fdmulq */
+ CHECK_FPU_FEATURE(dc, FLOAT128);
+ gen_op_load_fpr_DT0(DFPREG(rs1));
+ gen_op_load_fpr_DT1(DFPREG(rs2));
+ gen_clear_float_exceptions();
+ gen_helper_fdmulq();
+ gen_helper_check_ieee_exceptions();
+ gen_op_store_QT0_fpr(QFPREG(rd));
+ break;
+ case 0xc4: /* fitos */
+ gen_clear_float_exceptions();
+ gen_helper_fitos(cpu_tmp32, cpu_fpr[rs2]);
+ gen_helper_check_ieee_exceptions();
+ tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);
+ break;
+ case 0xc6: /* fdtos */
+ gen_op_load_fpr_DT1(DFPREG(rs2));
+ gen_clear_float_exceptions();
+ gen_helper_fdtos(cpu_tmp32);
+ gen_helper_check_ieee_exceptions();
+ tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);
+ break;
+ case 0xc7: /* fqtos */
+ CHECK_FPU_FEATURE(dc, FLOAT128);
+ gen_op_load_fpr_QT1(QFPREG(rs2));
+ gen_clear_float_exceptions();
+ gen_helper_fqtos(cpu_tmp32);
+ gen_helper_check_ieee_exceptions();
+ tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);
+ break;
+ case 0xc8: /* fitod */
+ gen_helper_fitod(cpu_fpr[rs2]);
+ gen_op_store_DT0_fpr(DFPREG(rd));
+ break;
+ case 0xc9: /* fstod */
+ gen_helper_fstod(cpu_fpr[rs2]);
+ gen_op_store_DT0_fpr(DFPREG(rd));
+ break;
+ case 0xcb: /* fqtod */
+ CHECK_FPU_FEATURE(dc, FLOAT128);
+ gen_op_load_fpr_QT1(QFPREG(rs2));
+ gen_clear_float_exceptions();
+ gen_helper_fqtod();
+ gen_helper_check_ieee_exceptions();
+ gen_op_store_DT0_fpr(DFPREG(rd));
+ break;
+ case 0xcc: /* fitoq */
+ CHECK_FPU_FEATURE(dc, FLOAT128);
+ gen_helper_fitoq(cpu_fpr[rs2]);
+ gen_op_store_QT0_fpr(QFPREG(rd));
+ break;
+ case 0xcd: /* fstoq */
+ CHECK_FPU_FEATURE(dc, FLOAT128);
+ gen_helper_fstoq(cpu_fpr[rs2]);
+ gen_op_store_QT0_fpr(QFPREG(rd));
+ break;
+ case 0xce: /* fdtoq */
+ CHECK_FPU_FEATURE(dc, FLOAT128);
+ gen_op_load_fpr_DT1(DFPREG(rs2));
+ gen_helper_fdtoq();
+ gen_op_store_QT0_fpr(QFPREG(rd));
+ break;
+ case 0xd1: /* fstoi */
+ gen_clear_float_exceptions();
+ gen_helper_fstoi(cpu_tmp32, cpu_fpr[rs2]);
+ gen_helper_check_ieee_exceptions();
+ tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);
+ break;
+ case 0xd2: /* fdtoi */
+ gen_op_load_fpr_DT1(DFPREG(rs2));
+ gen_clear_float_exceptions();
+ gen_helper_fdtoi(cpu_tmp32);
+ gen_helper_check_ieee_exceptions();
+ tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);
+ break;
+ case 0xd3: /* fqtoi */
+ CHECK_FPU_FEATURE(dc, FLOAT128);
+ gen_op_load_fpr_QT1(QFPREG(rs2));
+ gen_clear_float_exceptions();
+ gen_helper_fqtoi(cpu_tmp32);
+ gen_helper_check_ieee_exceptions();
+ tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);
+ break;
#ifdef TARGET_SPARC64
- case 0x2: /* V9 fmovd */
- tcg_gen_mov_i32(cpu_fpr[DFPREG(rd)],
- cpu_fpr[DFPREG(rs2)]);
- tcg_gen_mov_i32(cpu_fpr[DFPREG(rd) + 1],
- cpu_fpr[DFPREG(rs2) + 1]);
- break;
- case 0x3: /* V9 fmovq */
- CHECK_FPU_FEATURE(dc, FLOAT128);
- tcg_gen_mov_i32(cpu_fpr[QFPREG(rd)],
- cpu_fpr[QFPREG(rs2)]);
- tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 1],
- cpu_fpr[QFPREG(rs2) + 1]);
- tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 2],
- cpu_fpr[QFPREG(rs2) + 2]);
- tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 3],
- cpu_fpr[QFPREG(rs2) + 3]);
- break;
- case 0x6: /* V9 fnegd */
- gen_op_load_fpr_DT1(DFPREG(rs2));
- gen_helper_fnegd();
- gen_op_store_DT0_fpr(DFPREG(rd));
- break;
- case 0x7: /* V9 fnegq */
- CHECK_FPU_FEATURE(dc, FLOAT128);
- gen_op_load_fpr_QT1(QFPREG(rs2));
- gen_helper_fnegq();
- gen_op_store_QT0_fpr(QFPREG(rd));
- break;
- case 0xa: /* V9 fabsd */
- gen_op_load_fpr_DT1(DFPREG(rs2));
- gen_helper_fabsd();
- gen_op_store_DT0_fpr(DFPREG(rd));
- break;
- case 0xb: /* V9 fabsq */
- CHECK_FPU_FEATURE(dc, FLOAT128);
- gen_op_load_fpr_QT1(QFPREG(rs2));
- gen_helper_fabsq();
- gen_op_store_QT0_fpr(QFPREG(rd));
- break;
- case 0x81: /* V9 fstox */
- gen_clear_float_exceptions();
- gen_helper_fstox(cpu_fpr[rs2]);
- gen_helper_check_ieee_exceptions();
- gen_op_store_DT0_fpr(DFPREG(rd));
- break;
- case 0x82: /* V9 fdtox */
- gen_op_load_fpr_DT1(DFPREG(rs2));
- gen_clear_float_exceptions();
- gen_helper_fdtox();
- gen_helper_check_ieee_exceptions();
- gen_op_store_DT0_fpr(DFPREG(rd));
- break;
- case 0x83: /* V9 fqtox */
- CHECK_FPU_FEATURE(dc, FLOAT128);
- gen_op_load_fpr_QT1(QFPREG(rs2));
- gen_clear_float_exceptions();
- gen_helper_fqtox();
- gen_helper_check_ieee_exceptions();
- gen_op_store_DT0_fpr(DFPREG(rd));
- break;
- case 0x84: /* V9 fxtos */
- gen_op_load_fpr_DT1(DFPREG(rs2));
- gen_clear_float_exceptions();
- gen_helper_fxtos(cpu_tmp32);
- gen_helper_check_ieee_exceptions();
- tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);
- break;
- case 0x88: /* V9 fxtod */
- gen_op_load_fpr_DT1(DFPREG(rs2));
- gen_clear_float_exceptions();
- gen_helper_fxtod();
- gen_helper_check_ieee_exceptions();
- gen_op_store_DT0_fpr(DFPREG(rd));
- break;
- case 0x8c: /* V9 fxtoq */
- CHECK_FPU_FEATURE(dc, FLOAT128);
- gen_op_load_fpr_DT1(DFPREG(rs2));
- gen_clear_float_exceptions();
- gen_helper_fxtoq();
- gen_helper_check_ieee_exceptions();
- gen_op_store_QT0_fpr(QFPREG(rd));
- break;
+ case 0x2: /* V9 fmovd */
+ tcg_gen_mov_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs2)]);
+ tcg_gen_mov_i32(cpu_fpr[DFPREG(rd) + 1],
+ cpu_fpr[DFPREG(rs2) + 1]);
+ break;
+ case 0x3: /* V9 fmovq */
+ CHECK_FPU_FEATURE(dc, FLOAT128);
+ tcg_gen_mov_i32(cpu_fpr[QFPREG(rd)], cpu_fpr[QFPREG(rs2)]);
+ tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 1],
+ cpu_fpr[QFPREG(rs2) + 1]);
+ tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 2],
+ cpu_fpr[QFPREG(rs2) + 2]);
+ tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 3],
+ cpu_fpr[QFPREG(rs2) + 3]);
+ break;
+ case 0x6: /* V9 fnegd */
+ gen_op_load_fpr_DT1(DFPREG(rs2));
+ gen_helper_fnegd();
+ gen_op_store_DT0_fpr(DFPREG(rd));
+ break;
+ case 0x7: /* V9 fnegq */
+ CHECK_FPU_FEATURE(dc, FLOAT128);
+ gen_op_load_fpr_QT1(QFPREG(rs2));
+ gen_helper_fnegq();
+ gen_op_store_QT0_fpr(QFPREG(rd));
+ break;
+ case 0xa: /* V9 fabsd */
+ gen_op_load_fpr_DT1(DFPREG(rs2));
+ gen_helper_fabsd();
+ gen_op_store_DT0_fpr(DFPREG(rd));
+ break;
+ case 0xb: /* V9 fabsq */
+ CHECK_FPU_FEATURE(dc, FLOAT128);
+ gen_op_load_fpr_QT1(QFPREG(rs2));
+ gen_helper_fabsq();
+ gen_op_store_QT0_fpr(QFPREG(rd));
+ break;
+ case 0x81: /* V9 fstox */
+ gen_clear_float_exceptions();
+ gen_helper_fstox(cpu_fpr[rs2]);
+ gen_helper_check_ieee_exceptions();
+ gen_op_store_DT0_fpr(DFPREG(rd));
+ break;
+ case 0x82: /* V9 fdtox */
+ gen_op_load_fpr_DT1(DFPREG(rs2));
+ gen_clear_float_exceptions();
+ gen_helper_fdtox();
+ gen_helper_check_ieee_exceptions();
+ gen_op_store_DT0_fpr(DFPREG(rd));
+ break;
+ case 0x83: /* V9 fqtox */
+ CHECK_FPU_FEATURE(dc, FLOAT128);
+ gen_op_load_fpr_QT1(QFPREG(rs2));
+ gen_clear_float_exceptions();
+ gen_helper_fqtox();
+ gen_helper_check_ieee_exceptions();
+ gen_op_store_DT0_fpr(DFPREG(rd));
+ break;
+ case 0x84: /* V9 fxtos */
+ gen_op_load_fpr_DT1(DFPREG(rs2));
+ gen_clear_float_exceptions();
+ gen_helper_fxtos(cpu_tmp32);
+ gen_helper_check_ieee_exceptions();
+ tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);
+ break;
+ case 0x88: /* V9 fxtod */
+ gen_op_load_fpr_DT1(DFPREG(rs2));
+ gen_clear_float_exceptions();
+ gen_helper_fxtod();
+ gen_helper_check_ieee_exceptions();
+ gen_op_store_DT0_fpr(DFPREG(rd));
+ break;
+ case 0x8c: /* V9 fxtoq */
+ CHECK_FPU_FEATURE(dc, FLOAT128);
+ gen_op_load_fpr_DT1(DFPREG(rs2));
+ gen_clear_float_exceptions();
+ gen_helper_fxtoq();
+ gen_helper_check_ieee_exceptions();
+ gen_op_store_QT0_fpr(QFPREG(rd));
+ break;
#endif
- default:
- goto illegal_insn;
+ default:
+ goto illegal_insn;
}
} else if (xop == 0x35) { /* FPU Operations */
#ifdef TARGET_SPARC64
int l1; \
\
l1 = gen_new_label(); \
- r_cond = tcg_temp_new(); \
+ r_cond = tcg_temp_new(); \
cond = GET_FIELD_SP(insn, 14, 17); \
gen_fcond(r_cond, fcc, cond); \
tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \
int l1; \
\
l1 = gen_new_label(); \
- r_cond = tcg_temp_new(); \
+ r_cond = tcg_temp_new(); \
cond = GET_FIELD_SP(insn, 14, 17); \
gen_fcond(r_cond, fcc, cond); \
tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \
int l1; \
\
l1 = gen_new_label(); \
- r_cond = tcg_temp_new(); \
+ r_cond = tcg_temp_new(); \
cond = GET_FIELD_SP(insn, 14, 17); \
gen_fcond(r_cond, fcc, cond); \
tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \
#undef FMOVSCC
#undef FMOVDCC
#undef FMOVQCC
-#define FMOVCC(size_FDQ, icc) \
- { \
- TCGv r_cond; \
- int l1; \
- \
- l1 = gen_new_label(); \
- r_cond = tcg_temp_new(); \
- cond = GET_FIELD_SP(insn, 14, 17); \
- gen_cond(r_cond, icc, cond); \
- tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \
- 0, l1); \
- glue(glue(gen_op_load_fpr_, size_FDQ), T0) \
- (glue(size_FDQ, FPREG(rs2))); \
- glue(glue(gen_op_store_, size_FDQ), T0_fpr) \
- (glue(size_FDQ, FPREG(rd))); \
- gen_set_label(l1); \
- tcg_temp_free(r_cond); \
- }
#define FMOVSCC(icc) \
{ \
TCGv r_cond; \
int l1; \
\
l1 = gen_new_label(); \
- r_cond = tcg_temp_new(); \
+ r_cond = tcg_temp_new(); \
cond = GET_FIELD_SP(insn, 14, 17); \
- gen_cond(r_cond, icc, cond); \
+ gen_cond(r_cond, icc, cond, dc); \
tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \
0, l1); \
tcg_gen_mov_i32(cpu_fpr[rd], cpu_fpr[rs2]); \
int l1; \
\
l1 = gen_new_label(); \
- r_cond = tcg_temp_new(); \
+ r_cond = tcg_temp_new(); \
cond = GET_FIELD_SP(insn, 14, 17); \
- gen_cond(r_cond, icc, cond); \
+ gen_cond(r_cond, icc, cond, dc); \
tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \
0, l1); \
tcg_gen_mov_i32(cpu_fpr[DFPREG(rd)], \
int l1; \
\
l1 = gen_new_label(); \
- r_cond = tcg_temp_new(); \
+ r_cond = tcg_temp_new(); \
cond = GET_FIELD_SP(insn, 14, 17); \
- gen_cond(r_cond, icc, cond); \
+ gen_cond(r_cond, icc, cond, dc); \
tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \
0, l1); \
tcg_gen_mov_i32(cpu_fpr[QFPREG(rd)], \
if (IS_IMM) { /* immediate */
TCGv r_const;
- rs2 = GET_FIELDs(insn, 19, 31);
- r_const = tcg_const_tl((int)rs2);
+ simm = GET_FIELDs(insn, 19, 31);
+ r_const = tcg_const_tl(simm);
gen_movl_TN_reg(rd, r_const);
tcg_temp_free(r_const);
} else { /* register */
} else {
cpu_src1 = get_src1(insn, cpu_src1);
if (IS_IMM) { /* immediate */
- rs2 = GET_FIELDs(insn, 19, 31);
- tcg_gen_ori_tl(cpu_dst, cpu_src1, (int)rs2);
+ simm = GET_FIELDs(insn, 19, 31);
+ tcg_gen_ori_tl(cpu_dst, cpu_src1, simm);
gen_movl_TN_reg(rd, cpu_dst);
} else { /* register */
// or x, %g0, y -> mov T1, x; mov y, T1
} else if (xop == 0x25) { /* sll, V9 sllx */
cpu_src1 = get_src1(insn, cpu_src1);
if (IS_IMM) { /* immediate */
- rs2 = GET_FIELDs(insn, 20, 31);
+ simm = GET_FIELDs(insn, 20, 31);
if (insn & (1 << 12)) {
- tcg_gen_shli_i64(cpu_dst, cpu_src1, rs2 & 0x3f);
+ tcg_gen_shli_i64(cpu_dst, cpu_src1, simm & 0x3f);
} else {
- tcg_gen_shli_i64(cpu_dst, cpu_src1, rs2 & 0x1f);
+ tcg_gen_shli_i64(cpu_dst, cpu_src1, simm & 0x1f);
}
} else { /* register */
rs2 = GET_FIELD(insn, 27, 31);
} else if (xop == 0x26) { /* srl, V9 srlx */
cpu_src1 = get_src1(insn, cpu_src1);
if (IS_IMM) { /* immediate */
- rs2 = GET_FIELDs(insn, 20, 31);
+ simm = GET_FIELDs(insn, 20, 31);
if (insn & (1 << 12)) {
- tcg_gen_shri_i64(cpu_dst, cpu_src1, rs2 & 0x3f);
+ tcg_gen_shri_i64(cpu_dst, cpu_src1, simm & 0x3f);
} else {
tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
- tcg_gen_shri_i64(cpu_dst, cpu_dst, rs2 & 0x1f);
+ tcg_gen_shri_i64(cpu_dst, cpu_dst, simm & 0x1f);
}
} else { /* register */
rs2 = GET_FIELD(insn, 27, 31);
} else if (xop == 0x27) { /* sra, V9 srax */
cpu_src1 = get_src1(insn, cpu_src1);
if (IS_IMM) { /* immediate */
- rs2 = GET_FIELDs(insn, 20, 31);
+ simm = GET_FIELDs(insn, 20, 31);
if (insn & (1 << 12)) {
- tcg_gen_sari_i64(cpu_dst, cpu_src1, rs2 & 0x3f);
+ tcg_gen_sari_i64(cpu_dst, cpu_src1, simm & 0x3f);
} else {
tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
tcg_gen_ext32s_i64(cpu_dst, cpu_dst);
- tcg_gen_sari_i64(cpu_dst, cpu_dst, rs2 & 0x1f);
+ tcg_gen_sari_i64(cpu_dst, cpu_dst, simm & 0x1f);
}
} else { /* register */
rs2 = GET_FIELD(insn, 27, 31);
gen_movl_TN_reg(rd, cpu_dst);
#endif
} else if (xop < 0x36) {
- cpu_src1 = get_src1(insn, cpu_src1);
- cpu_src2 = get_src2(insn, cpu_src2);
if (xop < 0x20) {
+ cpu_src1 = get_src1(insn, cpu_src1);
+ cpu_src2 = get_src2(insn, cpu_src2);
switch (xop & ~0x10) {
- case 0x0:
- if (xop & 0x10)
- gen_op_add_cc(cpu_dst, cpu_src1, cpu_src2);
- else
- tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
+ case 0x0: /* add */
+ if (IS_IMM) {
+ simm = GET_FIELDs(insn, 19, 31);
+ if (xop & 0x10) {
+ gen_op_addi_cc(cpu_dst, cpu_src1, simm);
+ tcg_gen_movi_i32(cpu_cc_op, CC_OP_ADD);
+ dc->cc_op = CC_OP_ADD;
+ } else {
+ tcg_gen_addi_tl(cpu_dst, cpu_src1, simm);
+ }
+ } else {
+ if (xop & 0x10) {
+ gen_op_add_cc(cpu_dst, cpu_src1, cpu_src2);
+ tcg_gen_movi_i32(cpu_cc_op, CC_OP_ADD);
+ dc->cc_op = CC_OP_ADD;
+ } else {
+ tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
+ }
+ }
break;
- case 0x1:
- tcg_gen_and_tl(cpu_dst, cpu_src1, cpu_src2);
- if (xop & 0x10)
- gen_op_logic_cc(cpu_dst);
+ case 0x1: /* and */
+ if (IS_IMM) {
+ simm = GET_FIELDs(insn, 19, 31);
+ tcg_gen_andi_tl(cpu_dst, cpu_src1, simm);
+ } else {
+ tcg_gen_and_tl(cpu_dst, cpu_src1, cpu_src2);
+ }
+ if (xop & 0x10) {
+ tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
+ tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
+ dc->cc_op = CC_OP_LOGIC;
+ }
break;
- case 0x2:
- tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_src2);
- if (xop & 0x10)
- gen_op_logic_cc(cpu_dst);
+ case 0x2: /* or */
+ if (IS_IMM) {
+ simm = GET_FIELDs(insn, 19, 31);
+ tcg_gen_ori_tl(cpu_dst, cpu_src1, simm);
+ } else {
+ tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_src2);
+ }
+ if (xop & 0x10) {
+ tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
+ tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
+ dc->cc_op = CC_OP_LOGIC;
+ }
break;
- case 0x3:
- tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
- if (xop & 0x10)
- gen_op_logic_cc(cpu_dst);
+ case 0x3: /* xor */
+ if (IS_IMM) {
+ simm = GET_FIELDs(insn, 19, 31);
+ tcg_gen_xori_tl(cpu_dst, cpu_src1, simm);
+ } else {
+ tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
+ }
+ if (xop & 0x10) {
+ tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
+ tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
+ dc->cc_op = CC_OP_LOGIC;
+ }
break;
- case 0x4:
- if (xop & 0x10)
- gen_op_sub_cc(cpu_dst, cpu_src1, cpu_src2);
- else
- tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_src2);
+ case 0x4: /* sub */
+ if (IS_IMM) {
+ simm = GET_FIELDs(insn, 19, 31);
+ if (xop & 0x10) {
+ gen_op_subi_cc(cpu_dst, cpu_src1, simm, dc);
+ } else {
+ tcg_gen_subi_tl(cpu_dst, cpu_src1, simm);
+ }
+ } else {
+ if (xop & 0x10) {
+ gen_op_sub_cc(cpu_dst, cpu_src1, cpu_src2);
+ tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUB);
+ dc->cc_op = CC_OP_SUB;
+ } else {
+ tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_src2);
+ }
+ }
break;
- case 0x5:
- tcg_gen_andc_tl(cpu_dst, cpu_src1, cpu_src2);
- if (xop & 0x10)
- gen_op_logic_cc(cpu_dst);
+ case 0x5: /* andn */
+ if (IS_IMM) {
+ simm = GET_FIELDs(insn, 19, 31);
+ tcg_gen_andi_tl(cpu_dst, cpu_src1, ~simm);
+ } else {
+ tcg_gen_andc_tl(cpu_dst, cpu_src1, cpu_src2);
+ }
+ if (xop & 0x10) {
+ tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
+ tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
+ dc->cc_op = CC_OP_LOGIC;
+ }
break;
- case 0x6:
- tcg_gen_orc_tl(cpu_dst, cpu_src1, cpu_src2);
- if (xop & 0x10)
- gen_op_logic_cc(cpu_dst);
+ case 0x6: /* orn */
+ if (IS_IMM) {
+ simm = GET_FIELDs(insn, 19, 31);
+ tcg_gen_ori_tl(cpu_dst, cpu_src1, ~simm);
+ } else {
+ tcg_gen_orc_tl(cpu_dst, cpu_src1, cpu_src2);
+ }
+ if (xop & 0x10) {
+ tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
+ tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
+ dc->cc_op = CC_OP_LOGIC;
+ }
break;
- case 0x7:
- tcg_gen_not_tl(cpu_tmp0, cpu_src2);
- tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_tmp0);
- if (xop & 0x10)
- gen_op_logic_cc(cpu_dst);
+ case 0x7: /* xorn */
+ if (IS_IMM) {
+ simm = GET_FIELDs(insn, 19, 31);
+ tcg_gen_xori_tl(cpu_dst, cpu_src1, ~simm);
+ } else {
+ tcg_gen_not_tl(cpu_tmp0, cpu_src2);
+ tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_tmp0);
+ }
+ if (xop & 0x10) {
+ tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
+ tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
+ dc->cc_op = CC_OP_LOGIC;
+ }
break;
- case 0x8:
- if (xop & 0x10)
- gen_op_addx_cc(cpu_dst, cpu_src1, cpu_src2);
- else {
- gen_mov_reg_C(cpu_tmp0, cpu_psr);
- tcg_gen_add_tl(cpu_tmp0, cpu_src2, cpu_tmp0);
- tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_tmp0);
+ case 0x8: /* addx, V9 addc */
+ if (IS_IMM) {
+ simm = GET_FIELDs(insn, 19, 31);
+ if (xop & 0x10) {
+ gen_helper_compute_psr();
+ gen_op_addxi_cc(cpu_dst, cpu_src1, simm);
+ tcg_gen_movi_i32(cpu_cc_op, CC_OP_ADDX);
+ dc->cc_op = CC_OP_ADDX;
+ } else {
+ gen_helper_compute_psr();
+ gen_mov_reg_C(cpu_tmp0, cpu_psr);
+ tcg_gen_addi_tl(cpu_tmp0, cpu_tmp0, simm);
+ tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_tmp0);
+ }
+ } else {
+ if (xop & 0x10) {
+ gen_helper_compute_psr();
+ gen_op_addx_cc(cpu_dst, cpu_src1, cpu_src2);
+ tcg_gen_movi_i32(cpu_cc_op, CC_OP_ADDX);
+ dc->cc_op = CC_OP_ADDX;
+ } else {
+ gen_helper_compute_psr();
+ gen_mov_reg_C(cpu_tmp0, cpu_psr);
+ tcg_gen_add_tl(cpu_tmp0, cpu_src2, cpu_tmp0);
+ tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_tmp0);
+ }
}
break;
#ifdef TARGET_SPARC64
case 0x9: /* V9 mulx */
- tcg_gen_mul_i64(cpu_dst, cpu_src1, cpu_src2);
+ if (IS_IMM) {
+ simm = GET_FIELDs(insn, 19, 31);
+ tcg_gen_muli_i64(cpu_dst, cpu_src1, simm);
+ } else {
+ tcg_gen_mul_i64(cpu_dst, cpu_src1, cpu_src2);
+ }
break;
#endif
- case 0xa:
+ case 0xa: /* umul */
CHECK_IU_FEATURE(dc, MUL);
gen_op_umul(cpu_dst, cpu_src1, cpu_src2);
- if (xop & 0x10)
- gen_op_logic_cc(cpu_dst);
+ if (xop & 0x10) {
+ tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
+ tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
+ dc->cc_op = CC_OP_LOGIC;
+ }
break;
- case 0xb:
+ case 0xb: /* smul */
CHECK_IU_FEATURE(dc, MUL);
gen_op_smul(cpu_dst, cpu_src1, cpu_src2);
- if (xop & 0x10)
- gen_op_logic_cc(cpu_dst);
+ if (xop & 0x10) {
+ tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
+ tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
+ dc->cc_op = CC_OP_LOGIC;
+ }
break;
- case 0xc:
- if (xop & 0x10)
- gen_op_subx_cc(cpu_dst, cpu_src1, cpu_src2);
- else {
- gen_mov_reg_C(cpu_tmp0, cpu_psr);
- tcg_gen_add_tl(cpu_tmp0, cpu_src2, cpu_tmp0);
- tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_tmp0);
+ case 0xc: /* subx, V9 subc */
+ if (IS_IMM) {
+ simm = GET_FIELDs(insn, 19, 31);
+ if (xop & 0x10) {
+ gen_helper_compute_psr();
+ gen_op_subxi_cc(cpu_dst, cpu_src1, simm);
+ tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUBX);
+ dc->cc_op = CC_OP_SUBX;
+ } else {
+ gen_helper_compute_psr();
+ gen_mov_reg_C(cpu_tmp0, cpu_psr);
+ tcg_gen_addi_tl(cpu_tmp0, cpu_tmp0, simm);
+ tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_tmp0);
+ }
+ } else {
+ if (xop & 0x10) {
+ gen_helper_compute_psr();
+ gen_op_subx_cc(cpu_dst, cpu_src1, cpu_src2);
+ tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUBX);
+ dc->cc_op = CC_OP_SUBX;
+ } else {
+ gen_helper_compute_psr();
+ gen_mov_reg_C(cpu_tmp0, cpu_psr);
+ tcg_gen_add_tl(cpu_tmp0, cpu_src2, cpu_tmp0);
+ tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_tmp0);
+ }
}
break;
#ifdef TARGET_SPARC64
tcg_gen_divu_i64(cpu_dst, cpu_cc_src, cpu_cc_src2);
break;
#endif
- case 0xe:
+ case 0xe: /* udiv */
CHECK_IU_FEATURE(dc, DIV);
gen_helper_udiv(cpu_dst, cpu_src1, cpu_src2);
- if (xop & 0x10)
+ if (xop & 0x10) {
gen_op_div_cc(cpu_dst);
+ tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
+ dc->cc_op = CC_OP_FLAGS;
+ }
break;
- case 0xf:
+ case 0xf: /* sdiv */
CHECK_IU_FEATURE(dc, DIV);
gen_helper_sdiv(cpu_dst, cpu_src1, cpu_src2);
- if (xop & 0x10)
+ if (xop & 0x10) {
gen_op_div_cc(cpu_dst);
+ tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
+ dc->cc_op = CC_OP_FLAGS;
+ }
break;
default:
goto illegal_insn;
}
gen_movl_TN_reg(rd, cpu_dst);
} else {
+ cpu_src1 = get_src1(insn, cpu_src1);
+ cpu_src2 = get_src2(insn, cpu_src2);
switch (xop) {
case 0x20: /* taddcc */
gen_op_tadd_cc(cpu_dst, cpu_src1, cpu_src2);
gen_movl_TN_reg(rd, cpu_dst);
+ tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
+ dc->cc_op = CC_OP_FLAGS;
break;
case 0x21: /* tsubcc */
gen_op_tsub_cc(cpu_dst, cpu_src1, cpu_src2);
gen_movl_TN_reg(rd, cpu_dst);
+ tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
+ dc->cc_op = CC_OP_FLAGS;
break;
case 0x22: /* taddcctv */
save_state(dc, cpu_cond);
gen_op_tadd_ccTV(cpu_dst, cpu_src1, cpu_src2);
gen_movl_TN_reg(rd, cpu_dst);
+ tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
+ dc->cc_op = CC_OP_FLAGS;
break;
case 0x23: /* tsubcctv */
save_state(dc, cpu_cond);
gen_op_tsub_ccTV(cpu_dst, cpu_src1, cpu_src2);
gen_movl_TN_reg(rd, cpu_dst);
+ tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
+ dc->cc_op = CC_OP_FLAGS;
break;
case 0x24: /* mulscc */
+ gen_helper_compute_psr();
gen_op_mulscc(cpu_dst, cpu_src1, cpu_src2);
gen_movl_TN_reg(rd, cpu_dst);
+ tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
+ dc->cc_op = CC_OP_FLAGS;
break;
#ifndef TARGET_SPARC64
case 0x25: /* sll */
if (IS_IMM) { /* immediate */
- rs2 = GET_FIELDs(insn, 20, 31);
- tcg_gen_shli_tl(cpu_dst, cpu_src1, rs2 & 0x1f);
+ simm = GET_FIELDs(insn, 20, 31);
+ tcg_gen_shli_tl(cpu_dst, cpu_src1, simm & 0x1f);
} else { /* register */
tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
tcg_gen_shl_tl(cpu_dst, cpu_src1, cpu_tmp0);
break;
case 0x26: /* srl */
if (IS_IMM) { /* immediate */
- rs2 = GET_FIELDs(insn, 20, 31);
- tcg_gen_shri_tl(cpu_dst, cpu_src1, rs2 & 0x1f);
+ simm = GET_FIELDs(insn, 20, 31);
+ tcg_gen_shri_tl(cpu_dst, cpu_src1, simm & 0x1f);
} else { /* register */
tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
tcg_gen_shr_tl(cpu_dst, cpu_src1, cpu_tmp0);
break;
case 0x27: /* sra */
if (IS_IMM) { /* immediate */
- rs2 = GET_FIELDs(insn, 20, 31);
- tcg_gen_sari_tl(cpu_dst, cpu_src1, rs2 & 0x1f);
+ simm = GET_FIELDs(insn, 20, 31);
+ tcg_gen_sari_tl(cpu_dst, cpu_src1, simm & 0x1f);
} else { /* register */
tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
tcg_gen_sar_tl(cpu_dst, cpu_src1, cpu_tmp0);
case 0x2: /* V9 wrccr */
tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
gen_helper_wrccr(cpu_dst);
+ tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
+ dc->cc_op = CC_OP_FLAGS;
break;
case 0x3: /* V9 wrasi */
tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
#else
tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
gen_helper_wrpsr(cpu_dst);
+ tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
+ dc->cc_op = CC_OP_FLAGS;
save_state(dc, cpu_cond);
gen_op_next_insn();
tcg_gen_exit_tb(0);
r_cond = tcg_temp_new();
if (insn & (1 << 18)) {
if (cc == 0)
- gen_cond(r_cond, 0, cond);
+ gen_cond(r_cond, 0, cond, dc);
else if (cc == 2)
- gen_cond(r_cond, 1, cond);
+ gen_cond(r_cond, 1, cond, dc);
else
goto illegal_insn;
} else {
if (IS_IMM) { /* immediate */
TCGv r_const;
- rs2 = GET_FIELD_SPs(insn, 0, 10);
- r_const = tcg_const_tl((int)rs2);
+ simm = GET_FIELD_SPs(insn, 0, 10);
+ r_const = tcg_const_tl(simm);
gen_movl_TN_reg(rd, r_const);
tcg_temp_free(r_const);
} else {
if (IS_IMM) { /* immediate */
TCGv r_const;
- rs2 = GET_FIELD_SPs(insn, 0, 9);
- r_const = tcg_const_tl((int)rs2);
+ simm = GET_FIELD_SPs(insn, 0, 9);
+ r_const = tcg_const_tl(simm);
gen_movl_TN_reg(rd, r_const);
tcg_temp_free(r_const);
} else {
save_state(dc, cpu_cond);
cpu_src1 = get_src1(insn, cpu_src1);
if (IS_IMM) { /* immediate */
- rs2 = GET_FIELDs(insn, 19, 31);
- tcg_gen_addi_tl(cpu_dst, cpu_src1, (int)rs2);
+ simm = GET_FIELDs(insn, 19, 31);
+ tcg_gen_addi_tl(cpu_dst, cpu_src1, simm);
} else { /* register */
rs2 = GET_FIELD(insn, 27, 31);
if (rs2) {
} else {
cpu_src1 = get_src1(insn, cpu_src1);
if (IS_IMM) { /* immediate */
- rs2 = GET_FIELDs(insn, 19, 31);
- tcg_gen_addi_tl(cpu_dst, cpu_src1, (int)rs2);
+ simm = GET_FIELDs(insn, 19, 31);
+ tcg_gen_addi_tl(cpu_dst, cpu_src1, simm);
} else { /* register */
rs2 = GET_FIELD(insn, 27, 31);
if (rs2) {
gen_movl_reg_TN(rs2, cpu_src2);
tcg_gen_mov_tl(cpu_addr, cpu_src1);
} else if (IS_IMM) { /* immediate */
- rs2 = GET_FIELDs(insn, 19, 31);
- tcg_gen_addi_tl(cpu_addr, cpu_src1, (int)rs2);
+ simm = GET_FIELDs(insn, 19, 31);
+ tcg_gen_addi_tl(cpu_addr, cpu_src1, simm);
} else { /* register */
rs2 = GET_FIELD(insn, 27, 31);
if (rs2 != 0) {
(xop > 0x17 && xop <= 0x1d ) ||
(xop > 0x2c && xop <= 0x33) || xop == 0x1f || xop == 0x3d) {
switch (xop) {
- case 0x0: /* load unsigned word */
+ case 0x0: /* ld, V9 lduw, load unsigned word */
gen_address_mask(dc, cpu_addr);
tcg_gen_qemu_ld32u(cpu_val, cpu_addr, dc->mem_idx);
break;
- case 0x1: /* load unsigned byte */
+ case 0x1: /* ldub, load unsigned byte */
gen_address_mask(dc, cpu_addr);
tcg_gen_qemu_ld8u(cpu_val, cpu_addr, dc->mem_idx);
break;
- case 0x2: /* load unsigned halfword */
+ case 0x2: /* lduh, load unsigned halfword */
gen_address_mask(dc, cpu_addr);
tcg_gen_qemu_ld16u(cpu_val, cpu_addr, dc->mem_idx);
break;
- case 0x3: /* load double word */
+ case 0x3: /* ldd, load double word */
if (rd & 1)
goto illegal_insn;
else {
tcg_gen_andi_tl(cpu_val, cpu_val, 0xffffffffULL);
}
break;
- case 0x9: /* load signed byte */
+ case 0x9: /* ldsb, load signed byte */
gen_address_mask(dc, cpu_addr);
tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx);
break;
- case 0xa: /* load signed halfword */
+ case 0xa: /* ldsh, load signed halfword */
gen_address_mask(dc, cpu_addr);
tcg_gen_qemu_ld16s(cpu_val, cpu_addr, dc->mem_idx);
break;
tcg_temp_free(r_const);
}
break;
- case 0x0f: /* swap register with memory. Also
+ case 0x0f: /* swap, swap register with memory. Also
atomically */
CHECK_IU_FEATURE(dc, SWAP);
gen_movl_reg_TN(rd, cpu_val);
tcg_gen_mov_tl(cpu_val, cpu_tmp0);
break;
#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
- case 0x10: /* load word alternate */
+ case 0x10: /* lda, V9 lduwa, load word alternate */
#ifndef TARGET_SPARC64
if (IS_IMM)
goto illegal_insn;
save_state(dc, cpu_cond);
gen_ld_asi(cpu_val, cpu_addr, insn, 4, 0);
break;
- case 0x11: /* load unsigned byte alternate */
+ case 0x11: /* lduba, load unsigned byte alternate */
#ifndef TARGET_SPARC64
if (IS_IMM)
goto illegal_insn;
save_state(dc, cpu_cond);
gen_ld_asi(cpu_val, cpu_addr, insn, 1, 0);
break;
- case 0x12: /* load unsigned halfword alternate */
+ case 0x12: /* lduha, load unsigned halfword alternate */
#ifndef TARGET_SPARC64
if (IS_IMM)
goto illegal_insn;
save_state(dc, cpu_cond);
gen_ld_asi(cpu_val, cpu_addr, insn, 2, 0);
break;
- case 0x13: /* load double word alternate */
+ case 0x13: /* ldda, load double word alternate */
#ifndef TARGET_SPARC64
if (IS_IMM)
goto illegal_insn;
save_state(dc, cpu_cond);
gen_ldda_asi(cpu_val, cpu_addr, insn, rd);
goto skip_move;
- case 0x19: /* load signed byte alternate */
+ case 0x19: /* ldsba, load signed byte alternate */
#ifndef TARGET_SPARC64
if (IS_IMM)
goto illegal_insn;
save_state(dc, cpu_cond);
gen_ld_asi(cpu_val, cpu_addr, insn, 1, 1);
break;
- case 0x1a: /* load signed halfword alternate */
+ case 0x1a: /* ldsha, load signed halfword alternate */
#ifndef TARGET_SPARC64
if (IS_IMM)
goto illegal_insn;
save_state(dc, cpu_cond);
gen_ldstub_asi(cpu_val, cpu_addr, insn);
break;
- case 0x1f: /* swap reg with alt. memory. Also
+ case 0x1f: /* swapa, swap reg with alt. memory. Also
atomically */
CHECK_IU_FEATURE(dc, SWAP);
#ifndef TARGET_SPARC64
goto jmp_insn;
save_state(dc, cpu_cond);
switch (xop) {
- case 0x20: /* load fpreg */
+ case 0x20: /* ldf, load fpreg */
gen_address_mask(dc, cpu_addr);
tcg_gen_qemu_ld32u(cpu_tmp0, cpu_addr, dc->mem_idx);
tcg_gen_trunc_tl_i32(cpu_fpr[rd], cpu_tmp0);
}
#endif
break;
- case 0x22: /* load quad fpreg */
+ case 0x22: /* ldqf, load quad fpreg */
{
TCGv_i32 r_const;
gen_op_store_QT0_fpr(QFPREG(rd));
}
break;
- case 0x23: /* load double fpreg */
+ case 0x23: /* lddf, load double fpreg */
{
TCGv_i32 r_const;
default:
goto illegal_insn;
}
- } else if (xop < 8 || (xop >= 0x14 && xop < 0x18) || \
+ } else if (xop < 8 || (xop >= 0x14 && xop < 0x18) ||
xop == 0xe || xop == 0x1e) {
gen_movl_reg_TN(rd, cpu_val);
switch (xop) {
- case 0x4: /* store word */
+ case 0x4: /* st, store word */
gen_address_mask(dc, cpu_addr);
tcg_gen_qemu_st32(cpu_val, cpu_addr, dc->mem_idx);
break;
- case 0x5: /* store byte */
+ case 0x5: /* stb, store byte */
gen_address_mask(dc, cpu_addr);
tcg_gen_qemu_st8(cpu_val, cpu_addr, dc->mem_idx);
break;
- case 0x6: /* store halfword */
+ case 0x6: /* sth, store halfword */
gen_address_mask(dc, cpu_addr);
tcg_gen_qemu_st16(cpu_val, cpu_addr, dc->mem_idx);
break;
- case 0x7: /* store double word */
+ case 0x7: /* std, store double word */
if (rd & 1)
goto illegal_insn;
else {
}
break;
#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
- case 0x14: /* store word alternate */
+ case 0x14: /* sta, V9 stwa, store word alternate */
#ifndef TARGET_SPARC64
if (IS_IMM)
goto illegal_insn;
save_state(dc, cpu_cond);
gen_st_asi(cpu_val, cpu_addr, insn, 4);
break;
- case 0x15: /* store byte alternate */
+ case 0x15: /* stba, store byte alternate */
#ifndef TARGET_SPARC64
if (IS_IMM)
goto illegal_insn;
save_state(dc, cpu_cond);
gen_st_asi(cpu_val, cpu_addr, insn, 1);
break;
- case 0x16: /* store halfword alternate */
+ case 0x16: /* stha, store halfword alternate */
#ifndef TARGET_SPARC64
if (IS_IMM)
goto illegal_insn;
save_state(dc, cpu_cond);
gen_st_asi(cpu_val, cpu_addr, insn, 2);
break;
- case 0x17: /* store double word alternate */
+ case 0x17: /* stda, store double word alternate */
#ifndef TARGET_SPARC64
if (IS_IMM)
goto illegal_insn;
goto jmp_insn;
save_state(dc, cpu_cond);
switch (xop) {
- case 0x24: /* store fpreg */
+ case 0x24: /* stf, store fpreg */
gen_address_mask(dc, cpu_addr);
tcg_gen_ext_i32_tl(cpu_tmp0, cpu_fpr[rd]);
tcg_gen_qemu_st32(cpu_tmp0, cpu_addr, dc->mem_idx);
goto nfq_insn;
#endif
#endif
- case 0x27: /* store double fpreg */
+ case 0x27: /* stdf, store double fpreg */
{
TCGv_i32 r_const;
default:
goto illegal_insn;
}
- }
- else
+ } else
goto illegal_insn;
}
break;
dc->pc = pc_start;
last_pc = dc->pc;
dc->npc = (target_ulong) tb->cs_base;
+ dc->cc_op = CC_OP_DYNAMIC;
dc->mem_idx = cpu_mmu_index(env);
dc->def = env->def;
if ((dc->def->features & CPU_FEATURE_FLOAT))
max_insns = CF_COUNT_MASK;
gen_icount_start();
do {
- if (unlikely(env->breakpoints)) {
- for (bp = env->breakpoints; bp != NULL; bp = bp->next) {
+ if (unlikely(!TAILQ_EMPTY(&env->breakpoints))) {
+ TAILQ_FOREACH(bp, &env->breakpoints, entry) {
if (bp->pc == dc->pc) {
if (dc->pc != pc_start)
save_state(dc, cpu_cond);
}
}
if (spc) {
- if (loglevel > 0)
- fprintf(logfile, "Search PC...\n");
+ qemu_log("Search PC...\n");
j = gen_opc_ptr - gen_opc_buf;
if (lj < j) {
lj++;
break;
/* if single step mode, we generate only one instruction and
generate an exception */
- if (env->singlestep_enabled) {
+ if (env->singlestep_enabled || singlestep) {
tcg_gen_movi_tl(cpu_pc, dc->pc);
tcg_gen_exit_tb(0);
break;
while (lj <= j)
gen_opc_instr_start[lj++] = 0;
#if 0
- if (loglevel > 0) {
- page_dump(logfile);
- }
+ log_page_dump();
#endif
gen_opc_jump_pc[0] = dc->jump_pc[0];
gen_opc_jump_pc[1] = dc->jump_pc[1];
tb->icount = num_insns;
}
#ifdef DEBUG_DISAS
- if (loglevel & CPU_LOG_TB_IN_ASM) {
- fprintf(logfile, "--------------\n");
- fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
- target_disas(logfile, pc_start, last_pc + 4 - pc_start, 0);
- fprintf(logfile, "\n");
+ if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
+ qemu_log("--------------\n");
+ qemu_log("IN: %s\n", lookup_symbol(pc_start));
+ log_target_disas(pc_start, last_pc + 4 - pc_start, 0);
+ qemu_log("\n");
}
#endif
}
"cc_src2");
cpu_cc_dst = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, cc_dst),
"cc_dst");
+ cpu_cc_op = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUState, cc_op),
+ "cc_op");
cpu_psr = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUState, psr),
"psr");
cpu_fsr = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, fsr),
projects / qemu / blobdiff