Convert subx

[qemu] / target-sparc / translate.c

diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index f7bb15f..f4d3fbe 100644 (file)
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.c
@@ -432,18 +432,6 @@ static inline void gen_cc_V_tag(TCGv src1, TCGv src2)
     gen_set_label(l1);
 }
 
-static inline void gen_op_logic_cc(TCGv dst)
-{
-    tcg_gen_mov_tl(cpu_cc_dst, dst);
-
-    gen_cc_clear_icc();
-    gen_cc_NZ_icc(cpu_cc_dst);
-#ifdef TARGET_SPARC64
-    gen_cc_clear_xcc();
-    gen_cc_NZ_xcc(cpu_cc_dst);
-#endif
-}
-
 static inline void gen_tag_tv(TCGv src1, TCGv src2)
 {
     int l1;
@@ -475,33 +463,14 @@ static inline void gen_op_add_cc(TCGv dst, TCGv src1, TCGv src2)
     tcg_gen_mov_tl(dst, cpu_cc_dst);
 }
 
-static inline void gen_op_addx_cc2(TCGv dst)
-{
-    gen_cc_NZ_icc(cpu_cc_dst);
-    gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
-    gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
-#ifdef TARGET_SPARC64
-    gen_cc_NZ_xcc(cpu_cc_dst);
-    gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
-    gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
-#endif
-    tcg_gen_mov_tl(dst, cpu_cc_dst);
-}
-
 static inline void gen_op_addxi_cc(TCGv dst, TCGv src1, target_long src2)
 {
     tcg_gen_mov_tl(cpu_cc_src, src1);
     tcg_gen_movi_tl(cpu_cc_src2, src2);
     gen_mov_reg_C(cpu_tmp0, cpu_psr);
     tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_tmp0);
-    gen_cc_clear_icc();
-    gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
-#ifdef TARGET_SPARC64
-    gen_cc_clear_xcc();
-    gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
-#endif
     tcg_gen_addi_tl(cpu_cc_dst, cpu_cc_dst, src2);
-    gen_op_addx_cc2(dst);
+    tcg_gen_mov_tl(dst, cpu_cc_dst);
 }
 
 static inline void gen_op_addx_cc(TCGv dst, TCGv src1, TCGv src2)
@@ -510,14 +479,8 @@ static inline void gen_op_addx_cc(TCGv dst, TCGv src1, TCGv src2)
     tcg_gen_mov_tl(cpu_cc_src2, src2);
     gen_mov_reg_C(cpu_tmp0, cpu_psr);
     tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_tmp0);
-    gen_cc_clear_icc();
-    gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
-#ifdef TARGET_SPARC64
-    gen_cc_clear_xcc();
-    gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
-#endif
     tcg_gen_add_tl(cpu_cc_dst, cpu_cc_dst, cpu_cc_src2);
-    gen_op_addx_cc2(dst);
+    tcg_gen_mov_tl(dst, cpu_cc_dst);
 }
 
 static inline void gen_op_tadd_cc(TCGv dst, TCGv src1, TCGv src2)
@@ -648,32 +611,20 @@ static inline void gen_sub_tv(TCGv dst, TCGv src1, TCGv src2)
     tcg_temp_free(r_temp);
 }
 
-static inline void gen_op_sub_cc2(TCGv dst)
-{
-    gen_cc_clear_icc();
-    gen_cc_NZ_icc(cpu_cc_dst);
-    gen_cc_C_sub_icc(cpu_cc_src, cpu_cc_src2);
-    gen_cc_V_sub_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
-#ifdef TARGET_SPARC64
-    gen_cc_clear_xcc();
-    gen_cc_NZ_xcc(cpu_cc_dst);
-    gen_cc_C_sub_xcc(cpu_cc_src, cpu_cc_src2);
-    gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
-#endif
-    tcg_gen_mov_tl(dst, cpu_cc_dst);
-}
-
-static inline void gen_op_subi_cc(TCGv dst, TCGv src1, target_long src2)
+static inline void gen_op_subi_cc(TCGv dst, TCGv src1, target_long src2, DisasContext *dc)
 {
     tcg_gen_mov_tl(cpu_cc_src, src1);
     tcg_gen_movi_tl(cpu_cc_src2, src2);
     if (src2 == 0) {
-        tcg_gen_mov_tl(dst, src1);
-        gen_op_logic_cc(dst);
+        tcg_gen_mov_tl(cpu_cc_dst, src1);
+        tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
+        dc->cc_op = CC_OP_LOGIC;
     } else {
         tcg_gen_subi_tl(cpu_cc_dst, cpu_cc_src, src2);
-        gen_op_sub_cc2(dst);
+        tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUB);
+        dc->cc_op = CC_OP_SUB;
     }
+    tcg_gen_mov_tl(dst, cpu_cc_dst);
 }
 
 static inline void gen_op_sub_cc(TCGv dst, TCGv src1, TCGv src2)
@@ -681,19 +632,6 @@ static inline void gen_op_sub_cc(TCGv dst, TCGv src1, TCGv src2)
     tcg_gen_mov_tl(cpu_cc_src, src1);
     tcg_gen_mov_tl(cpu_cc_src2, src2);
     tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
-    gen_op_sub_cc2(dst);
-}
-
-static inline void gen_op_subx_cc2(TCGv dst)
-{
-    gen_cc_NZ_icc(cpu_cc_dst);
-    gen_cc_C_sub_icc(cpu_cc_dst, cpu_cc_src);
-    gen_cc_V_sub_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
-#ifdef TARGET_SPARC64
-    gen_cc_NZ_xcc(cpu_cc_dst);
-    gen_cc_C_sub_xcc(cpu_cc_dst, cpu_cc_src);
-    gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
-#endif
     tcg_gen_mov_tl(dst, cpu_cc_dst);
 }
 
@@ -703,14 +641,8 @@ static inline void gen_op_subxi_cc(TCGv dst, TCGv src1, target_long src2)
     tcg_gen_movi_tl(cpu_cc_src2, src2);
     gen_mov_reg_C(cpu_tmp0, cpu_psr);
     tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_tmp0);
-    gen_cc_clear_icc();
-    gen_cc_C_sub_icc(cpu_cc_dst, cpu_cc_src);
-#ifdef TARGET_SPARC64
-    gen_cc_clear_xcc();
-    gen_cc_C_sub_xcc(cpu_cc_dst, cpu_cc_src);
-#endif
     tcg_gen_subi_tl(cpu_cc_dst, cpu_cc_dst, src2);
-    gen_op_subx_cc2(dst);
+    tcg_gen_mov_tl(dst, cpu_cc_dst);
 }
 
 static inline void gen_op_subx_cc(TCGv dst, TCGv src1, TCGv src2)
@@ -719,14 +651,8 @@ static inline void gen_op_subx_cc(TCGv dst, TCGv src1, TCGv src2)
     tcg_gen_mov_tl(cpu_cc_src2, src2);
     gen_mov_reg_C(cpu_tmp0, cpu_psr);
     tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_tmp0);
-    gen_cc_clear_icc();
-    gen_cc_C_sub_icc(cpu_cc_dst, cpu_cc_src);
-#ifdef TARGET_SPARC64
-    gen_cc_clear_xcc();
-    gen_cc_C_sub_xcc(cpu_cc_dst, cpu_cc_src);
-#endif
     tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_dst, cpu_cc_src2);
-    gen_op_subx_cc2(dst);
+    tcg_gen_mov_tl(dst, cpu_cc_dst);
 }
 
 static inline void gen_op_tsub_cc(TCGv dst, TCGv src1, TCGv src2)
@@ -3161,9 +3087,9 @@ static void disas_sparc_insn(DisasContext * dc)
                             tcg_gen_and_tl(cpu_dst, cpu_src1, cpu_src2);
                         }
                         if (xop & 0x10) {
-                            gen_op_logic_cc(cpu_dst);
-                            tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
-                            dc->cc_op = CC_OP_FLAGS;
+                            tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
+                            tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
+                            dc->cc_op = CC_OP_LOGIC;
                         }
                         break;
                     case 0x2: /* or */
@@ -3174,9 +3100,9 @@ static void disas_sparc_insn(DisasContext * dc)
                             tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_src2);
                         }
                         if (xop & 0x10) {
-                            gen_op_logic_cc(cpu_dst);
-                            tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
-                            dc->cc_op = CC_OP_FLAGS;
+                            tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
+                            tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
+                            dc->cc_op = CC_OP_LOGIC;
                         }
                         break;
                     case 0x3: /* xor */
@@ -3187,26 +3113,24 @@ static void disas_sparc_insn(DisasContext * dc)
                             tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
                         }
                         if (xop & 0x10) {
-                            gen_op_logic_cc(cpu_dst);
-                            tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
-                            dc->cc_op = CC_OP_FLAGS;
+                            tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
+                            tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
+                            dc->cc_op = CC_OP_LOGIC;
                         }
                         break;
                     case 0x4: /* sub */
                         if (IS_IMM) {
                             simm = GET_FIELDs(insn, 19, 31);
                             if (xop & 0x10) {
-                                gen_op_subi_cc(cpu_dst, cpu_src1, simm);
-                                tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
-                                dc->cc_op = CC_OP_FLAGS;
+                                gen_op_subi_cc(cpu_dst, cpu_src1, simm, dc);
                             } else {
                                 tcg_gen_subi_tl(cpu_dst, cpu_src1, simm);
                             }
                         } else {
                             if (xop & 0x10) {
                                 gen_op_sub_cc(cpu_dst, cpu_src1, cpu_src2);
-                                tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
-                                dc->cc_op = CC_OP_FLAGS;
+                                tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUB);
+                                dc->cc_op = CC_OP_SUB;
                             } else {
                                 tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_src2);
                             }
@@ -3220,9 +3144,9 @@ static void disas_sparc_insn(DisasContext * dc)
                             tcg_gen_andc_tl(cpu_dst, cpu_src1, cpu_src2);
                         }
                         if (xop & 0x10) {
-                            gen_op_logic_cc(cpu_dst);
-                            tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
-                            dc->cc_op = CC_OP_FLAGS;
+                            tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
+                            tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
+                            dc->cc_op = CC_OP_LOGIC;
                         }
                         break;
                     case 0x6: /* orn */
@@ -3233,9 +3157,9 @@ static void disas_sparc_insn(DisasContext * dc)
                             tcg_gen_orc_tl(cpu_dst, cpu_src1, cpu_src2);
                         }
                         if (xop & 0x10) {
-                            gen_op_logic_cc(cpu_dst);
-                            tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
-                            dc->cc_op = CC_OP_FLAGS;
+                            tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
+                            tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
+                            dc->cc_op = CC_OP_LOGIC;
                         }
                         break;
                     case 0x7: /* xorn */
@@ -3247,9 +3171,9 @@ static void disas_sparc_insn(DisasContext * dc)
                             tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_tmp0);
                         }
                         if (xop & 0x10) {
-                            gen_op_logic_cc(cpu_dst);
-                            tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
-                            dc->cc_op = CC_OP_FLAGS;
+                            tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
+                            tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
+                            dc->cc_op = CC_OP_LOGIC;
                         }
                         break;
                     case 0x8: /* addx, V9 addc */
@@ -3258,8 +3182,8 @@ static void disas_sparc_insn(DisasContext * dc)
                             if (xop & 0x10) {
                                 gen_helper_compute_psr();
                                 gen_op_addxi_cc(cpu_dst, cpu_src1, simm);
-                                tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
-                                dc->cc_op = CC_OP_FLAGS;
+                                tcg_gen_movi_i32(cpu_cc_op, CC_OP_ADDX);
+                                dc->cc_op = CC_OP_ADDX;
                             } else {
                                 gen_helper_compute_psr();
                                 gen_mov_reg_C(cpu_tmp0, cpu_psr);
@@ -3270,8 +3194,8 @@ static void disas_sparc_insn(DisasContext * dc)
                             if (xop & 0x10) {
                                 gen_helper_compute_psr();
                                 gen_op_addx_cc(cpu_dst, cpu_src1, cpu_src2);
-                                tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
-                                dc->cc_op = CC_OP_FLAGS;
+                                tcg_gen_movi_i32(cpu_cc_op, CC_OP_ADDX);
+                                dc->cc_op = CC_OP_ADDX;
                             } else {
                                 gen_helper_compute_psr();
                                 gen_mov_reg_C(cpu_tmp0, cpu_psr);
@@ -3294,18 +3218,18 @@ static void disas_sparc_insn(DisasContext * dc)
                         CHECK_IU_FEATURE(dc, MUL);
                         gen_op_umul(cpu_dst, cpu_src1, cpu_src2);
                         if (xop & 0x10) {
-                            gen_op_logic_cc(cpu_dst);
-                            tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
-                            dc->cc_op = CC_OP_FLAGS;
+                            tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
+                            tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
+                            dc->cc_op = CC_OP_LOGIC;
                         }
                         break;
                     case 0xb: /* smul */
                         CHECK_IU_FEATURE(dc, MUL);
                         gen_op_smul(cpu_dst, cpu_src1, cpu_src2);
                         if (xop & 0x10) {
-                            gen_op_logic_cc(cpu_dst);
-                            tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
-                            dc->cc_op = CC_OP_FLAGS;
+                            tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
+                            tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
+                            dc->cc_op = CC_OP_LOGIC;
                         }
                         break;
                     case 0xc: /* subx, V9 subc */
@@ -3314,8 +3238,8 @@ static void disas_sparc_insn(DisasContext * dc)
                             if (xop & 0x10) {
                                 gen_helper_compute_psr();
                                 gen_op_subxi_cc(cpu_dst, cpu_src1, simm);
-                                tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
-                                dc->cc_op = CC_OP_FLAGS;
+                                tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUBX);
+                                dc->cc_op = CC_OP_SUBX;
                             } else {
                                 gen_helper_compute_psr();
                                 gen_mov_reg_C(cpu_tmp0, cpu_psr);
@@ -3326,8 +3250,8 @@ static void disas_sparc_insn(DisasContext * dc)
                             if (xop & 0x10) {
                                 gen_helper_compute_psr();
                                 gen_op_subx_cc(cpu_dst, cpu_src1, cpu_src2);
-                                tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
-                                dc->cc_op = CC_OP_FLAGS;
+                                tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUBX);
+                                dc->cc_op = CC_OP_SUBX;
                             } else {
                                 gen_helper_compute_psr();
                                 gen_mov_reg_C(cpu_tmp0, cpu_psr);