X-Git-Url: http://git.maemo.org/git/?a=blobdiff_plain;f=exec-all.h;h=f91e6460c34230dba7864aad0f810b322dce7b97;hb=73c632edc4e28d0a8cae3b34abf7ae46fa33bf1e;hp=943297755a5bebce591949886e2e6a340d253e2e;hpb=551bd27f22638c854c43d7e6417d549764311c31;p=qemu diff --git a/exec-all.h b/exec-all.h index 9432977..f91e646 100644 --- a/exec-all.h +++ b/exec-all.h @@ -15,9 +15,14 @@ * * You should have received a copy of the GNU Lesser General Public * License along with this library; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA */ +#ifndef _EXEC_ALL_H_ +#define _EXEC_ALL_H_ + +#include "qemu-common.h" + /* allow to see translation results - the slowdown should be negligible, so we leave it */ #define DEBUG_DISAS @@ -52,16 +57,10 @@ extern uint16_t gen_opc_icount[OPC_BUF_SIZE]; extern target_ulong gen_opc_jump_pc[2]; extern uint32_t gen_opc_hflags[OPC_BUF_SIZE]; -typedef void (GenOpFunc)(void); -typedef void (GenOpFunc1)(long); -typedef void (GenOpFunc2)(long, long); -typedef void (GenOpFunc3)(long, long, long); +#include "qemu-log.h" -extern FILE *logfile; -extern int loglevel; - -int gen_intermediate_code(CPUState *env, struct TranslationBlock *tb); -int gen_intermediate_code_pc(CPUState *env, struct TranslationBlock *tb); +void gen_intermediate_code(CPUState *env, struct TranslationBlock *tb); +void gen_intermediate_code_pc(CPUState *env, struct TranslationBlock *tb); void gen_pc_load(CPUState *env, struct TranslationBlock *tb, unsigned long searched_pc, int pc_pos, void *puc); @@ -81,6 +80,7 @@ TranslationBlock *tb_gen_code(CPUState *env, target_ulong pc, target_ulong cs_base, int flags, int cflags); void cpu_exec_init(CPUState *env); +void QEMU_NORETURN cpu_loop_exit(void); int page_unprotect(target_ulong address, unsigned long pc, void *puc); void tb_invalidate_phys_page_range(target_phys_addr_t start, target_phys_addr_t end, int is_cpu_write_access); @@ -115,7 +115,7 @@ static inline int tlb_set_page(CPUState *env1, target_ulong vaddr, #define CODE_GEN_AVG_BLOCK_SIZE 64 #endif -#if defined(__powerpc__) || defined(__x86_64__) || defined(__arm__) +#if defined(_ARCH_PPC) || defined(__x86_64__) || defined(__arm__) #define USE_DIRECT_JUMP #endif #if defined(__i386__) && !defined(_WIN32) @@ -190,39 +190,9 @@ extern int code_gen_max_blocks; #if defined(USE_DIRECT_JUMP) -#if defined(__powerpc__) -static inline void flush_icache_range(unsigned long start, unsigned long stop); -static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr) -{ - /* This must be in concord with INDEX_op_goto_tb inside tcg_out_op */ - uint32_t *ptr; - long disp = addr - jmp_addr; - unsigned long patch_size; - - ptr = (uint32_t *)jmp_addr; - - if ((disp << 6) >> 6 != disp) { - ptr[0] = 0x3c000000 | (addr >> 16); /* lis 0,addr@ha */ - ptr[1] = 0x60000000 | (addr & 0xffff); /* la 0,addr@l(0) */ - ptr[2] = 0x7c0903a6; /* mtctr 0 */ - ptr[3] = 0x4e800420; /* brctr */ - patch_size = 16; - } else { - /* patch the branch destination */ - if (disp != 16) { - *ptr = 0x48000000 | (disp & 0x03fffffc); /* b disp */ - patch_size = 4; - } else { - ptr[0] = 0x60000000; /* nop */ - ptr[1] = 0x60000000; - ptr[2] = 0x60000000; - ptr[3] = 0x60000000; - patch_size = 16; - } - } - /* flush icache */ - flush_icache_range(jmp_addr, jmp_addr + patch_size); -} +#if defined(_ARCH_PPC) +extern void ppc_tb_set_jmp_target(unsigned long jmp_addr, unsigned long addr); +#define tb_set_jmp_target1 ppc_tb_set_jmp_target #elif defined(__i386__) || defined(__x86_64__) static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr) { @@ -233,18 +203,26 @@ static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr #elif defined(__arm__) static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr) { +#if QEMU_GNUC_PREREQ(4, 1) + void __clear_cache(char *beg, char *end); +#else register unsigned long _beg __asm ("a1"); register unsigned long _end __asm ("a2"); register unsigned long _flg __asm ("a3"); +#endif /* we could use a ldr pc, [pc, #-4] kind of branch and avoid the flush */ *(uint32_t *)jmp_addr |= ((addr - (jmp_addr + 8)) >> 2) & 0xffffff; +#if QEMU_GNUC_PREREQ(4, 1) + __clear_cache((char *) jmp_addr, (char *) jmp_addr + 4); +#else /* flush icache */ _beg = jmp_addr; _end = jmp_addr + 4; _flg = 0; __asm __volatile__ ("swi 0x9f0002" : : "r" (_beg), "r" (_end), "r" (_flg)); +#endif } #endif @@ -287,24 +265,6 @@ static inline void tb_add_jump(TranslationBlock *tb, int n, TranslationBlock *tb_find_pc(unsigned long pc_ptr); -#ifndef offsetof -#define offsetof(type, field) ((size_t) &((type *)0)->field) -#endif - -#if defined(_WIN32) -#define ASM_DATA_SECTION ".section \".data\"\n" -#define ASM_PREVIOUS_SECTION ".section .text\n" -#elif defined(__APPLE__) -#define ASM_DATA_SECTION ".data\n" -#define ASM_PREVIOUS_SECTION ".text\n" -#else -#define ASM_DATA_SECTION ".section \".data\"\n" -#define ASM_PREVIOUS_SECTION ".previous\n" -#endif - -#define ASM_OP_LABEL_NAME(n, opname) \ - ASM_NAME(__op_label) #n "." ASM_NAME(opname) - extern CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4]; extern CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4]; extern void *io_mem_opaque[IO_MEM_NB_ENTRIES]; @@ -320,6 +280,8 @@ extern int tb_invalidated_flag; void tlb_fill(target_ulong addr, int is_write, int mmu_idx, void *retaddr); +#include "softmmu_defs.h" + #define ACCESS_TYPE (NB_MMU_MODES + 1) #define MEMSUFFIX _code #define env cpu_single_env @@ -354,6 +316,7 @@ static inline target_ulong get_phys_addr_code(CPUState *env1, target_ulong addr) static inline target_ulong get_phys_addr_code(CPUState *env1, target_ulong addr) { int mmu_idx, page_index, pd; + void *p; page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); mmu_idx = cpu_mmu_index(env1); @@ -364,12 +327,14 @@ static inline target_ulong get_phys_addr_code(CPUState *env1, target_ulong addr) pd = env1->tlb_table[mmu_idx][page_index].addr_code & ~TARGET_PAGE_MASK; if (pd > IO_MEM_ROM && !(pd & IO_MEM_ROMD)) { #if defined(TARGET_SPARC) || defined(TARGET_MIPS) - do_unassigned_access(addr, 0, 1, 0); + do_unassigned_access(addr, 0, 1, 0, 4); #else cpu_abort(env1, "Trying to execute code outside RAM or ROM at 0x" TARGET_FMT_lx "\n", addr); #endif } - return addr + env1->tlb_table[mmu_idx][page_index].addend - (unsigned long)phys_ram_base; + p = (void *)(unsigned long)addr + + env1->tlb_table[mmu_idx][page_index].addend; + return qemu_ram_addr_from_host(p); } /* Deterministic execution requires that IO only be performed on the last @@ -387,7 +352,7 @@ static inline int can_do_io(CPUState *env) } #endif -#ifdef USE_KQEMU +#ifdef CONFIG_KQEMU #define KQEMU_MODIFY_PAGE_MASK (0xff & ~(VGA_DIRTY_FLAG | CODE_DIRTY_FLAG)) #define MSR_QPI_COMMBASE 0xfabe0010 @@ -405,6 +370,9 @@ void kqemu_record_dump(void); extern uint32_t kqemu_comm_base; +extern ram_addr_t kqemu_phys_ram_size; +extern uint8_t *kqemu_phys_ram_base; + static inline int kqemu_is_ok(CPUState *env) { return(env->kqemu_enabled && @@ -418,3 +386,12 @@ static inline int kqemu_is_ok(CPUState *env) } #endif + +typedef void (CPUDebugExcpHandler)(CPUState *env); + +CPUDebugExcpHandler *cpu_set_debug_excp_handler(CPUDebugExcpHandler *handler); + +/* vl.c */ +extern int singlestep; + +#endif