X-Git-Url: http://git.maemo.org/git/?a=blobdiff_plain;f=hw%2Fppc405_uc.c;h=8dc33c7ec3f9947e0e222aaa0e3fcf7a98da30e3;hb=8217606e6edb49591b4a6fd5a0d1229cebe470a9;hp=329330a61ccb7ac432d64f8689dfcd020d05372f;hpb=aae9366a036b813d58fad2d99d28a2a478109f75;p=qemu

diff --git a/hw/ppc405_uc.c b/hw/ppc405_uc.c
index 329330a..8dc33c7 100644
--- a/hw/ppc405_uc.c
+++ b/hw/ppc405_uc.c
@@ -27,9 +27,7 @@
 #include "pc.h"
 #include "qemu-timer.h"
 #include "sysemu.h"
-
-extern int loglevel;
-extern FILE *logfile;
+#include "qemu-log.h"
 
 #define DEBUG_OPBA
 #define DEBUG_SDRAM
@@ -53,38 +51,38 @@ ram_addr_t ppc405_set_bootinfo (CPUState *env, ppc4xx_bd_info_t *bd,
         bdloc = 0x01000000UL - sizeof(struct ppc4xx_bd_info_t);
     else
         bdloc = bd->bi_memsize - sizeof(struct ppc4xx_bd_info_t);
-    stl_raw(phys_ram_base + bdloc + 0x00, bd->bi_memstart);
-    stl_raw(phys_ram_base + bdloc + 0x04, bd->bi_memsize);
-    stl_raw(phys_ram_base + bdloc + 0x08, bd->bi_flashstart);
-    stl_raw(phys_ram_base + bdloc + 0x0C, bd->bi_flashsize);
-    stl_raw(phys_ram_base + bdloc + 0x10, bd->bi_flashoffset);
-    stl_raw(phys_ram_base + bdloc + 0x14, bd->bi_sramstart);
-    stl_raw(phys_ram_base + bdloc + 0x18, bd->bi_sramsize);
-    stl_raw(phys_ram_base + bdloc + 0x1C, bd->bi_bootflags);
-    stl_raw(phys_ram_base + bdloc + 0x20, bd->bi_ipaddr);
+    stl_phys(bdloc + 0x00, bd->bi_memstart);
+    stl_phys(bdloc + 0x04, bd->bi_memsize);
+    stl_phys(bdloc + 0x08, bd->bi_flashstart);
+    stl_phys(bdloc + 0x0C, bd->bi_flashsize);
+    stl_phys(bdloc + 0x10, bd->bi_flashoffset);
+    stl_phys(bdloc + 0x14, bd->bi_sramstart);
+    stl_phys(bdloc + 0x18, bd->bi_sramsize);
+    stl_phys(bdloc + 0x1C, bd->bi_bootflags);
+    stl_phys(bdloc + 0x20, bd->bi_ipaddr);
     for (i = 0; i < 6; i++)
-        stb_raw(phys_ram_base + bdloc + 0x24 + i, bd->bi_enetaddr[i]);
-    stw_raw(phys_ram_base + bdloc + 0x2A, bd->bi_ethspeed);
-    stl_raw(phys_ram_base + bdloc + 0x2C, bd->bi_intfreq);
-    stl_raw(phys_ram_base + bdloc + 0x30, bd->bi_busfreq);
-    stl_raw(phys_ram_base + bdloc + 0x34, bd->bi_baudrate);
+        stb_phys(bdloc + 0x24 + i, bd->bi_enetaddr[i]);
+    stw_phys(bdloc + 0x2A, bd->bi_ethspeed);
+    stl_phys(bdloc + 0x2C, bd->bi_intfreq);
+    stl_phys(bdloc + 0x30, bd->bi_busfreq);
+    stl_phys(bdloc + 0x34, bd->bi_baudrate);
     for (i = 0; i < 4; i++)
-        stb_raw(phys_ram_base + bdloc + 0x38 + i, bd->bi_s_version[i]);
+        stb_phys(bdloc + 0x38 + i, bd->bi_s_version[i]);
     for (i = 0; i < 32; i++)
-        stb_raw(phys_ram_base + bdloc + 0x3C + i, bd->bi_s_version[i]);
-    stl_raw(phys_ram_base + bdloc + 0x5C, bd->bi_plb_busfreq);
-    stl_raw(phys_ram_base + bdloc + 0x60, bd->bi_pci_busfreq);
+        stb_phys(bdloc + 0x3C + i, bd->bi_s_version[i]);
+    stl_phys(bdloc + 0x5C, bd->bi_plb_busfreq);
+    stl_phys(bdloc + 0x60, bd->bi_pci_busfreq);
     for (i = 0; i < 6; i++)
-        stb_raw(phys_ram_base + bdloc + 0x64 + i, bd->bi_pci_enetaddr[i]);
+        stb_phys(bdloc + 0x64 + i, bd->bi_pci_enetaddr[i]);
     n = 0x6A;
     if (flags & 0x00000001) {
         for (i = 0; i < 6; i++)
-            stb_raw(phys_ram_base + bdloc + n++, bd->bi_pci_enetaddr2[i]);
+            stb_phys(bdloc + n++, bd->bi_pci_enetaddr2[i]);
     }
-    stl_raw(phys_ram_base + bdloc + n, bd->bi_opbfreq);
+    stl_phys(bdloc + n, bd->bi_opbfreq);
     n += 4;
     for (i = 0; i < 2; i++) {
-        stl_raw(phys_ram_base + bdloc + n, bd->bi_iic_fast[i]);
+        stl_phys(bdloc + n, bd->bi_iic_fast[i]);
         n += 4;
     }
 
@@ -171,13 +169,11 @@ void ppc4xx_plb_init (CPUState *env)
     ppc4xx_plb_t *plb;
 
     plb = qemu_mallocz(sizeof(ppc4xx_plb_t));
-    if (plb != NULL) {
-        ppc_dcr_register(env, PLB0_ACR, plb, &dcr_read_plb, &dcr_write_plb);
-        ppc_dcr_register(env, PLB0_BEAR, plb, &dcr_read_plb, &dcr_write_plb);
-        ppc_dcr_register(env, PLB0_BESR, plb, &dcr_read_plb, &dcr_write_plb);
-        ppc4xx_plb_reset(plb);
-        qemu_register_reset(ppc4xx_plb_reset, plb);
-    }
+    ppc_dcr_register(env, PLB0_ACR, plb, &dcr_read_plb, &dcr_write_plb);
+    ppc_dcr_register(env, PLB0_BEAR, plb, &dcr_read_plb, &dcr_write_plb);
+    ppc_dcr_register(env, PLB0_BESR, plb, &dcr_read_plb, &dcr_write_plb);
+    ppc4xx_plb_reset(plb);
+    qemu_register_reset(ppc4xx_plb_reset, 0, plb);
 }
 
 /*****************************************************************************/
@@ -250,13 +246,11 @@ void ppc4xx_pob_init (CPUState *env)
     ppc4xx_pob_t *pob;
 
     pob = qemu_mallocz(sizeof(ppc4xx_pob_t));
-    if (pob != NULL) {
-        ppc_dcr_register(env, POB0_BEAR, pob, &dcr_read_pob, &dcr_write_pob);
-        ppc_dcr_register(env, POB0_BESR0, pob, &dcr_read_pob, &dcr_write_pob);
-        ppc_dcr_register(env, POB0_BESR1, pob, &dcr_read_pob, &dcr_write_pob);
-        qemu_register_reset(ppc4xx_pob_reset, pob);
-        ppc4xx_pob_reset(env);
-    }
+    ppc_dcr_register(env, POB0_BEAR, pob, &dcr_read_pob, &dcr_write_pob);
+    ppc_dcr_register(env, POB0_BESR0, pob, &dcr_read_pob, &dcr_write_pob);
+    ppc_dcr_register(env, POB0_BESR1, pob, &dcr_read_pob, &dcr_write_pob);
+    qemu_register_reset(ppc4xx_pob_reset, 0, pob);
+    ppc4xx_pob_reset(env);
 }
 
 /*****************************************************************************/
@@ -386,16 +380,14 @@ void ppc4xx_opba_init (CPUState *env, ppc4xx_mmio_t *mmio,
     ppc4xx_opba_t *opba;
 
     opba = qemu_mallocz(sizeof(ppc4xx_opba_t));
-    if (opba != NULL) {
-        opba->base = offset;
+    opba->base = offset;
 #ifdef DEBUG_OPBA
-        printf("%s: offset " PADDRX "\n", __func__, offset);
+    printf("%s: offset " PADDRX "\n", __func__, offset);
 #endif
-        ppc4xx_mmio_register(env, mmio, offset, 0x002,
-                             opba_read, opba_write, opba);
-        qemu_register_reset(ppc4xx_opba_reset, opba);
-        ppc4xx_opba_reset(opba);
-    }
+    ppc4xx_mmio_register(env, mmio, offset, 0x002,
+                         opba_read, opba_write, opba);
+    qemu_register_reset(ppc4xx_opba_reset, 0, opba);
+    ppc4xx_opba_reset(opba);
 }
 
 /*****************************************************************************/
@@ -403,347 +395,6 @@ void ppc4xx_opba_init (CPUState *env, ppc4xx_mmio_t *mmio,
 /* XXX: TODO */
 
 /*****************************************************************************/
-/* SDRAM controller */
-typedef struct ppc4xx_sdram_t ppc4xx_sdram_t;
-struct ppc4xx_sdram_t {
-    uint32_t addr;
-    int nbanks;
-    target_phys_addr_t ram_bases[4];
-    target_phys_addr_t ram_sizes[4];
-    uint32_t besr0;
-    uint32_t besr1;
-    uint32_t bear;
-    uint32_t cfg;
-    uint32_t status;
-    uint32_t rtr;
-    uint32_t pmit;
-    uint32_t bcr[4];
-    uint32_t tr;
-    uint32_t ecccfg;
-    uint32_t eccesr;
-    qemu_irq irq;
-};
-
-enum {
-    SDRAM0_CFGADDR = 0x010,
-    SDRAM0_CFGDATA = 0x011,
-};
-
-/* XXX: TOFIX: some patches have made this code become inconsistent:
- *      there are type inconsistencies, mixing target_phys_addr_t, target_ulong
- *      and uint32_t
- */
-static uint32_t sdram_bcr (target_phys_addr_t ram_base,
-                           target_phys_addr_t ram_size)
-{
-    uint32_t bcr;
-
-    switch (ram_size) {
-    case (4 * 1024 * 1024):
-        bcr = 0x00000000;
-        break;
-    case (8 * 1024 * 1024):
-        bcr = 0x00020000;
-        break;
-    case (16 * 1024 * 1024):
-        bcr = 0x00040000;
-        break;
-    case (32 * 1024 * 1024):
-        bcr = 0x00060000;
-        break;
-    case (64 * 1024 * 1024):
-        bcr = 0x00080000;
-        break;
-    case (128 * 1024 * 1024):
-        bcr = 0x000A0000;
-        break;
-    case (256 * 1024 * 1024):
-        bcr = 0x000C0000;
-        break;
-    default:
-        printf("%s: invalid RAM size " PADDRX "\n", __func__, ram_size);
-        return 0x00000000;
-    }
-    bcr |= ram_base & 0xFF800000;
-    bcr |= 1;
-
-    return bcr;
-}
-
-static always_inline target_phys_addr_t sdram_base (uint32_t bcr)
-{
-    return bcr & 0xFF800000;
-}
-
-static target_ulong sdram_size (uint32_t bcr)
-{
-    target_ulong size;
-    int sh;
-
-    sh = (bcr >> 17) & 0x7;
-    if (sh == 7)
-        size = -1;
-    else
-        size = (4 * 1024 * 1024) << sh;
-
-    return size;
-}
-
-static void sdram_set_bcr (uint32_t *bcrp, uint32_t bcr, int enabled)
-{
-    if (*bcrp & 0x00000001) {
-        /* Unmap RAM */
-#ifdef DEBUG_SDRAM
-        printf("%s: unmap RAM area " PADDRX " " ADDRX "\n",
-               __func__, sdram_base(*bcrp), sdram_size(*bcrp));
-#endif
-        cpu_register_physical_memory(sdram_base(*bcrp), sdram_size(*bcrp),
-                                     IO_MEM_UNASSIGNED);
-    }
-    *bcrp = bcr & 0xFFDEE001;
-    if (enabled && (bcr & 0x00000001)) {
-#ifdef DEBUG_SDRAM
-        printf("%s: Map RAM area " PADDRX " " ADDRX "\n",
-               __func__, sdram_base(bcr), sdram_size(bcr));
-#endif
-        cpu_register_physical_memory(sdram_base(bcr), sdram_size(bcr),
-                                     sdram_base(bcr) | IO_MEM_RAM);
-    }
-}
-
-static void sdram_map_bcr (ppc4xx_sdram_t *sdram)
-{
-    int i;
-
-    for (i = 0; i < sdram->nbanks; i++) {
-        if (sdram->ram_sizes[i] != 0) {
-            sdram_set_bcr(&sdram->bcr[i],
-                          sdram_bcr(sdram->ram_bases[i], sdram->ram_sizes[i]),
-                          1);
-        } else {
-            sdram_set_bcr(&sdram->bcr[i], 0x00000000, 0);
-        }
-    }
-}
-
-static void sdram_unmap_bcr (ppc4xx_sdram_t *sdram)
-{
-    int i;
-
-    for (i = 0; i < sdram->nbanks; i++) {
-#ifdef DEBUG_SDRAM
-        printf("%s: Unmap RAM area " PADDRX " " ADDRX "\n",
-               __func__, sdram_base(sdram->bcr[i]), sdram_size(sdram->bcr[i]));
-#endif
-        cpu_register_physical_memory(sdram_base(sdram->bcr[i]),
-                                     sdram_size(sdram->bcr[i]),
-                                     IO_MEM_UNASSIGNED);
-    }
-}
-
-static target_ulong dcr_read_sdram (void *opaque, int dcrn)
-{
-    ppc4xx_sdram_t *sdram;
-    target_ulong ret;
-
-    sdram = opaque;
-    switch (dcrn) {
-    case SDRAM0_CFGADDR:
-        ret = sdram->addr;
-        break;
-    case SDRAM0_CFGDATA:
-        switch (sdram->addr) {
-        case 0x00: /* SDRAM_BESR0 */
-            ret = sdram->besr0;
-            break;
-        case 0x08: /* SDRAM_BESR1 */
-            ret = sdram->besr1;
-            break;
-        case 0x10: /* SDRAM_BEAR */
-            ret = sdram->bear;
-            break;
-        case 0x20: /* SDRAM_CFG */
-            ret = sdram->cfg;
-            break;
-        case 0x24: /* SDRAM_STATUS */
-            ret = sdram->status;
-            break;
-        case 0x30: /* SDRAM_RTR */
-            ret = sdram->rtr;
-            break;
-        case 0x34: /* SDRAM_PMIT */
-            ret = sdram->pmit;
-            break;
-        case 0x40: /* SDRAM_B0CR */
-            ret = sdram->bcr[0];
-            break;
-        case 0x44: /* SDRAM_B1CR */
-            ret = sdram->bcr[1];
-            break;
-        case 0x48: /* SDRAM_B2CR */
-            ret = sdram->bcr[2];
-            break;
-        case 0x4C: /* SDRAM_B3CR */
-            ret = sdram->bcr[3];
-            break;
-        case 0x80: /* SDRAM_TR */
-            ret = -1; /* ? */
-            break;
-        case 0x94: /* SDRAM_ECCCFG */
-            ret = sdram->ecccfg;
-            break;
-        case 0x98: /* SDRAM_ECCESR */
-            ret = sdram->eccesr;
-            break;
-        default: /* Error */
-            ret = -1;
-            break;
-        }
-        break;
-    default:
-        /* Avoid gcc warning */
-        ret = 0x00000000;
-        break;
-    }
-
-    return ret;
-}
-
-static void dcr_write_sdram (void *opaque, int dcrn, target_ulong val)
-{
-    ppc4xx_sdram_t *sdram;
-
-    sdram = opaque;
-    switch (dcrn) {
-    case SDRAM0_CFGADDR:
-        sdram->addr = val;
-        break;
-    case SDRAM0_CFGDATA:
-        switch (sdram->addr) {
-        case 0x00: /* SDRAM_BESR0 */
-            sdram->besr0 &= ~val;
-            break;
-        case 0x08: /* SDRAM_BESR1 */
-            sdram->besr1 &= ~val;
-            break;
-        case 0x10: /* SDRAM_BEAR */
-            sdram->bear = val;
-            break;
-        case 0x20: /* SDRAM_CFG */
-            val &= 0xFFE00000;
-            if (!(sdram->cfg & 0x80000000) && (val & 0x80000000)) {
-#ifdef DEBUG_SDRAM
-                printf("%s: enable SDRAM controller\n", __func__);
-#endif
-                /* validate all RAM mappings */
-                sdram_map_bcr(sdram);
-                sdram->status &= ~0x80000000;
-            } else if ((sdram->cfg & 0x80000000) && !(val & 0x80000000)) {
-#ifdef DEBUG_SDRAM
-                printf("%s: disable SDRAM controller\n", __func__);
-#endif
-                /* invalidate all RAM mappings */
-                sdram_unmap_bcr(sdram);
-                sdram->status |= 0x80000000;
-            }
-            if (!(sdram->cfg & 0x40000000) && (val & 0x40000000))
-                sdram->status |= 0x40000000;
-            else if ((sdram->cfg & 0x40000000) && !(val & 0x40000000))
-                sdram->status &= ~0x40000000;
-            sdram->cfg = val;
-            break;
-        case 0x24: /* SDRAM_STATUS */
-            /* Read-only register */
-            break;
-        case 0x30: /* SDRAM_RTR */
-            sdram->rtr = val & 0x3FF80000;
-            break;
-        case 0x34: /* SDRAM_PMIT */
-            sdram->pmit = (val & 0xF8000000) | 0x07C00000;
-            break;
-        case 0x40: /* SDRAM_B0CR */
-            sdram_set_bcr(&sdram->bcr[0], val, sdram->cfg & 0x80000000);
-            break;
-        case 0x44: /* SDRAM_B1CR */
-            sdram_set_bcr(&sdram->bcr[1], val, sdram->cfg & 0x80000000);
-            break;
-        case 0x48: /* SDRAM_B2CR */
-            sdram_set_bcr(&sdram->bcr[2], val, sdram->cfg & 0x80000000);
-            break;
-        case 0x4C: /* SDRAM_B3CR */
-            sdram_set_bcr(&sdram->bcr[3], val, sdram->cfg & 0x80000000);
-            break;
-        case 0x80: /* SDRAM_TR */
-            sdram->tr = val & 0x018FC01F;
-            break;
-        case 0x94: /* SDRAM_ECCCFG */
-            sdram->ecccfg = val & 0x00F00000;
-            break;
-        case 0x98: /* SDRAM_ECCESR */
-            val &= 0xFFF0F000;
-            if (sdram->eccesr == 0 && val != 0)
-                qemu_irq_raise(sdram->irq);
-            else if (sdram->eccesr != 0 && val == 0)
-                qemu_irq_lower(sdram->irq);
-            sdram->eccesr = val;
-            break;
-        default: /* Error */
-            break;
-        }
-        break;
-    }
-}
-
-static void sdram_reset (void *opaque)
-{
-    ppc4xx_sdram_t *sdram;
-
-    sdram = opaque;
-    sdram->addr = 0x00000000;
-    sdram->bear = 0x00000000;
-    sdram->besr0 = 0x00000000; /* No error */
-    sdram->besr1 = 0x00000000; /* No error */
-    sdram->cfg = 0x00000000;
-    sdram->ecccfg = 0x00000000; /* No ECC */
-    sdram->eccesr = 0x00000000; /* No error */
-    sdram->pmit = 0x07C00000;
-    sdram->rtr = 0x05F00000;
-    sdram->tr = 0x00854009;
-    /* We pre-initialize RAM banks */
-    sdram->status = 0x00000000;
-    sdram->cfg = 0x00800000;
-    sdram_unmap_bcr(sdram);
-}
-
-void ppc405_sdram_init (CPUState *env, qemu_irq irq, int nbanks,
-                        target_phys_addr_t *ram_bases,
-                        target_phys_addr_t *ram_sizes,
-                        int do_init)
-{
-    ppc4xx_sdram_t *sdram;
-
-    sdram = qemu_mallocz(sizeof(ppc4xx_sdram_t));
-    if (sdram != NULL) {
-        sdram->irq = irq;
-        sdram->nbanks = nbanks;
-        memset(sdram->ram_bases, 0, 4 * sizeof(target_phys_addr_t));
-        memcpy(sdram->ram_bases, ram_bases,
-               nbanks * sizeof(target_phys_addr_t));
-        memset(sdram->ram_sizes, 0, 4 * sizeof(target_phys_addr_t));
-        memcpy(sdram->ram_sizes, ram_sizes,
-               nbanks * sizeof(target_phys_addr_t));
-        sdram_reset(sdram);
-        qemu_register_reset(&sdram_reset, sdram);
-        ppc_dcr_register(env, SDRAM0_CFGADDR,
-                         sdram, &dcr_read_sdram, &dcr_write_sdram);
-        ppc_dcr_register(env, SDRAM0_CFGDATA,
-                         sdram, &dcr_read_sdram, &dcr_write_sdram);
-        if (do_init)
-            sdram_map_bcr(sdram);
-    }
-}
-
-/*****************************************************************************/
 /* Peripheral controller */
 typedef struct ppc4xx_ebc_t ppc4xx_ebc_t;
 struct ppc4xx_ebc_t {
@@ -928,14 +579,12 @@ void ppc405_ebc_init (CPUState *env)
     ppc4xx_ebc_t *ebc;
 
     ebc = qemu_mallocz(sizeof(ppc4xx_ebc_t));
-    if (ebc != NULL) {
-        ebc_reset(ebc);
-        qemu_register_reset(&ebc_reset, ebc);
-        ppc_dcr_register(env, EBC0_CFGADDR,
-                         ebc, &dcr_read_ebc, &dcr_write_ebc);
-        ppc_dcr_register(env, EBC0_CFGDATA,
-                         ebc, &dcr_read_ebc, &dcr_write_ebc);
-    }
+    ebc_reset(ebc);
+    qemu_register_reset(&ebc_reset, 0, ebc);
+    ppc_dcr_register(env, EBC0_CFGADDR,
+                     ebc, &dcr_read_ebc, &dcr_write_ebc);
+    ppc_dcr_register(env, EBC0_CFGDATA,
+                     ebc, &dcr_read_ebc, &dcr_write_ebc);
 }
 
 /*****************************************************************************/
@@ -1021,59 +670,57 @@ void ppc405_dma_init (CPUState *env, qemu_irq irqs[4])
     ppc405_dma_t *dma;
 
     dma = qemu_mallocz(sizeof(ppc405_dma_t));
-    if (dma != NULL) {
-        memcpy(dma->irqs, irqs, 4 * sizeof(qemu_irq));
-        ppc405_dma_reset(dma);
-        qemu_register_reset(&ppc405_dma_reset, dma);
-        ppc_dcr_register(env, DMA0_CR0,
-                         dma, &dcr_read_dma, &dcr_write_dma);
-        ppc_dcr_register(env, DMA0_CT0,
-                         dma, &dcr_read_dma, &dcr_write_dma);
-        ppc_dcr_register(env, DMA0_DA0,
-                         dma, &dcr_read_dma, &dcr_write_dma);
-        ppc_dcr_register(env, DMA0_SA0,
-                         dma, &dcr_read_dma, &dcr_write_dma);
-        ppc_dcr_register(env, DMA0_SG0,
-                         dma, &dcr_read_dma, &dcr_write_dma);
-        ppc_dcr_register(env, DMA0_CR1,
-                         dma, &dcr_read_dma, &dcr_write_dma);
-        ppc_dcr_register(env, DMA0_CT1,
-                         dma, &dcr_read_dma, &dcr_write_dma);
-        ppc_dcr_register(env, DMA0_DA1,
-                         dma, &dcr_read_dma, &dcr_write_dma);
-        ppc_dcr_register(env, DMA0_SA1,
-                         dma, &dcr_read_dma, &dcr_write_dma);
-        ppc_dcr_register(env, DMA0_SG1,
-                         dma, &dcr_read_dma, &dcr_write_dma);
-        ppc_dcr_register(env, DMA0_CR2,
-                         dma, &dcr_read_dma, &dcr_write_dma);
-        ppc_dcr_register(env, DMA0_CT2,
-                         dma, &dcr_read_dma, &dcr_write_dma);
-        ppc_dcr_register(env, DMA0_DA2,
-                         dma, &dcr_read_dma, &dcr_write_dma);
-        ppc_dcr_register(env, DMA0_SA2,
-                         dma, &dcr_read_dma, &dcr_write_dma);
-        ppc_dcr_register(env, DMA0_SG2,
-                         dma, &dcr_read_dma, &dcr_write_dma);
-        ppc_dcr_register(env, DMA0_CR3,
-                         dma, &dcr_read_dma, &dcr_write_dma);
-        ppc_dcr_register(env, DMA0_CT3,
-                         dma, &dcr_read_dma, &dcr_write_dma);
-        ppc_dcr_register(env, DMA0_DA3,
-                         dma, &dcr_read_dma, &dcr_write_dma);
-        ppc_dcr_register(env, DMA0_SA3,
-                         dma, &dcr_read_dma, &dcr_write_dma);
-        ppc_dcr_register(env, DMA0_SG3,
-                         dma, &dcr_read_dma, &dcr_write_dma);
-        ppc_dcr_register(env, DMA0_SR,
-                         dma, &dcr_read_dma, &dcr_write_dma);
-        ppc_dcr_register(env, DMA0_SGC,
-                         dma, &dcr_read_dma, &dcr_write_dma);
-        ppc_dcr_register(env, DMA0_SLP,
-                         dma, &dcr_read_dma, &dcr_write_dma);
-        ppc_dcr_register(env, DMA0_POL,
-                         dma, &dcr_read_dma, &dcr_write_dma);
-    }
+    memcpy(dma->irqs, irqs, 4 * sizeof(qemu_irq));
+    ppc405_dma_reset(dma);
+    qemu_register_reset(&ppc405_dma_reset, 0, dma);
+    ppc_dcr_register(env, DMA0_CR0,
+                     dma, &dcr_read_dma, &dcr_write_dma);
+    ppc_dcr_register(env, DMA0_CT0,
+                     dma, &dcr_read_dma, &dcr_write_dma);
+    ppc_dcr_register(env, DMA0_DA0,
+                     dma, &dcr_read_dma, &dcr_write_dma);
+    ppc_dcr_register(env, DMA0_SA0,
+                     dma, &dcr_read_dma, &dcr_write_dma);
+    ppc_dcr_register(env, DMA0_SG0,
+                     dma, &dcr_read_dma, &dcr_write_dma);
+    ppc_dcr_register(env, DMA0_CR1,
+                     dma, &dcr_read_dma, &dcr_write_dma);
+    ppc_dcr_register(env, DMA0_CT1,
+                     dma, &dcr_read_dma, &dcr_write_dma);
+    ppc_dcr_register(env, DMA0_DA1,
+                     dma, &dcr_read_dma, &dcr_write_dma);
+    ppc_dcr_register(env, DMA0_SA1,
+                     dma, &dcr_read_dma, &dcr_write_dma);
+    ppc_dcr_register(env, DMA0_SG1,
+                     dma, &dcr_read_dma, &dcr_write_dma);
+    ppc_dcr_register(env, DMA0_CR2,
+                     dma, &dcr_read_dma, &dcr_write_dma);
+    ppc_dcr_register(env, DMA0_CT2,
+                     dma, &dcr_read_dma, &dcr_write_dma);
+    ppc_dcr_register(env, DMA0_DA2,
+                     dma, &dcr_read_dma, &dcr_write_dma);
+    ppc_dcr_register(env, DMA0_SA2,
+                     dma, &dcr_read_dma, &dcr_write_dma);
+    ppc_dcr_register(env, DMA0_SG2,
+                     dma, &dcr_read_dma, &dcr_write_dma);
+    ppc_dcr_register(env, DMA0_CR3,
+                     dma, &dcr_read_dma, &dcr_write_dma);
+    ppc_dcr_register(env, DMA0_CT3,
+                     dma, &dcr_read_dma, &dcr_write_dma);
+    ppc_dcr_register(env, DMA0_DA3,
+                     dma, &dcr_read_dma, &dcr_write_dma);
+    ppc_dcr_register(env, DMA0_SA3,
+                     dma, &dcr_read_dma, &dcr_write_dma);
+    ppc_dcr_register(env, DMA0_SG3,
+                     dma, &dcr_read_dma, &dcr_write_dma);
+    ppc_dcr_register(env, DMA0_SR,
+                     dma, &dcr_read_dma, &dcr_write_dma);
+    ppc_dcr_register(env, DMA0_SGC,
+                     dma, &dcr_read_dma, &dcr_write_dma);
+    ppc_dcr_register(env, DMA0_SLP,
+                     dma, &dcr_read_dma, &dcr_write_dma);
+    ppc_dcr_register(env, DMA0_POL,
+                     dma, &dcr_read_dma, &dcr_write_dma);
 }
 
 /*****************************************************************************/
@@ -1188,16 +835,14 @@ void ppc405_gpio_init (CPUState *env, ppc4xx_mmio_t *mmio,
     ppc405_gpio_t *gpio;
 
     gpio = qemu_mallocz(sizeof(ppc405_gpio_t));
-    if (gpio != NULL) {
-        gpio->base = offset;
-        ppc405_gpio_reset(gpio);
-        qemu_register_reset(&ppc405_gpio_reset, gpio);
+    gpio->base = offset;
+    ppc405_gpio_reset(gpio);
+    qemu_register_reset(&ppc405_gpio_reset, 0, gpio);
 #ifdef DEBUG_GPIO
-        printf("%s: offset " PADDRX "\n", __func__, offset);
+    printf("%s: offset " PADDRX "\n", __func__, offset);
 #endif
-        ppc4xx_mmio_register(env, mmio, offset, 0x038,
-                             ppc405_gpio_read, ppc405_gpio_write, gpio);
-    }
+    ppc4xx_mmio_register(env, mmio, offset, 0x038,
+                         ppc405_gpio_read, ppc405_gpio_write, gpio);
 }
 
 /*****************************************************************************/
@@ -1223,7 +868,7 @@ void ppc405_serial_init (CPUState *env, ppc4xx_mmio_t *mmio,
 #ifdef DEBUG_SERIAL
     printf("%s: offset " PADDRX "\n", __func__, offset);
 #endif
-    serial = serial_mm_init(offset, 0, irq, chr, 0);
+    serial = serial_mm_init(offset, 0, irq, 399193, chr, 0);
     ppc4xx_mmio_register(env, mmio, offset, 0x008,
                          serial_mm_read, serial_mm_write, serial);
 }
@@ -1376,24 +1021,22 @@ static void ocm_reset (void *opaque)
     ocm->dsacntl = dsacntl;
 }
 
-void ppc405_ocm_init (CPUState *env, unsigned long offset)
+void ppc405_ocm_init (CPUState *env)
 {
     ppc405_ocm_t *ocm;
 
     ocm = qemu_mallocz(sizeof(ppc405_ocm_t));
-    if (ocm != NULL) {
-        ocm->offset = offset;
-        ocm_reset(ocm);
-        qemu_register_reset(&ocm_reset, ocm);
-        ppc_dcr_register(env, OCM0_ISARC,
-                         ocm, &dcr_read_ocm, &dcr_write_ocm);
-        ppc_dcr_register(env, OCM0_ISACNTL,
-                         ocm, &dcr_read_ocm, &dcr_write_ocm);
-        ppc_dcr_register(env, OCM0_DSARC,
-                         ocm, &dcr_read_ocm, &dcr_write_ocm);
-        ppc_dcr_register(env, OCM0_DSACNTL,
-                         ocm, &dcr_read_ocm, &dcr_write_ocm);
-    }
+    ocm->offset = qemu_ram_alloc(4096);
+    ocm_reset(ocm);
+    qemu_register_reset(&ocm_reset, 0, ocm);
+    ppc_dcr_register(env, OCM0_ISARC,
+                     ocm, &dcr_read_ocm, &dcr_write_ocm);
+    ppc_dcr_register(env, OCM0_ISACNTL,
+                     ocm, &dcr_read_ocm, &dcr_write_ocm);
+    ppc_dcr_register(env, OCM0_DSARC,
+                     ocm, &dcr_read_ocm, &dcr_write_ocm);
+    ppc_dcr_register(env, OCM0_DSACNTL,
+                     ocm, &dcr_read_ocm, &dcr_write_ocm);
 }
 
 /*****************************************************************************/
@@ -1629,17 +1272,15 @@ void ppc405_i2c_init (CPUState *env, ppc4xx_mmio_t *mmio,
     ppc4xx_i2c_t *i2c;
 
     i2c = qemu_mallocz(sizeof(ppc4xx_i2c_t));
-    if (i2c != NULL) {
-        i2c->base = offset;
-        i2c->irq = irq;
-        ppc4xx_i2c_reset(i2c);
+    i2c->base = offset;
+    i2c->irq = irq;
+    ppc4xx_i2c_reset(i2c);
 #ifdef DEBUG_I2C
-        printf("%s: offset " PADDRX "\n", __func__, offset);
+    printf("%s: offset " PADDRX "\n", __func__, offset);
 #endif
-        ppc4xx_mmio_register(env, mmio, offset, 0x011,
-                             i2c_read, i2c_write, i2c);
-        qemu_register_reset(ppc4xx_i2c_reset, i2c);
-    }
+    ppc4xx_mmio_register(env, mmio, offset, 0x011,
+                         i2c_read, i2c_write, i2c);
+    qemu_register_reset(ppc4xx_i2c_reset, 0, i2c);
 }
 
 /*****************************************************************************/
@@ -1911,19 +1552,17 @@ void ppc4xx_gpt_init (CPUState *env, ppc4xx_mmio_t *mmio,
     int i;
 
     gpt = qemu_mallocz(sizeof(ppc4xx_gpt_t));
-    if (gpt != NULL) {
-        gpt->base = offset;
-        for (i = 0; i < 5; i++)
-            gpt->irqs[i] = irqs[i];
-        gpt->timer = qemu_new_timer(vm_clock, &ppc4xx_gpt_cb, gpt);
-        ppc4xx_gpt_reset(gpt);
+    gpt->base = offset;
+    for (i = 0; i < 5; i++)
+        gpt->irqs[i] = irqs[i];
+    gpt->timer = qemu_new_timer(vm_clock, &ppc4xx_gpt_cb, gpt);
+    ppc4xx_gpt_reset(gpt);
 #ifdef DEBUG_GPT
-        printf("%s: offset " PADDRX "\n", __func__, offset);
+    printf("%s: offset " PADDRX "\n", __func__, offset);
 #endif
-        ppc4xx_mmio_register(env, mmio, offset, 0x0D4,
-                             gpt_read, gpt_write, gpt);
-        qemu_register_reset(ppc4xx_gpt_reset, gpt);
-    }
+    ppc4xx_mmio_register(env, mmio, offset, 0x0D4,
+                         gpt_read, gpt_write, gpt);
+    qemu_register_reset(ppc4xx_gpt_reset, 0, gpt);
 }
 
 /*****************************************************************************/
@@ -2145,50 +1784,48 @@ void ppc405_mal_init (CPUState *env, qemu_irq irqs[4])
     int i;
 
     mal = qemu_mallocz(sizeof(ppc40x_mal_t));
-    if (mal != NULL) {
-        for (i = 0; i < 4; i++)
-            mal->irqs[i] = irqs[i];
-        ppc40x_mal_reset(mal);
-        qemu_register_reset(&ppc40x_mal_reset, mal);
-        ppc_dcr_register(env, MAL0_CFG,
-                         mal, &dcr_read_mal, &dcr_write_mal);
-        ppc_dcr_register(env, MAL0_ESR,
-                         mal, &dcr_read_mal, &dcr_write_mal);
-        ppc_dcr_register(env, MAL0_IER,
-                         mal, &dcr_read_mal, &dcr_write_mal);
-        ppc_dcr_register(env, MAL0_TXCASR,
-                         mal, &dcr_read_mal, &dcr_write_mal);
-        ppc_dcr_register(env, MAL0_TXCARR,
-                         mal, &dcr_read_mal, &dcr_write_mal);
-        ppc_dcr_register(env, MAL0_TXEOBISR,
-                         mal, &dcr_read_mal, &dcr_write_mal);
-        ppc_dcr_register(env, MAL0_TXDEIR,
-                         mal, &dcr_read_mal, &dcr_write_mal);
-        ppc_dcr_register(env, MAL0_RXCASR,
-                         mal, &dcr_read_mal, &dcr_write_mal);
-        ppc_dcr_register(env, MAL0_RXCARR,
-                         mal, &dcr_read_mal, &dcr_write_mal);
-        ppc_dcr_register(env, MAL0_RXEOBISR,
-                         mal, &dcr_read_mal, &dcr_write_mal);
-        ppc_dcr_register(env, MAL0_RXDEIR,
-                         mal, &dcr_read_mal, &dcr_write_mal);
-        ppc_dcr_register(env, MAL0_TXCTP0R,
-                         mal, &dcr_read_mal, &dcr_write_mal);
-        ppc_dcr_register(env, MAL0_TXCTP1R,
-                         mal, &dcr_read_mal, &dcr_write_mal);
-        ppc_dcr_register(env, MAL0_TXCTP2R,
-                         mal, &dcr_read_mal, &dcr_write_mal);
-        ppc_dcr_register(env, MAL0_TXCTP3R,
-                         mal, &dcr_read_mal, &dcr_write_mal);
-        ppc_dcr_register(env, MAL0_RXCTP0R,
-                         mal, &dcr_read_mal, &dcr_write_mal);
-        ppc_dcr_register(env, MAL0_RXCTP1R,
-                         mal, &dcr_read_mal, &dcr_write_mal);
-        ppc_dcr_register(env, MAL0_RCBS0,
-                         mal, &dcr_read_mal, &dcr_write_mal);
-        ppc_dcr_register(env, MAL0_RCBS1,
-                         mal, &dcr_read_mal, &dcr_write_mal);
-    }
+    for (i = 0; i < 4; i++)
+        mal->irqs[i] = irqs[i];
+    ppc40x_mal_reset(mal);
+    qemu_register_reset(&ppc40x_mal_reset, 0, mal);
+    ppc_dcr_register(env, MAL0_CFG,
+                     mal, &dcr_read_mal, &dcr_write_mal);
+    ppc_dcr_register(env, MAL0_ESR,
+                     mal, &dcr_read_mal, &dcr_write_mal);
+    ppc_dcr_register(env, MAL0_IER,
+                     mal, &dcr_read_mal, &dcr_write_mal);
+    ppc_dcr_register(env, MAL0_TXCASR,
+                     mal, &dcr_read_mal, &dcr_write_mal);
+    ppc_dcr_register(env, MAL0_TXCARR,
+                     mal, &dcr_read_mal, &dcr_write_mal);
+    ppc_dcr_register(env, MAL0_TXEOBISR,
+                     mal, &dcr_read_mal, &dcr_write_mal);
+    ppc_dcr_register(env, MAL0_TXDEIR,
+                     mal, &dcr_read_mal, &dcr_write_mal);
+    ppc_dcr_register(env, MAL0_RXCASR,
+                     mal, &dcr_read_mal, &dcr_write_mal);
+    ppc_dcr_register(env, MAL0_RXCARR,
+                     mal, &dcr_read_mal, &dcr_write_mal);
+    ppc_dcr_register(env, MAL0_RXEOBISR,
+                     mal, &dcr_read_mal, &dcr_write_mal);
+    ppc_dcr_register(env, MAL0_RXDEIR,
+                     mal, &dcr_read_mal, &dcr_write_mal);
+    ppc_dcr_register(env, MAL0_TXCTP0R,
+                     mal, &dcr_read_mal, &dcr_write_mal);
+    ppc_dcr_register(env, MAL0_TXCTP1R,
+                     mal, &dcr_read_mal, &dcr_write_mal);
+    ppc_dcr_register(env, MAL0_TXCTP2R,
+                     mal, &dcr_read_mal, &dcr_write_mal);
+    ppc_dcr_register(env, MAL0_TXCTP3R,
+                     mal, &dcr_read_mal, &dcr_write_mal);
+    ppc_dcr_register(env, MAL0_RXCTP0R,
+                     mal, &dcr_read_mal, &dcr_write_mal);
+    ppc_dcr_register(env, MAL0_RXCTP1R,
+                     mal, &dcr_read_mal, &dcr_write_mal);
+    ppc_dcr_register(env, MAL0_RCBS0,
+                     mal, &dcr_read_mal, &dcr_write_mal);
+    ppc_dcr_register(env, MAL0_RCBS1,
+                     mal, &dcr_read_mal, &dcr_write_mal);
 }
 
 /*****************************************************************************/
@@ -2513,45 +2150,41 @@ static void ppc405cr_cpc_init (CPUState *env, clk_setup_t clk_setup[7],
     ppc405cr_cpc_t *cpc;
 
     cpc = qemu_mallocz(sizeof(ppc405cr_cpc_t));
-    if (cpc != NULL) {
-        memcpy(cpc->clk_setup, clk_setup,
-               PPC405CR_CLK_NB * sizeof(clk_setup_t));
-        cpc->sysclk = sysclk;
-        cpc->jtagid = 0x42051049;
-        ppc_dcr_register(env, PPC405CR_CPC0_PSR, cpc,
-                         &dcr_read_crcpc, &dcr_write_crcpc);
-        ppc_dcr_register(env, PPC405CR_CPC0_CR0, cpc,
-                         &dcr_read_crcpc, &dcr_write_crcpc);
-        ppc_dcr_register(env, PPC405CR_CPC0_CR1, cpc,
-                         &dcr_read_crcpc, &dcr_write_crcpc);
-        ppc_dcr_register(env, PPC405CR_CPC0_JTAGID, cpc,
-                         &dcr_read_crcpc, &dcr_write_crcpc);
-        ppc_dcr_register(env, PPC405CR_CPC0_PLLMR, cpc,
-                         &dcr_read_crcpc, &dcr_write_crcpc);
-        ppc_dcr_register(env, PPC405CR_CPC0_ER, cpc,
-                         &dcr_read_crcpc, &dcr_write_crcpc);
-        ppc_dcr_register(env, PPC405CR_CPC0_FR, cpc,
-                         &dcr_read_crcpc, &dcr_write_crcpc);
-        ppc_dcr_register(env, PPC405CR_CPC0_SR, cpc,
-                         &dcr_read_crcpc, &dcr_write_crcpc);
-        ppc405cr_clk_init(cpc);
-        qemu_register_reset(ppc405cr_cpc_reset, cpc);
-        ppc405cr_cpc_reset(cpc);
-    }
+    memcpy(cpc->clk_setup, clk_setup,
+           PPC405CR_CLK_NB * sizeof(clk_setup_t));
+    cpc->sysclk = sysclk;
+    cpc->jtagid = 0x42051049;
+    ppc_dcr_register(env, PPC405CR_CPC0_PSR, cpc,
+                     &dcr_read_crcpc, &dcr_write_crcpc);
+    ppc_dcr_register(env, PPC405CR_CPC0_CR0, cpc,
+                     &dcr_read_crcpc, &dcr_write_crcpc);
+    ppc_dcr_register(env, PPC405CR_CPC0_CR1, cpc,
+                     &dcr_read_crcpc, &dcr_write_crcpc);
+    ppc_dcr_register(env, PPC405CR_CPC0_JTAGID, cpc,
+                     &dcr_read_crcpc, &dcr_write_crcpc);
+    ppc_dcr_register(env, PPC405CR_CPC0_PLLMR, cpc,
+                     &dcr_read_crcpc, &dcr_write_crcpc);
+    ppc_dcr_register(env, PPC405CR_CPC0_ER, cpc,
+                     &dcr_read_crcpc, &dcr_write_crcpc);
+    ppc_dcr_register(env, PPC405CR_CPC0_FR, cpc,
+                     &dcr_read_crcpc, &dcr_write_crcpc);
+    ppc_dcr_register(env, PPC405CR_CPC0_SR, cpc,
+                     &dcr_read_crcpc, &dcr_write_crcpc);
+    ppc405cr_clk_init(cpc);
+    qemu_register_reset(ppc405cr_cpc_reset, 0, cpc);
+    ppc405cr_cpc_reset(cpc);
 }
 
 CPUState *ppc405cr_init (target_phys_addr_t ram_bases[4],
                          target_phys_addr_t ram_sizes[4],
                          uint32_t sysclk, qemu_irq **picp,
-                         ram_addr_t *offsetp, int do_init)
+                         int do_init)
 {
     clk_setup_t clk_setup[PPC405CR_CLK_NB];
     qemu_irq dma_irqs[4];
     CPUState *env;
     ppc4xx_mmio_t *mmio;
     qemu_irq *pic, *irqs;
-    ram_addr_t offset;
-    int i;
 
     memset(clk_setup, 0, sizeof(clk_setup));
     env = ppc4xx_init("405cr", &clk_setup[PPC405CR_CPU_CLK],
@@ -2573,10 +2206,7 @@ CPUState *ppc405cr_init (target_phys_addr_t ram_bases[4],
     pic = ppcuic_init(env, irqs, 0x0C0, 0, 1);
     *picp = pic;
     /* SDRAM controller */
-    ppc405_sdram_init(env, pic[14], 1, ram_bases, ram_sizes, do_init);
-    offset = 0;
-    for (i = 0; i < 4; i++)
-        offset += ram_sizes[i];
+    ppc4xx_sdram_init(env, pic[14], 1, ram_bases, ram_sizes, do_init);
     /* External bus controller */
     ppc405_ebc_init(env);
     /* DMA controller */
@@ -2587,18 +2217,17 @@ CPUState *ppc405cr_init (target_phys_addr_t ram_bases[4],
     ppc405_dma_init(env, dma_irqs);
     /* Serial ports */
     if (serial_hds[0] != NULL) {
-        ppc405_serial_init(env, mmio, 0x300, pic[31], serial_hds[0]);
+        ppc405_serial_init(env, mmio, 0x300, pic[0], serial_hds[0]);
     }
     if (serial_hds[1] != NULL) {
-        ppc405_serial_init(env, mmio, 0x400, pic[30], serial_hds[1]);
+        ppc405_serial_init(env, mmio, 0x400, pic[1], serial_hds[1]);
     }
     /* IIC controller */
-    ppc405_i2c_init(env, mmio, 0x500, pic[29]);
+    ppc405_i2c_init(env, mmio, 0x500, pic[2]);
     /* GPIO */
     ppc405_gpio_init(env, mmio, 0x700);
     /* CPU control */
     ppc405cr_cpc_init(env, clk_setup, sysclk);
-    *offsetp = offset;
 
     return env;
 }
@@ -2859,52 +2488,48 @@ static void ppc405ep_cpc_init (CPUState *env, clk_setup_t clk_setup[8],
     ppc405ep_cpc_t *cpc;
 
     cpc = qemu_mallocz(sizeof(ppc405ep_cpc_t));
-    if (cpc != NULL) {
-        memcpy(cpc->clk_setup, clk_setup,
-               PPC405EP_CLK_NB * sizeof(clk_setup_t));
-        cpc->jtagid = 0x20267049;
-        cpc->sysclk = sysclk;
-        ppc405ep_cpc_reset(cpc);
-        qemu_register_reset(&ppc405ep_cpc_reset, cpc);
-        ppc_dcr_register(env, PPC405EP_CPC0_BOOT, cpc,
-                         &dcr_read_epcpc, &dcr_write_epcpc);
-        ppc_dcr_register(env, PPC405EP_CPC0_EPCTL, cpc,
-                         &dcr_read_epcpc, &dcr_write_epcpc);
-        ppc_dcr_register(env, PPC405EP_CPC0_PLLMR0, cpc,
-                         &dcr_read_epcpc, &dcr_write_epcpc);
-        ppc_dcr_register(env, PPC405EP_CPC0_PLLMR1, cpc,
-                         &dcr_read_epcpc, &dcr_write_epcpc);
-        ppc_dcr_register(env, PPC405EP_CPC0_UCR, cpc,
-                         &dcr_read_epcpc, &dcr_write_epcpc);
-        ppc_dcr_register(env, PPC405EP_CPC0_SRR, cpc,
-                         &dcr_read_epcpc, &dcr_write_epcpc);
-        ppc_dcr_register(env, PPC405EP_CPC0_JTAGID, cpc,
-                         &dcr_read_epcpc, &dcr_write_epcpc);
-        ppc_dcr_register(env, PPC405EP_CPC0_PCI, cpc,
-                         &dcr_read_epcpc, &dcr_write_epcpc);
+    memcpy(cpc->clk_setup, clk_setup,
+           PPC405EP_CLK_NB * sizeof(clk_setup_t));
+    cpc->jtagid = 0x20267049;
+    cpc->sysclk = sysclk;
+    ppc405ep_cpc_reset(cpc);
+    qemu_register_reset(&ppc405ep_cpc_reset, 0, cpc);
+    ppc_dcr_register(env, PPC405EP_CPC0_BOOT, cpc,
+                     &dcr_read_epcpc, &dcr_write_epcpc);
+    ppc_dcr_register(env, PPC405EP_CPC0_EPCTL, cpc,
+                     &dcr_read_epcpc, &dcr_write_epcpc);
+    ppc_dcr_register(env, PPC405EP_CPC0_PLLMR0, cpc,
+                     &dcr_read_epcpc, &dcr_write_epcpc);
+    ppc_dcr_register(env, PPC405EP_CPC0_PLLMR1, cpc,
+                     &dcr_read_epcpc, &dcr_write_epcpc);
+    ppc_dcr_register(env, PPC405EP_CPC0_UCR, cpc,
+                     &dcr_read_epcpc, &dcr_write_epcpc);
+    ppc_dcr_register(env, PPC405EP_CPC0_SRR, cpc,
+                     &dcr_read_epcpc, &dcr_write_epcpc);
+    ppc_dcr_register(env, PPC405EP_CPC0_JTAGID, cpc,
+                     &dcr_read_epcpc, &dcr_write_epcpc);
+    ppc_dcr_register(env, PPC405EP_CPC0_PCI, cpc,
+                     &dcr_read_epcpc, &dcr_write_epcpc);
 #if 0
-        ppc_dcr_register(env, PPC405EP_CPC0_ER, cpc,
-                         &dcr_read_epcpc, &dcr_write_epcpc);
-        ppc_dcr_register(env, PPC405EP_CPC0_FR, cpc,
-                         &dcr_read_epcpc, &dcr_write_epcpc);
-        ppc_dcr_register(env, PPC405EP_CPC0_SR, cpc,
-                         &dcr_read_epcpc, &dcr_write_epcpc);
+    ppc_dcr_register(env, PPC405EP_CPC0_ER, cpc,
+                     &dcr_read_epcpc, &dcr_write_epcpc);
+    ppc_dcr_register(env, PPC405EP_CPC0_FR, cpc,
+                     &dcr_read_epcpc, &dcr_write_epcpc);
+    ppc_dcr_register(env, PPC405EP_CPC0_SR, cpc,
+                     &dcr_read_epcpc, &dcr_write_epcpc);
 #endif
-    }
 }
 
 CPUState *ppc405ep_init (target_phys_addr_t ram_bases[2],
                          target_phys_addr_t ram_sizes[2],
                          uint32_t sysclk, qemu_irq **picp,
-                         ram_addr_t *offsetp, int do_init)
+                         int do_init)
 {
     clk_setup_t clk_setup[PPC405EP_CLK_NB], tlb_clk_setup;
     qemu_irq dma_irqs[4], gpt_irqs[5], mal_irqs[4];
     CPUState *env;
     ppc4xx_mmio_t *mmio;
     qemu_irq *pic, *irqs;
-    ram_addr_t offset;
-    int i;
 
     memset(clk_setup, 0, sizeof(clk_setup));
     /* init CPUs */
@@ -2930,52 +2555,48 @@ CPUState *ppc405ep_init (target_phys_addr_t ram_bases[2],
     pic = ppcuic_init(env, irqs, 0x0C0, 0, 1);
     *picp = pic;
     /* SDRAM controller */
-    ppc405_sdram_init(env, pic[14], 2, ram_bases, ram_sizes, do_init);
-    offset = 0;
-    for (i = 0; i < 2; i++)
-        offset += ram_sizes[i];
+	/* XXX 405EP has no ECC interrupt */
+    ppc4xx_sdram_init(env, pic[17], 2, ram_bases, ram_sizes, do_init);
     /* External bus controller */
     ppc405_ebc_init(env);
     /* DMA controller */
-    dma_irqs[0] = pic[26];
-    dma_irqs[1] = pic[25];
-    dma_irqs[2] = pic[24];
-    dma_irqs[3] = pic[23];
+    dma_irqs[0] = pic[5];
+    dma_irqs[1] = pic[6];
+    dma_irqs[2] = pic[7];
+    dma_irqs[3] = pic[8];
     ppc405_dma_init(env, dma_irqs);
     /* IIC controller */
-    ppc405_i2c_init(env, mmio, 0x500, pic[29]);
+    ppc405_i2c_init(env, mmio, 0x500, pic[2]);
     /* GPIO */
     ppc405_gpio_init(env, mmio, 0x700);
     /* Serial ports */
     if (serial_hds[0] != NULL) {
-        ppc405_serial_init(env, mmio, 0x300, pic[31], serial_hds[0]);
+        ppc405_serial_init(env, mmio, 0x300, pic[0], serial_hds[0]);
     }
     if (serial_hds[1] != NULL) {
-        ppc405_serial_init(env, mmio, 0x400, pic[30], serial_hds[1]);
+        ppc405_serial_init(env, mmio, 0x400, pic[1], serial_hds[1]);
     }
     /* OCM */
-    ppc405_ocm_init(env, ram_sizes[0] + ram_sizes[1]);
-    offset += 4096;
+    ppc405_ocm_init(env);
     /* GPT */
-    gpt_irqs[0] = pic[12];
-    gpt_irqs[1] = pic[11];
-    gpt_irqs[2] = pic[10];
-    gpt_irqs[3] = pic[9];
-    gpt_irqs[4] = pic[8];
+    gpt_irqs[0] = pic[19];
+    gpt_irqs[1] = pic[20];
+    gpt_irqs[2] = pic[21];
+    gpt_irqs[3] = pic[22];
+    gpt_irqs[4] = pic[23];
     ppc4xx_gpt_init(env, mmio, 0x000, gpt_irqs);
     /* PCI */
-    /* Uses pic[28], pic[15], pic[13] */
+    /* Uses pic[3], pic[16], pic[18] */
     /* MAL */
-    mal_irqs[0] = pic[20];
-    mal_irqs[1] = pic[19];
-    mal_irqs[2] = pic[18];
-    mal_irqs[3] = pic[17];
+    mal_irqs[0] = pic[11];
+    mal_irqs[1] = pic[12];
+    mal_irqs[2] = pic[13];
+    mal_irqs[3] = pic[14];
     ppc405_mal_init(env, mal_irqs);
     /* Ethernet */
-    /* Uses pic[22], pic[16], pic[14] */
+    /* Uses pic[9], pic[15], pic[17] */
     /* CPU control */
     ppc405ep_cpc_init(env, clk_setup, sysclk);
-    *offsetp = offset;
 
     return env;
 }