X-Git-Url: http://git.maemo.org/git/?a=blobdiff_plain;f=hw%2Fppc_prep.c;h=5392072982731c7e0559f1fcfab0506ee8e90400;hb=refs%2Fheads%2Flinux-user-for-upstream;hp=88dcac838dae18b5a7054da0a77fc04bb34616d3;hpb=46e50e9d58aa0fd6ab8f5cadceb8b55ee7e1d806;p=qemu diff --git a/hw/ppc_prep.c b/hw/ppc_prep.c index 88dcac8..5392072 100644 --- a/hw/ppc_prep.c +++ b/hw/ppc_prep.c @@ -1,8 +1,8 @@ /* * QEMU PPC PREP hardware System Emulator - * - * Copyright (c) 2003-2004 Jocelyn Mayer - * + * + * Copyright (c) 2003-2007 Jocelyn Mayer + * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights @@ -21,40 +21,50 @@ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN * THE SOFTWARE. */ -#include "vl.h" +#include "hw.h" +#include "nvram.h" +#include "pc.h" +#include "fdc.h" +#include "net.h" +#include "sysemu.h" +#include "isa.h" +#include "pci.h" +#include "ppc.h" +#include "boards.h" +#include "qemu-log.h" +#include "ide.h" //#define HARD_DEBUG_PPC_IO //#define DEBUG_PPC_IO +/* SMP is not enabled, for now */ +#define MAX_CPUS 1 + +#define MAX_IDE_BUS 2 + +#define BIOS_SIZE (1024 * 1024) #define BIOS_FILENAME "ppc_rom.bin" #define KERNEL_LOAD_ADDR 0x01000000 #define INITRD_LOAD_ADDR 0x01800000 -extern int loglevel; -extern FILE *logfile; - #if defined (HARD_DEBUG_PPC_IO) && !defined (DEBUG_PPC_IO) #define DEBUG_PPC_IO #endif #if defined (HARD_DEBUG_PPC_IO) -#define PPC_IO_DPRINTF(fmt, args...) \ +#define PPC_IO_DPRINTF(fmt, ...) \ do { \ - if (loglevel & CPU_LOG_IOPORT) { \ - fprintf(logfile, "%s: " fmt, __func__ , ##args); \ + if (qemu_loglevel_mask(CPU_LOG_IOPORT)) { \ + qemu_log("%s: " fmt, __func__ , ## __VA_ARGS__); \ } else { \ - printf("%s : " fmt, __func__ , ##args); \ + printf("%s : " fmt, __func__ , ## __VA_ARGS__); \ } \ } while (0) #elif defined (DEBUG_PPC_IO) -#define PPC_IO_DPRINTF(fmt, args...) \ -do { \ - if (loglevel & CPU_LOG_IOPORT) { \ - fprintf(logfile, "%s: " fmt, __func__ , ##args); \ - } \ -} while (0) +#define PPC_IO_DPRINTF(fmt, ...) \ +qemu_log_mask(CPU_LOG_IOPORT, fmt, ## __VA_ARGS__) #else -#define PPC_IO_DPRINTF(fmt, args...) do { } while (0) +#define PPC_IO_DPRINTF(fmt, ...) do { } while (0) #endif /* Constants for devices init */ @@ -72,11 +82,13 @@ static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; /* ISA IO ports bridge */ #define PPC_IO_BASE 0x80000000 +#if 0 /* Speaker port 0x61 */ -int speaker_data_on; -int dummy_refresh_clock; +static int speaker_data_on; +static int dummy_refresh_clock; +#endif -static void speaker_ioport_write(void *opaque, uint32_t addr, uint32_t val) +static void speaker_ioport_write (void *opaque, uint32_t addr, uint32_t val) { #if 0 speaker_data_on = (val >> 1) & 1; @@ -84,32 +96,39 @@ static void speaker_ioport_write(void *opaque, uint32_t addr, uint32_t val) #endif } -static uint32_t speaker_ioport_read(void *opaque, uint32_t addr) +static uint32_t speaker_ioport_read (void *opaque, uint32_t addr) { #if 0 int out; out = pit_get_out(pit, 2, qemu_get_clock(vm_clock)); dummy_refresh_clock ^= 1; return (speaker_data_on << 1) | pit_get_gate(pit, 2) | (out << 5) | - (dummy_refresh_clock << 4); + (dummy_refresh_clock << 4); #endif return 0; } /* PCI intack register */ /* Read-only register (?) */ -static void _PPC_intack_write (void *opaque, target_phys_addr_t addr, uint32_t value) +static void _PPC_intack_write (void *opaque, + target_phys_addr_t addr, uint32_t value) { - // printf("%s: 0x%08x => 0x%08x\n", __func__, addr, value); +#if 0 + printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr, + value); +#endif } -static inline uint32_t _PPC_intack_read (target_phys_addr_t addr) +static inline uint32_t _PPC_intack_read(target_phys_addr_t addr) { uint32_t retval = 0; - if (addr == 0xBFFFFFF0) - retval = pic_intack_read(NULL); - // printf("%s: 0x%08x <= %d\n", __func__, addr, retval); + if ((addr & 0xf) == 0) + retval = pic_intack_read(isa_pic); +#if 0 + printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr, + retval); +#endif return retval; } @@ -137,13 +156,13 @@ static uint32_t PPC_intack_readl (void *opaque, target_phys_addr_t addr) #endif } -static CPUWriteMemoryFunc *PPC_intack_write[] = { +static CPUWriteMemoryFunc * const PPC_intack_write[] = { &_PPC_intack_write, &_PPC_intack_write, &_PPC_intack_write, }; -static CPUReadMemoryFunc *PPC_intack_read[] = { +static CPUReadMemoryFunc * const PPC_intack_read[] = { &PPC_intack_readb, &PPC_intack_readw, &PPC_intack_readl, @@ -176,32 +195,39 @@ static struct { /* Error diagnostic */ } XCSR; -static void PPC_XCSR_writeb (void *opaque, target_phys_addr_t addr, uint32_t value) +static void PPC_XCSR_writeb (void *opaque, + target_phys_addr_t addr, uint32_t value) { - printf("%s: 0x%08lx => 0x%08x\n", __func__, (long)addr, value); + printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr, + value); } -static void PPC_XCSR_writew (void *opaque, target_phys_addr_t addr, uint32_t value) +static void PPC_XCSR_writew (void *opaque, + target_phys_addr_t addr, uint32_t value) { #ifdef TARGET_WORDS_BIGENDIAN value = bswap16(value); #endif - printf("%s: 0x%08lx => 0x%08x\n", __func__, (long)addr, value); + printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr, + value); } -static void PPC_XCSR_writel (void *opaque, target_phys_addr_t addr, uint32_t value) +static void PPC_XCSR_writel (void *opaque, + target_phys_addr_t addr, uint32_t value) { #ifdef TARGET_WORDS_BIGENDIAN value = bswap32(value); #endif - printf("%s: 0x%08lx => 0x%08x\n", __func__, (long)addr, value); + printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr, + value); } static uint32_t PPC_XCSR_readb (void *opaque, target_phys_addr_t addr) { uint32_t retval = 0; - printf("%s: 0x%08lx <= %d\n", __func__, (long)addr, retval); + printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr, + retval); return retval; } @@ -210,7 +236,8 @@ static uint32_t PPC_XCSR_readw (void *opaque, target_phys_addr_t addr) { uint32_t retval = 0; - printf("%s: 0x%08lx <= %d\n", __func__, (long)addr, retval); + printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr, + retval); #ifdef TARGET_WORDS_BIGENDIAN retval = bswap16(retval); #endif @@ -222,7 +249,8 @@ static uint32_t PPC_XCSR_readl (void *opaque, target_phys_addr_t addr) { uint32_t retval = 0; - printf("%s: 0x%08lx <= %d\n", __func__, (long)addr, retval); + printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr, + retval); #ifdef TARGET_WORDS_BIGENDIAN retval = bswap32(retval); #endif @@ -230,13 +258,13 @@ static uint32_t PPC_XCSR_readl (void *opaque, target_phys_addr_t addr) return retval; } -static CPUWriteMemoryFunc *PPC_XCSR_write[] = { +static CPUWriteMemoryFunc * const PPC_XCSR_write[] = { &PPC_XCSR_writeb, &PPC_XCSR_writew, &PPC_XCSR_writel, }; -static CPUReadMemoryFunc *PPC_XCSR_read[] = { +static CPUReadMemoryFunc * const PPC_XCSR_read[] = { &PPC_XCSR_readb, &PPC_XCSR_readw, &PPC_XCSR_readl, @@ -245,10 +273,13 @@ static CPUReadMemoryFunc *PPC_XCSR_read[] = { /* Fake super-io ports for PREP platform (Intel 82378ZB) */ typedef struct sysctrl_t { + qemu_irq reset_irq; m48t59_t *nvram; uint8_t state; uint8_t syscontrol; uint8_t fake_io[2]; + int contiguous_map; + int endian; } sysctrl_t; enum { @@ -261,7 +292,8 @@ static void PREP_io_write (void *opaque, uint32_t addr, uint32_t val) { sysctrl_t *sysctrl = opaque; - PPC_IO_DPRINTF("0x%08lx => 0x%08x\n", (long)addr - PPC_IO_BASE, val); + PPC_IO_DPRINTF("0x%08" PRIx32 " => 0x%02" PRIx32 "\n", addr - PPC_IO_BASE, + val); sysctrl->fake_io[addr - 0x0398] = val; } @@ -269,7 +301,7 @@ static uint32_t PREP_io_read (void *opaque, uint32_t addr) { sysctrl_t *sysctrl = opaque; - PPC_IO_DPRINTF("0x%08lx <= 0x%08x\n", (long)addr - PPC_IO_BASE, + PPC_IO_DPRINTF("0x%08" PRIx32 " <= 0x%02" PRIx32 "\n", addr - PPC_IO_BASE, sysctrl->fake_io[addr - 0x0398]); return sysctrl->fake_io[addr - 0x0398]; } @@ -278,18 +310,22 @@ static void PREP_io_800_writeb (void *opaque, uint32_t addr, uint32_t val) { sysctrl_t *sysctrl = opaque; - PPC_IO_DPRINTF("0x%08lx => 0x%08x\n", (long)addr - PPC_IO_BASE, val); + PPC_IO_DPRINTF("0x%08" PRIx32 " => 0x%02" PRIx32 "\n", + addr - PPC_IO_BASE, val); switch (addr) { case 0x0092: /* Special port 92 */ /* Check soft reset asked */ if (val & 0x01) { - // cpu_interrupt(cpu_single_env, CPU_INTERRUPT_RESET); + qemu_irq_raise(sysctrl->reset_irq); + } else { + qemu_irq_lower(sysctrl->reset_irq); } /* Check LE mode */ if (val & 0x02) { - printf("Little Endian mode isn't supported (yet ?)\n"); - abort(); + sysctrl->endian = 1; + } else { + sysctrl->endian = 0; } break; case 0x0800: @@ -320,7 +356,7 @@ static void PREP_io_800_writeb (void *opaque, uint32_t addr, uint32_t val) break; case 0x0814: /* L2 invalidate register */ - // tlb_flush(cpu_single_env, 1); + // tlb_flush(first_cpu, 1); break; case 0x081C: /* system control register */ @@ -328,14 +364,11 @@ static void PREP_io_800_writeb (void *opaque, uint32_t addr, uint32_t val) break; case 0x0850: /* I/O map type register */ - if (!(val & 0x01)) { - printf("No support for non-continuous I/O map mode\n"); - abort(); - } + sysctrl->contiguous_map = val & 0x01; break; default: - printf("ERROR: unaffected IO port write: %04lx => %02x\n", - (long)addr, val); + printf("ERROR: unaffected IO port write: %04" PRIx32 + " => %02" PRIx32"\n", addr, val); break; } } @@ -375,6 +408,9 @@ static uint32_t PREP_io_800_readb (void *opaque, uint32_t addr) /* Motorola base module extended feature register */ retval = 0x39; /* No USB, CF and PCI bridge. NVRAM present */ break; + case 0x0814: + /* L2 invalidate: don't care */ + break; case 0x0818: /* Keylock */ retval = 0x00; @@ -391,131 +427,308 @@ static uint32_t PREP_io_800_readb (void *opaque, uint32_t addr) break; case 0x0850: /* I/O map type register */ - retval = 0x01; + retval = sysctrl->contiguous_map; break; default: - printf("ERROR: unaffected IO port: %04lx read\n", (long)addr); + printf("ERROR: unaffected IO port: %04" PRIx32 " read\n", addr); break; } - PPC_IO_DPRINTF("0x%08lx <= 0x%08x\n", (long)addr - PPC_IO_BASE, retval); + PPC_IO_DPRINTF("0x%08" PRIx32 " <= 0x%02" PRIx32 "\n", + addr - PPC_IO_BASE, retval); return retval; } -extern CPUPPCState *global_env; +static inline target_phys_addr_t prep_IO_address(sysctrl_t *sysctrl, + target_phys_addr_t addr) +{ + if (sysctrl->contiguous_map == 0) { + /* 64 KB contiguous space for IOs */ + addr &= 0xFFFF; + } else { + /* 8 MB non-contiguous space for IOs */ + addr = (addr & 0x1F) | ((addr & 0x007FFF000) >> 7); + } + + return addr; +} + +static void PPC_prep_io_writeb (void *opaque, target_phys_addr_t addr, + uint32_t value) +{ + sysctrl_t *sysctrl = opaque; + + addr = prep_IO_address(sysctrl, addr); + cpu_outb(NULL, addr, value); +} + +static uint32_t PPC_prep_io_readb (void *opaque, target_phys_addr_t addr) +{ + sysctrl_t *sysctrl = opaque; + uint32_t ret; + + addr = prep_IO_address(sysctrl, addr); + ret = cpu_inb(NULL, addr); + + return ret; +} + +static void PPC_prep_io_writew (void *opaque, target_phys_addr_t addr, + uint32_t value) +{ + sysctrl_t *sysctrl = opaque; + + addr = prep_IO_address(sysctrl, addr); +#ifdef TARGET_WORDS_BIGENDIAN + value = bswap16(value); +#endif + PPC_IO_DPRINTF("0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", addr, value); + cpu_outw(NULL, addr, value); +} + +static uint32_t PPC_prep_io_readw (void *opaque, target_phys_addr_t addr) +{ + sysctrl_t *sysctrl = opaque; + uint32_t ret; + + addr = prep_IO_address(sysctrl, addr); + ret = cpu_inw(NULL, addr); +#ifdef TARGET_WORDS_BIGENDIAN + ret = bswap16(ret); +#endif + PPC_IO_DPRINTF("0x" TARGET_FMT_plx " <= 0x%08" PRIx32 "\n", addr, ret); + + return ret; +} + +static void PPC_prep_io_writel (void *opaque, target_phys_addr_t addr, + uint32_t value) +{ + sysctrl_t *sysctrl = opaque; + + addr = prep_IO_address(sysctrl, addr); +#ifdef TARGET_WORDS_BIGENDIAN + value = bswap32(value); +#endif + PPC_IO_DPRINTF("0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", addr, value); + cpu_outl(NULL, addr, value); +} + +static uint32_t PPC_prep_io_readl (void *opaque, target_phys_addr_t addr) +{ + sysctrl_t *sysctrl = opaque; + uint32_t ret; + + addr = prep_IO_address(sysctrl, addr); + ret = cpu_inl(NULL, addr); +#ifdef TARGET_WORDS_BIGENDIAN + ret = bswap32(ret); +#endif + PPC_IO_DPRINTF("0x" TARGET_FMT_plx " <= 0x%08" PRIx32 "\n", addr, ret); + + return ret; +} + +static CPUWriteMemoryFunc * const PPC_prep_io_write[] = { + &PPC_prep_io_writeb, + &PPC_prep_io_writew, + &PPC_prep_io_writel, +}; + +static CPUReadMemoryFunc * const PPC_prep_io_read[] = { + &PPC_prep_io_readb, + &PPC_prep_io_readw, + &PPC_prep_io_readl, +}; #define NVRAM_SIZE 0x2000 /* PowerPC PREP hardware initialisation */ -void ppc_prep_init(int ram_size, int vga_ram_size, int boot_device, - DisplayState *ds, const char **fd_filename, int snapshot, - const char *kernel_filename, const char *kernel_cmdline, - const char *initrd_filename) +static void ppc_prep_init (ram_addr_t ram_size, + const char *boot_device, + const char *kernel_filename, + const char *kernel_cmdline, + const char *initrd_filename, + const char *cpu_model) { - char buf[1024]; - m48t59_t *nvram; + CPUState *env = NULL, *envs[MAX_CPUS]; + char *filename; + nvram_t nvram; + m48t59_t *m48t59; int PPC_io_memory; - int ret, linux_boot, i, nb_nics1, fd; - unsigned long bios_offset; + int linux_boot, i, nb_nics1, bios_size; + ram_addr_t ram_offset, bios_offset; uint32_t kernel_base, kernel_size, initrd_base, initrd_size; PCIBus *pci_bus; + qemu_irq *i8259; + int ppc_boot_device; + DriveInfo *dinfo; + DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; + BlockDriverState *fd[MAX_FD]; sysctrl = qemu_mallocz(sizeof(sysctrl_t)); - if (sysctrl == NULL) - return; linux_boot = (kernel_filename != NULL); + /* init CPUs */ + if (cpu_model == NULL) + cpu_model = "602"; + for (i = 0; i < smp_cpus; i++) { + env = cpu_init(cpu_model); + if (!env) { + fprintf(stderr, "Unable to find PowerPC CPU definition\n"); + exit(1); + } + if (env->flags & POWERPC_FLAG_RTC_CLK) { + /* POWER / PowerPC 601 RTC clock frequency is 7.8125 MHz */ + cpu_ppc_tb_init(env, 7812500UL); + } else { + /* Set time-base frequency to 100 Mhz */ + cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL); + } + qemu_register_reset(&cpu_ppc_reset, env); + envs[i] = env; + } + /* allocate RAM */ - cpu_register_physical_memory(0, ram_size, IO_MEM_RAM); + ram_offset = qemu_ram_alloc(ram_size); + cpu_register_physical_memory(0, ram_size, ram_offset); /* allocate and load BIOS */ - bios_offset = ram_size + vga_ram_size; - snprintf(buf, sizeof(buf), "%s/%s", bios_dir, BIOS_FILENAME); - ret = load_image(buf, phys_ram_base + bios_offset); - if (ret != BIOS_SIZE) { - fprintf(stderr, "qemu: could not load PPC PREP bios '%s'\n", buf); - exit(1); + bios_offset = qemu_ram_alloc(BIOS_SIZE); + if (bios_name == NULL) + bios_name = BIOS_FILENAME; + filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); + if (filename) { + bios_size = get_image_size(filename); + } else { + bios_size = -1; + } + if (bios_size > 0 && bios_size <= BIOS_SIZE) { + target_phys_addr_t bios_addr; + bios_size = (bios_size + 0xfff) & ~0xfff; + bios_addr = (uint32_t)(-bios_size); + cpu_register_physical_memory(bios_addr, bios_size, + bios_offset | IO_MEM_ROM); + bios_size = load_image_targphys(filename, bios_addr, bios_size); + } + if (bios_size < 0 || bios_size > BIOS_SIZE) { + hw_error("qemu: could not load PPC PREP bios '%s'\n", bios_name); + } + if (filename) { + qemu_free(filename); + } + if (env->nip < 0xFFF80000 && bios_size < 0x00100000) { + hw_error("PowerPC 601 / 620 / 970 need a 1MB BIOS\n"); } - cpu_register_physical_memory((uint32_t)(-BIOS_SIZE), - BIOS_SIZE, bios_offset | IO_MEM_ROM); - cpu_single_env->nip = 0xfffffffc; if (linux_boot) { kernel_base = KERNEL_LOAD_ADDR; /* now we can load the kernel */ - kernel_size = load_image(kernel_filename, phys_ram_base + kernel_base); + kernel_size = load_image_targphys(kernel_filename, kernel_base, + ram_size - kernel_base); if (kernel_size < 0) { - fprintf(stderr, "qemu: could not load kernel '%s'\n", - kernel_filename); + hw_error("qemu: could not load kernel '%s'\n", kernel_filename); exit(1); } /* load initrd */ if (initrd_filename) { initrd_base = INITRD_LOAD_ADDR; - initrd_size = load_image(initrd_filename, - phys_ram_base + initrd_base); + initrd_size = load_image_targphys(initrd_filename, initrd_base, + ram_size - initrd_base); if (initrd_size < 0) { - fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", - initrd_filename); - exit(1); + hw_error("qemu: could not load initial ram disk '%s'\n", + initrd_filename); } } else { initrd_base = 0; initrd_size = 0; } - boot_device = 'm'; + ppc_boot_device = 'm'; } else { kernel_base = 0; kernel_size = 0; initrd_base = 0; initrd_size = 0; + ppc_boot_device = '\0'; + /* For now, OHW cannot boot from the network. */ + for (i = 0; boot_device[i] != '\0'; i++) { + if (boot_device[i] >= 'a' && boot_device[i] <= 'f') { + ppc_boot_device = boot_device[i]; + break; + } + } + if (ppc_boot_device == '\0') { + fprintf(stderr, "No valid boot device for Mac99 machine\n"); + exit(1); + } } - /* Register CPU as a 74x/75x */ - cpu_ppc_register(cpu_single_env, 0x00080000); - /* Set time-base frequency to 100 Mhz */ - cpu_ppc_tb_init(cpu_single_env, 100UL * 1000UL * 1000UL); - isa_mem_base = 0xc0000000; - pci_bus = pci_prep_init(); - /* Register 64 KB of ISA IO space */ - PPC_io_memory = cpu_register_io_memory(0, PPC_io_read, PPC_io_write, NULL); - cpu_register_physical_memory(0x80000000, 0x00010000, PPC_io_memory); + if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) { + hw_error("Only 6xx bus is supported on PREP machine\n"); + } + i8259 = i8259_init(first_cpu->irq_inputs[PPC6xx_INPUT_INT]); + pci_bus = pci_prep_init(i8259); + /* Hmm, prep has no pci-isa bridge ??? */ + isa_bus_new(NULL); + isa_bus_irqs(i8259); + // pci_bus = i440fx_init(); + /* Register 8 MB of ISA IO space (needed for non-contiguous map) */ + PPC_io_memory = cpu_register_io_memory(PPC_prep_io_read, + PPC_prep_io_write, sysctrl); + cpu_register_physical_memory(0x80000000, 0x00800000, PPC_io_memory); /* init basic PC hardware */ - vga_initialize(pci_bus, ds, phys_ram_base + ram_size, ram_size, - vga_ram_size); - rtc_init(0x70, 8); + pci_vga_init(pci_bus, 0, 0); // openpic = openpic_init(0x00000000, 0xF0000000, 1); - // pic_init(openpic); - pic_init(); - // pit = pit_init(0x40, 0); + // pit = pit_init(0x40, i8259[0]); + rtc_init(2000); - fd = serial_open_device(); - serial_init(0x3f8, 4, fd); + serial_init(0x3f8, i8259[4], 115200, serial_hds[0]); nb_nics1 = nb_nics; if (nb_nics1 > NE2000_NB_MAX) nb_nics1 = NE2000_NB_MAX; for(i = 0; i < nb_nics1; i++) { - isa_ne2000_init(ne2000_io[i], ne2000_irq[i], &nd_table[i]); + if (nd_table[i].model == NULL) { + nd_table[i].model = "ne2k_isa"; + } + if (strcmp(nd_table[i].model, "ne2k_isa") == 0) { + isa_ne2000_init(ne2000_io[i], ne2000_irq[i], &nd_table[i]); + } else { + pci_nic_init(&nd_table[i], "ne2k_pci", NULL); + } } - for(i = 0; i < 2; i++) { + if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) { + fprintf(stderr, "qemu: too many IDE bus\n"); + exit(1); + } + + for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) { + hd[i] = drive_get(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS); + } + + for(i = 0; i < MAX_IDE_BUS; i++) { isa_ide_init(ide_iobase[i], ide_iobase2[i], ide_irq[i], - bs_table[2 * i], bs_table[2 * i + 1]); + hd[2 * i], + hd[2 * i + 1]); } - kbd_init(); + isa_create_simple("i8042"); DMA_init(1); - // AUD_init(); // SB16_init(); - fdctrl_init(6, 2, 0, 0x3f0, fd_table); + for(i = 0; i < MAX_FD; i++) { + dinfo = drive_get(IF_FLOPPY, 0, i); + fd[i] = dinfo ? dinfo->bdrv : NULL; + } + fdctrl_init_isa(fd); /* Register speaker port */ register_ioport_read(0x61, 1, 1, speaker_ioport_read, NULL); register_ioport_write(0x61, 1, 1, speaker_ioport_write, NULL); /* Register fake IO ports for PREP */ + sysctrl->reset_irq = first_cpu->irq_inputs[PPC6xx_INPUT_HRESET]; register_ioport_read(0x398, 2, 1, &PREP_io_read, sysctrl); register_ioport_write(0x398, 2, 1, &PREP_io_write, sysctrl); /* System control ports */ @@ -524,26 +737,51 @@ void ppc_prep_init(int ram_size, int vga_ram_size, int boot_device, register_ioport_read(0x0800, 0x52, 1, &PREP_io_800_readb, sysctrl); register_ioport_write(0x0800, 0x52, 1, &PREP_io_800_writeb, sysctrl); /* PCI intack location */ - PPC_io_memory = cpu_register_io_memory(0, PPC_intack_read, + PPC_io_memory = cpu_register_io_memory(PPC_intack_read, PPC_intack_write, NULL); cpu_register_physical_memory(0xBFFFFFF0, 0x4, PPC_io_memory); /* PowerPC control and status register group */ #if 0 - PPC_io_memory = cpu_register_io_memory(0, PPC_XCSR_read, PPC_XCSR_write, NULL); + PPC_io_memory = cpu_register_io_memory(PPC_XCSR_read, PPC_XCSR_write, + NULL); cpu_register_physical_memory(0xFEFF0000, 0x1000, PPC_io_memory); #endif - nvram = m48t59_init(8, 0, 0x0074, NVRAM_SIZE); - if (nvram == NULL) + if (usb_enabled) { + usb_ohci_init_pci(pci_bus, -1); + } + + m48t59 = m48t59_init(i8259[8], 0, 0x0074, NVRAM_SIZE, 59); + if (m48t59 == NULL) return; - sysctrl->nvram = nvram; + sysctrl->nvram = m48t59; /* Initialise NVRAM */ - PPC_NVRAM_set_params(nvram, NVRAM_SIZE, "PREP", ram_size, boot_device, + nvram.opaque = m48t59; + nvram.read_fn = &m48t59_read; + nvram.write_fn = &m48t59_write; + PPC_NVRAM_set_params(&nvram, NVRAM_SIZE, "PREP", ram_size, ppc_boot_device, kernel_base, kernel_size, kernel_cmdline, initrd_base, initrd_size, /* XXX: need an option to load a NVRAM image */ 0, graphic_width, graphic_height, graphic_depth); + + /* Special port to get debug messages from Open-Firmware */ + register_ioport_write(0x0F00, 4, 1, &PPC_debug_write, NULL); } + +static QEMUMachine prep_machine = { + .name = "prep", + .desc = "PowerPC PREP platform", + .init = ppc_prep_init, + .max_cpus = MAX_CPUS, +}; + +static void prep_machine_init(void) +{ + qemu_register_machine(&prep_machine); +} + +machine_init(prep_machine_init);