X-Git-Url: http://git.maemo.org/git/?a=blobdiff_plain;f=target-i386%2Ftranslate.c;h=472600937554d4e5d35a28f6ba7381d2e57d4139;hb=a23978077ba006c8afdd842a448d5ac7106827ff;hp=dc7bb03c2a7dfd0f3a4396f47e0ae14eb0cfa0bf;hpb=e108dd01ce8fd3af84929ce925f791e1086a7a75;p=qemu diff --git a/target-i386/translate.c b/target-i386/translate.c index dc7bb03..4726009 100644 --- a/target-i386/translate.c +++ b/target-i386/translate.c @@ -15,7 +15,7 @@ * * You should have received a copy of the GNU Lesser General Public * License along with this library; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA */ #include #include @@ -23,14 +23,16 @@ #include #include #include -#include #include "cpu.h" #include "exec-all.h" #include "disas.h" -#include "helper.h" #include "tcg-op.h" +#include "helper.h" +#define GEN_HELPER 1 +#include "helper.h" + #define PREFIX_REPZ 0x01 #define PREFIX_REPNZ 0x02 #define PREFIX_LOCK 0x04 @@ -39,7 +41,7 @@ #ifdef TARGET_X86_64 #define X86_64_ONLY(x) x -#define X86_64_DEF(x...) x +#define X86_64_DEF(...) __VA_ARGS__ #define CODE64(s) ((s)->code64) #define REX_X(s) ((s)->rex_x) #define REX_B(s) ((s)->rex_b) @@ -49,7 +51,7 @@ #endif #else #define X86_64_ONLY(x) NULL -#define X86_64_DEF(x...) +#define X86_64_DEF(...) #define CODE64(s) 0 #define REX_X(s) 0 #define REX_B(s) 0 @@ -58,12 +60,20 @@ //#define MACRO_TEST 1 /* global register indexes */ -static TCGv cpu_env, cpu_T[2], cpu_A0, cpu_cc_op, cpu_cc_src, cpu_cc_dst; -static TCGv cpu_T3; +static TCGv_ptr cpu_env; +static TCGv cpu_A0, cpu_cc_src, cpu_cc_dst, cpu_cc_tmp; +static TCGv_i32 cpu_cc_op; +/* local temps */ +static TCGv cpu_T[2], cpu_T3; /* local register indexes (only used inside old micro ops) */ -static TCGv cpu_tmp0, cpu_tmp1_i64, cpu_tmp2_i32, cpu_tmp3_i32, cpu_tmp4, cpu_ptr0, cpu_ptr1; +static TCGv cpu_tmp0, cpu_tmp4; +static TCGv_ptr cpu_ptr0, cpu_ptr1; +static TCGv_i32 cpu_tmp2_i32, cpu_tmp3_i32; +static TCGv_i64 cpu_tmp1_i64; static TCGv cpu_tmp5, cpu_tmp6; +#include "gen-icount.h" + #ifdef TARGET_X86_64 static int x86_64_hregs; #endif @@ -103,6 +113,7 @@ typedef struct DisasContext { int cpuid_features; int cpuid_ext_features; int cpuid_ext2_features; + int cpuid_ext3_features; } DisasContext; static void gen_eob(DisasContext *s); @@ -133,6 +144,17 @@ enum { OP_SAR = 7, }; +enum { + JCC_O, + JCC_B, + JCC_Z, + JCC_BE, + JCC_S, + JCC_P, + JCC_L, + JCC_LE, +}; + /* operand size */ enum { OT_BYTE = 0, @@ -228,38 +250,10 @@ static inline void gen_op_andl_A0_ffff(void) #define NB_OP_SIZES 4 -#define DEF_REGS(prefix, suffix) \ - prefix ## EAX ## suffix,\ - prefix ## ECX ## suffix,\ - prefix ## EDX ## suffix,\ - prefix ## EBX ## suffix,\ - prefix ## ESP ## suffix,\ - prefix ## EBP ## suffix,\ - prefix ## ESI ## suffix,\ - prefix ## EDI ## suffix,\ - prefix ## R8 ## suffix,\ - prefix ## R9 ## suffix,\ - prefix ## R10 ## suffix,\ - prefix ## R11 ## suffix,\ - prefix ## R12 ## suffix,\ - prefix ## R13 ## suffix,\ - prefix ## R14 ## suffix,\ - prefix ## R15 ## suffix, - #else /* !TARGET_X86_64 */ #define NB_OP_SIZES 3 -#define DEF_REGS(prefix, suffix) \ - prefix ## EAX ## suffix,\ - prefix ## ECX ## suffix,\ - prefix ## EDX ## suffix,\ - prefix ## EBX ## suffix,\ - prefix ## ESP ## suffix,\ - prefix ## EBP ## suffix,\ - prefix ## ESI ## suffix,\ - prefix ## EDI ## suffix, - #endif /* !TARGET_X86_64 */ #if defined(WORDS_BIGENDIAN) @@ -276,34 +270,34 @@ static inline void gen_op_andl_A0_ffff(void) #define REG_LH_OFFSET 4 #endif -static inline void gen_op_mov_reg_TN(int ot, int t_index, int reg) +static inline void gen_op_mov_reg_v(int ot, int reg, TCGv t0) { switch(ot) { case OT_BYTE: if (reg < 4 X86_64_DEF( || reg >= 8 || x86_64_hregs)) { - tcg_gen_st8_tl(cpu_T[t_index], cpu_env, offsetof(CPUState, regs[reg]) + REG_B_OFFSET); + tcg_gen_st8_tl(t0, cpu_env, offsetof(CPUState, regs[reg]) + REG_B_OFFSET); } else { - tcg_gen_st8_tl(cpu_T[t_index], cpu_env, offsetof(CPUState, regs[reg - 4]) + REG_H_OFFSET); + tcg_gen_st8_tl(t0, cpu_env, offsetof(CPUState, regs[reg - 4]) + REG_H_OFFSET); } break; case OT_WORD: - tcg_gen_st16_tl(cpu_T[t_index], cpu_env, offsetof(CPUState, regs[reg]) + REG_W_OFFSET); + tcg_gen_st16_tl(t0, cpu_env, offsetof(CPUState, regs[reg]) + REG_W_OFFSET); break; #ifdef TARGET_X86_64 case OT_LONG: - tcg_gen_st32_tl(cpu_T[t_index], cpu_env, offsetof(CPUState, regs[reg]) + REG_L_OFFSET); + tcg_gen_st32_tl(t0, cpu_env, offsetof(CPUState, regs[reg]) + REG_L_OFFSET); /* high part of register set to zero */ tcg_gen_movi_tl(cpu_tmp0, 0); tcg_gen_st32_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]) + REG_LH_OFFSET); break; default: case OT_QUAD: - tcg_gen_st_tl(cpu_T[t_index], cpu_env, offsetof(CPUState, regs[reg])); + tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, regs[reg])); break; #else default: case OT_LONG: - tcg_gen_st32_tl(cpu_T[t_index], cpu_env, offsetof(CPUState, regs[reg]) + REG_L_OFFSET); + tcg_gen_st32_tl(t0, cpu_env, offsetof(CPUState, regs[reg]) + REG_L_OFFSET); break; #endif } @@ -311,12 +305,12 @@ static inline void gen_op_mov_reg_TN(int ot, int t_index, int reg) static inline void gen_op_mov_reg_T0(int ot, int reg) { - gen_op_mov_reg_TN(ot, 0, reg); + gen_op_mov_reg_v(ot, reg, cpu_T[0]); } static inline void gen_op_mov_reg_T1(int ot, int reg) { - gen_op_mov_reg_TN(ot, 1, reg); + gen_op_mov_reg_v(ot, reg, cpu_T[1]); } static inline void gen_op_mov_reg_A0(int size, int reg) @@ -345,23 +339,28 @@ static inline void gen_op_mov_reg_A0(int size, int reg) } } -static inline void gen_op_mov_TN_reg(int ot, int t_index, int reg) +static inline void gen_op_mov_v_reg(int ot, TCGv t0, int reg) { switch(ot) { case OT_BYTE: if (reg < 4 X86_64_DEF( || reg >= 8 || x86_64_hregs)) { goto std_case; } else { - tcg_gen_ld8u_tl(cpu_T[t_index], cpu_env, offsetof(CPUState, regs[reg - 4]) + REG_H_OFFSET); + tcg_gen_ld8u_tl(t0, cpu_env, offsetof(CPUState, regs[reg - 4]) + REG_H_OFFSET); } break; default: std_case: - tcg_gen_ld_tl(cpu_T[t_index], cpu_env, offsetof(CPUState, regs[reg])); + tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, regs[reg])); break; } } +static inline void gen_op_mov_TN_reg(int ot, int t_index, int reg) +{ + gen_op_mov_v_reg(ot, cpu_T[t_index], reg); +} + static inline void gen_op_movl_A0_reg(int reg) { tcg_gen_ld32u_tl(cpu_A0, cpu_env, offsetof(CPUState, regs[reg]) + REG_L_OFFSET); @@ -402,31 +401,57 @@ static inline void gen_op_jmp_T0(void) tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUState, eip)); } -static inline void gen_op_addw_ESP_im(int32_t val) +static inline void gen_op_add_reg_im(int size, int reg, int32_t val) { - tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[R_ESP])); - tcg_gen_addi_tl(cpu_tmp0, cpu_tmp0, val); - tcg_gen_st16_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[R_ESP]) + REG_W_OFFSET); + switch(size) { + case 0: + tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg])); + tcg_gen_addi_tl(cpu_tmp0, cpu_tmp0, val); + tcg_gen_st16_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]) + REG_W_OFFSET); + break; + case 1: + tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg])); + tcg_gen_addi_tl(cpu_tmp0, cpu_tmp0, val); +#ifdef TARGET_X86_64 + tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0xffffffff); +#endif + tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg])); + break; +#ifdef TARGET_X86_64 + case 2: + tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg])); + tcg_gen_addi_tl(cpu_tmp0, cpu_tmp0, val); + tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg])); + break; +#endif + } } -static inline void gen_op_addl_ESP_im(int32_t val) +static inline void gen_op_add_reg_T0(int size, int reg) { - tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[R_ESP])); - tcg_gen_addi_tl(cpu_tmp0, cpu_tmp0, val); + switch(size) { + case 0: + tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg])); + tcg_gen_add_tl(cpu_tmp0, cpu_tmp0, cpu_T[0]); + tcg_gen_st16_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]) + REG_W_OFFSET); + break; + case 1: + tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg])); + tcg_gen_add_tl(cpu_tmp0, cpu_tmp0, cpu_T[0]); #ifdef TARGET_X86_64 - tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0xffffffff); + tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0xffffffff); #endif - tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[R_ESP])); -} - + tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg])); + break; #ifdef TARGET_X86_64 -static inline void gen_op_addq_ESP_im(int32_t val) -{ - tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[R_ESP])); - tcg_gen_addi_tl(cpu_tmp0, cpu_tmp0, val); - tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[R_ESP])); -} + case 2: + tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg])); + tcg_gen_add_tl(cpu_tmp0, cpu_tmp0, cpu_T[0]); + tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg])); + break; #endif + } +} static inline void gen_op_set_cc_op(int32_t val) { @@ -484,20 +509,6 @@ static inline void gen_op_addq_A0_reg_sN(int shift, int reg) } #endif -static GenOpFunc *gen_op_cmov_reg_T1_T0[NB_OP_SIZES - 1][CPU_NB_REGS] = { - [0] = { - DEF_REGS(gen_op_cmovw_, _T1_T0) - }, - [1] = { - DEF_REGS(gen_op_cmovl_, _T1_T0) - }, -#ifdef TARGET_X86_64 - [2] = { - DEF_REGS(gen_op_cmovq_, _T1_T0) - }, -#endif -}; - static inline void gen_op_lds_T0_A0(int idx) { int mem_index = (idx >> 2) - 1; @@ -515,90 +526,76 @@ static inline void gen_op_lds_T0_A0(int idx) } } -/* sign does not matter, except for lidt/lgdt call (TODO: fix it) */ -static inline void gen_op_ld_T0_A0(int idx) +static inline void gen_op_ld_v(int idx, TCGv t0, TCGv a0) { int mem_index = (idx >> 2) - 1; switch(idx & 3) { case 0: - tcg_gen_qemu_ld8u(cpu_T[0], cpu_A0, mem_index); + tcg_gen_qemu_ld8u(t0, a0, mem_index); break; case 1: - tcg_gen_qemu_ld16u(cpu_T[0], cpu_A0, mem_index); + tcg_gen_qemu_ld16u(t0, a0, mem_index); break; case 2: - tcg_gen_qemu_ld32u(cpu_T[0], cpu_A0, mem_index); + tcg_gen_qemu_ld32u(t0, a0, mem_index); break; default: case 3: - tcg_gen_qemu_ld64(cpu_T[0], cpu_A0, mem_index); + /* Should never happen on 32-bit targets. */ +#ifdef TARGET_X86_64 + tcg_gen_qemu_ld64(t0, a0, mem_index); +#endif break; } } +/* XXX: always use ldu or lds */ +static inline void gen_op_ld_T0_A0(int idx) +{ + gen_op_ld_v(idx, cpu_T[0], cpu_A0); +} + static inline void gen_op_ldu_T0_A0(int idx) { - gen_op_ld_T0_A0(idx); + gen_op_ld_v(idx, cpu_T[0], cpu_A0); } static inline void gen_op_ld_T1_A0(int idx) { + gen_op_ld_v(idx, cpu_T[1], cpu_A0); +} + +static inline void gen_op_st_v(int idx, TCGv t0, TCGv a0) +{ int mem_index = (idx >> 2) - 1; switch(idx & 3) { case 0: - tcg_gen_qemu_ld8u(cpu_T[1], cpu_A0, mem_index); + tcg_gen_qemu_st8(t0, a0, mem_index); break; case 1: - tcg_gen_qemu_ld16u(cpu_T[1], cpu_A0, mem_index); + tcg_gen_qemu_st16(t0, a0, mem_index); break; case 2: - tcg_gen_qemu_ld32u(cpu_T[1], cpu_A0, mem_index); + tcg_gen_qemu_st32(t0, a0, mem_index); break; default: case 3: - tcg_gen_qemu_ld64(cpu_T[1], cpu_A0, mem_index); + /* Should never happen on 32-bit targets. */ +#ifdef TARGET_X86_64 + tcg_gen_qemu_st64(t0, a0, mem_index); +#endif break; } } static inline void gen_op_st_T0_A0(int idx) { - int mem_index = (idx >> 2) - 1; - switch(idx & 3) { - case 0: - tcg_gen_qemu_st8(cpu_T[0], cpu_A0, mem_index); - break; - case 1: - tcg_gen_qemu_st16(cpu_T[0], cpu_A0, mem_index); - break; - case 2: - tcg_gen_qemu_st32(cpu_T[0], cpu_A0, mem_index); - break; - default: - case 3: - tcg_gen_qemu_st64(cpu_T[0], cpu_A0, mem_index); - break; - } + gen_op_st_v(idx, cpu_T[0], cpu_A0); } static inline void gen_op_st_T1_A0(int idx) { - int mem_index = (idx >> 2) - 1; - switch(idx & 3) { - case 0: - tcg_gen_qemu_st8(cpu_T[1], cpu_A0, mem_index); - break; - case 1: - tcg_gen_qemu_st16(cpu_T[1], cpu_A0, mem_index); - break; - case 2: - tcg_gen_qemu_st32(cpu_T[1], cpu_A0, mem_index); - break; - default: - case 3: - tcg_gen_qemu_st64(cpu_T[1], cpu_A0, mem_index); - break; - } + gen_op_st_v(idx, cpu_T[1], cpu_A0); } static inline void gen_jmp_im(target_ulong pc) @@ -663,63 +660,79 @@ static inline void gen_string_movl_A0_EDI(DisasContext *s) } } -static GenOpFunc *gen_op_movl_T0_Dshift[4] = { - gen_op_movl_T0_Dshiftb, - gen_op_movl_T0_Dshiftw, - gen_op_movl_T0_Dshiftl, - X86_64_ONLY(gen_op_movl_T0_Dshiftq), +static inline void gen_op_movl_T0_Dshift(int ot) +{ + tcg_gen_ld32s_tl(cpu_T[0], cpu_env, offsetof(CPUState, df)); + tcg_gen_shli_tl(cpu_T[0], cpu_T[0], ot); }; -static GenOpFunc1 *gen_op_jnz_ecx[3] = { - gen_op_jnz_ecxw, - gen_op_jnz_ecxl, - X86_64_ONLY(gen_op_jnz_ecxq), -}; +static void gen_extu(int ot, TCGv reg) +{ + switch(ot) { + case OT_BYTE: + tcg_gen_ext8u_tl(reg, reg); + break; + case OT_WORD: + tcg_gen_ext16u_tl(reg, reg); + break; + case OT_LONG: + tcg_gen_ext32u_tl(reg, reg); + break; + default: + break; + } +} -static GenOpFunc1 *gen_op_jz_ecx[3] = { - gen_op_jz_ecxw, - gen_op_jz_ecxl, - X86_64_ONLY(gen_op_jz_ecxq), -}; +static void gen_exts(int ot, TCGv reg) +{ + switch(ot) { + case OT_BYTE: + tcg_gen_ext8s_tl(reg, reg); + break; + case OT_WORD: + tcg_gen_ext16s_tl(reg, reg); + break; + case OT_LONG: + tcg_gen_ext32s_tl(reg, reg); + break; + default: + break; + } +} -static GenOpFunc *gen_op_dec_ECX[3] = { - gen_op_decw_ECX, - gen_op_decl_ECX, - X86_64_ONLY(gen_op_decq_ECX), -}; +static inline void gen_op_jnz_ecx(int size, int label1) +{ + tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[R_ECX])); + gen_extu(size + 1, cpu_tmp0); + tcg_gen_brcondi_tl(TCG_COND_NE, cpu_tmp0, 0, label1); +} -static GenOpFunc1 *gen_op_string_jnz_sub[2][4] = { - { - gen_op_jnz_subb, - gen_op_jnz_subw, - gen_op_jnz_subl, - X86_64_ONLY(gen_op_jnz_subq), - }, - { - gen_op_jz_subb, - gen_op_jz_subw, - gen_op_jz_subl, - X86_64_ONLY(gen_op_jz_subq), - }, -}; +static inline void gen_op_jz_ecx(int size, int label1) +{ + tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[R_ECX])); + gen_extu(size + 1, cpu_tmp0); + tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, label1); +} -static void *helper_in_func[3] = { - helper_inb, - helper_inw, - helper_inl, -}; +static void gen_helper_in_func(int ot, TCGv v, TCGv_i32 n) +{ + switch (ot) { + case 0: gen_helper_inb(v, n); break; + case 1: gen_helper_inw(v, n); break; + case 2: gen_helper_inl(v, n); break; + } -static void *helper_out_func[3] = { - helper_outb, - helper_outw, - helper_outl, -}; +} -static void *gen_check_io_func[3] = { - helper_check_iob, - helper_check_iow, - helper_check_iol, -}; +static void gen_helper_out_func(int ot, TCGv_i32 v, TCGv_i32 n) +{ + switch (ot) { + case 0: gen_helper_outb(v, n); break; + case 1: gen_helper_outw(v, n); break; + case 2: gen_helper_outl(v, n); break; + } + +} static void gen_check_io(DisasContext *s, int ot, target_ulong cur_eip, uint32_t svm_flags) @@ -734,10 +747,13 @@ static void gen_check_io(DisasContext *s, int ot, target_ulong cur_eip, gen_jmp_im(cur_eip); state_saved = 1; tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); - tcg_gen_helper_0_1(gen_check_io_func[ot], - cpu_tmp2_i32); + switch (ot) { + case 0: gen_helper_check_iob(cpu_tmp2_i32); break; + case 1: gen_helper_check_iow(cpu_tmp2_i32); break; + case 2: gen_helper_check_iol(cpu_tmp2_i32); break; + } } - if(s->flags & (1ULL << INTERCEPT_IOIO_PROT)) { + if(s->flags & HF_SVMI_MASK) { if (!state_saved) { if (s->cc_op != CC_OP_DYNAMIC) gen_op_set_cc_op(s->cc_op); @@ -747,10 +763,8 @@ static void gen_check_io(DisasContext *s, int ot, target_ulong cur_eip, svm_flags |= (1 << (4 + ot)); next_eip = s->pc - s->cs_base; tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); - tcg_gen_helper_0_3(helper_svm_check_io, - cpu_tmp2_i32, - tcg_const_i32(svm_flags), - tcg_const_i32(next_eip - cur_eip)); + gen_helper_svm_check_io(cpu_tmp2_i32, tcg_const_i32(svm_flags), + tcg_const_i32(next_eip - cur_eip)); } } @@ -760,20 +774,9 @@ static inline void gen_movs(DisasContext *s, int ot) gen_op_ld_T0_A0(ot + s->mem_index); gen_string_movl_A0_EDI(s); gen_op_st_T0_A0(ot + s->mem_index); - gen_op_movl_T0_Dshift[ot](); -#ifdef TARGET_X86_64 - if (s->aflag == 2) { - gen_op_addq_ESI_T0(); - gen_op_addq_EDI_T0(); - } else -#endif - if (s->aflag) { - gen_op_addl_ESI_T0(); - gen_op_addl_EDI_T0(); - } else { - gen_op_addw_ESI_T0(); - gen_op_addw_EDI_T0(); - } + gen_op_movl_T0_Dshift(ot); + gen_op_add_reg_T0(s->aflag, R_ESI); + gen_op_add_reg_T0(s->aflag, R_EDI); } static inline void gen_update_cc_op(DisasContext *s) @@ -814,6 +817,323 @@ static void gen_op_update_neg_cc(void) tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); } +/* compute eflags.C to reg */ +static void gen_compute_eflags_c(TCGv reg) +{ + gen_helper_cc_compute_c(cpu_tmp2_i32, cpu_cc_op); + tcg_gen_extu_i32_tl(reg, cpu_tmp2_i32); +} + +/* compute all eflags to cc_src */ +static void gen_compute_eflags(TCGv reg) +{ + gen_helper_cc_compute_all(cpu_tmp2_i32, cpu_cc_op); + tcg_gen_extu_i32_tl(reg, cpu_tmp2_i32); +} + +static inline void gen_setcc_slow_T0(DisasContext *s, int jcc_op) +{ + if (s->cc_op != CC_OP_DYNAMIC) + gen_op_set_cc_op(s->cc_op); + switch(jcc_op) { + case JCC_O: + gen_compute_eflags(cpu_T[0]); + tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 11); + tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1); + break; + case JCC_B: + gen_compute_eflags_c(cpu_T[0]); + break; + case JCC_Z: + gen_compute_eflags(cpu_T[0]); + tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 6); + tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1); + break; + case JCC_BE: + gen_compute_eflags(cpu_tmp0); + tcg_gen_shri_tl(cpu_T[0], cpu_tmp0, 6); + tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_tmp0); + tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1); + break; + case JCC_S: + gen_compute_eflags(cpu_T[0]); + tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 7); + tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1); + break; + case JCC_P: + gen_compute_eflags(cpu_T[0]); + tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 2); + tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1); + break; + case JCC_L: + gen_compute_eflags(cpu_tmp0); + tcg_gen_shri_tl(cpu_T[0], cpu_tmp0, 11); /* CC_O */ + tcg_gen_shri_tl(cpu_tmp0, cpu_tmp0, 7); /* CC_S */ + tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_tmp0); + tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1); + break; + default: + case JCC_LE: + gen_compute_eflags(cpu_tmp0); + tcg_gen_shri_tl(cpu_T[0], cpu_tmp0, 11); /* CC_O */ + tcg_gen_shri_tl(cpu_tmp4, cpu_tmp0, 7); /* CC_S */ + tcg_gen_shri_tl(cpu_tmp0, cpu_tmp0, 6); /* CC_Z */ + tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_tmp4); + tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_tmp0); + tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1); + break; + } +} + +/* return true if setcc_slow is not needed (WARNING: must be kept in + sync with gen_jcc1) */ +static int is_fast_jcc_case(DisasContext *s, int b) +{ + int jcc_op; + jcc_op = (b >> 1) & 7; + switch(s->cc_op) { + /* we optimize the cmp/jcc case */ + case CC_OP_SUBB: + case CC_OP_SUBW: + case CC_OP_SUBL: + case CC_OP_SUBQ: + if (jcc_op == JCC_O || jcc_op == JCC_P) + goto slow_jcc; + break; + + /* some jumps are easy to compute */ + case CC_OP_ADDB: + case CC_OP_ADDW: + case CC_OP_ADDL: + case CC_OP_ADDQ: + + case CC_OP_LOGICB: + case CC_OP_LOGICW: + case CC_OP_LOGICL: + case CC_OP_LOGICQ: + + case CC_OP_INCB: + case CC_OP_INCW: + case CC_OP_INCL: + case CC_OP_INCQ: + + case CC_OP_DECB: + case CC_OP_DECW: + case CC_OP_DECL: + case CC_OP_DECQ: + + case CC_OP_SHLB: + case CC_OP_SHLW: + case CC_OP_SHLL: + case CC_OP_SHLQ: + if (jcc_op != JCC_Z && jcc_op != JCC_S) + goto slow_jcc; + break; + default: + slow_jcc: + return 0; + } + return 1; +} + +/* generate a conditional jump to label 'l1' according to jump opcode + value 'b'. In the fast case, T0 is guaranted not to be used. */ +static inline void gen_jcc1(DisasContext *s, int cc_op, int b, int l1) +{ + int inv, jcc_op, size, cond; + TCGv t0; + + inv = b & 1; + jcc_op = (b >> 1) & 7; + + switch(cc_op) { + /* we optimize the cmp/jcc case */ + case CC_OP_SUBB: + case CC_OP_SUBW: + case CC_OP_SUBL: + case CC_OP_SUBQ: + + size = cc_op - CC_OP_SUBB; + switch(jcc_op) { + case JCC_Z: + fast_jcc_z: + switch(size) { + case 0: + tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0xff); + t0 = cpu_tmp0; + break; + case 1: + tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0xffff); + t0 = cpu_tmp0; + break; +#ifdef TARGET_X86_64 + case 2: + tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0xffffffff); + t0 = cpu_tmp0; + break; +#endif + default: + t0 = cpu_cc_dst; + break; + } + tcg_gen_brcondi_tl(inv ? TCG_COND_NE : TCG_COND_EQ, t0, 0, l1); + break; + case JCC_S: + fast_jcc_s: + switch(size) { + case 0: + tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0x80); + tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE, cpu_tmp0, + 0, l1); + break; + case 1: + tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0x8000); + tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE, cpu_tmp0, + 0, l1); + break; +#ifdef TARGET_X86_64 + case 2: + tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0x80000000); + tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE, cpu_tmp0, + 0, l1); + break; +#endif + default: + tcg_gen_brcondi_tl(inv ? TCG_COND_GE : TCG_COND_LT, cpu_cc_dst, + 0, l1); + break; + } + break; + + case JCC_B: + cond = inv ? TCG_COND_GEU : TCG_COND_LTU; + goto fast_jcc_b; + case JCC_BE: + cond = inv ? TCG_COND_GTU : TCG_COND_LEU; + fast_jcc_b: + tcg_gen_add_tl(cpu_tmp4, cpu_cc_dst, cpu_cc_src); + switch(size) { + case 0: + t0 = cpu_tmp0; + tcg_gen_andi_tl(cpu_tmp4, cpu_tmp4, 0xff); + tcg_gen_andi_tl(t0, cpu_cc_src, 0xff); + break; + case 1: + t0 = cpu_tmp0; + tcg_gen_andi_tl(cpu_tmp4, cpu_tmp4, 0xffff); + tcg_gen_andi_tl(t0, cpu_cc_src, 0xffff); + break; +#ifdef TARGET_X86_64 + case 2: + t0 = cpu_tmp0; + tcg_gen_andi_tl(cpu_tmp4, cpu_tmp4, 0xffffffff); + tcg_gen_andi_tl(t0, cpu_cc_src, 0xffffffff); + break; +#endif + default: + t0 = cpu_cc_src; + break; + } + tcg_gen_brcond_tl(cond, cpu_tmp4, t0, l1); + break; + + case JCC_L: + cond = inv ? TCG_COND_GE : TCG_COND_LT; + goto fast_jcc_l; + case JCC_LE: + cond = inv ? TCG_COND_GT : TCG_COND_LE; + fast_jcc_l: + tcg_gen_add_tl(cpu_tmp4, cpu_cc_dst, cpu_cc_src); + switch(size) { + case 0: + t0 = cpu_tmp0; + tcg_gen_ext8s_tl(cpu_tmp4, cpu_tmp4); + tcg_gen_ext8s_tl(t0, cpu_cc_src); + break; + case 1: + t0 = cpu_tmp0; + tcg_gen_ext16s_tl(cpu_tmp4, cpu_tmp4); + tcg_gen_ext16s_tl(t0, cpu_cc_src); + break; +#ifdef TARGET_X86_64 + case 2: + t0 = cpu_tmp0; + tcg_gen_ext32s_tl(cpu_tmp4, cpu_tmp4); + tcg_gen_ext32s_tl(t0, cpu_cc_src); + break; +#endif + default: + t0 = cpu_cc_src; + break; + } + tcg_gen_brcond_tl(cond, cpu_tmp4, t0, l1); + break; + + default: + goto slow_jcc; + } + break; + + /* some jumps are easy to compute */ + case CC_OP_ADDB: + case CC_OP_ADDW: + case CC_OP_ADDL: + case CC_OP_ADDQ: + + case CC_OP_ADCB: + case CC_OP_ADCW: + case CC_OP_ADCL: + case CC_OP_ADCQ: + + case CC_OP_SBBB: + case CC_OP_SBBW: + case CC_OP_SBBL: + case CC_OP_SBBQ: + + case CC_OP_LOGICB: + case CC_OP_LOGICW: + case CC_OP_LOGICL: + case CC_OP_LOGICQ: + + case CC_OP_INCB: + case CC_OP_INCW: + case CC_OP_INCL: + case CC_OP_INCQ: + + case CC_OP_DECB: + case CC_OP_DECW: + case CC_OP_DECL: + case CC_OP_DECQ: + + case CC_OP_SHLB: + case CC_OP_SHLW: + case CC_OP_SHLL: + case CC_OP_SHLQ: + + case CC_OP_SARB: + case CC_OP_SARW: + case CC_OP_SARL: + case CC_OP_SARQ: + switch(jcc_op) { + case JCC_Z: + size = (cc_op - CC_OP_ADDB) & 3; + goto fast_jcc_z; + case JCC_S: + size = (cc_op - CC_OP_ADDB) & 3; + goto fast_jcc_s; + default: + goto slow_jcc; + } + break; + default: + slow_jcc: + gen_setcc_slow_T0(s, jcc_op); + tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE, + cpu_T[0], 0, l1); + break; + } +} + /* XXX: does not work with gdbstub "ice" single step - not a serious problem */ static int gen_jz_ecx_string(DisasContext *s, target_ulong next_eip) @@ -822,7 +1142,7 @@ static int gen_jz_ecx_string(DisasContext *s, target_ulong next_eip) l1 = gen_new_label(); l2 = gen_new_label(); - gen_op_jnz_ecx[s->aflag](l1); + gen_op_jnz_ecx(s->aflag, l1); gen_set_label(l2); gen_jmp_tb(s, next_eip, 1); gen_set_label(l1); @@ -834,17 +1154,8 @@ static inline void gen_stos(DisasContext *s, int ot) gen_op_mov_TN_reg(OT_LONG, 0, R_EAX); gen_string_movl_A0_EDI(s); gen_op_st_T0_A0(ot + s->mem_index); - gen_op_movl_T0_Dshift[ot](); -#ifdef TARGET_X86_64 - if (s->aflag == 2) { - gen_op_addq_EDI_T0(); - } else -#endif - if (s->aflag) { - gen_op_addl_EDI_T0(); - } else { - gen_op_addw_EDI_T0(); - } + gen_op_movl_T0_Dshift(ot); + gen_op_add_reg_T0(s->aflag, R_EDI); } static inline void gen_lods(DisasContext *s, int ot) @@ -852,17 +1163,8 @@ static inline void gen_lods(DisasContext *s, int ot) gen_string_movl_A0_ESI(s); gen_op_ld_T0_A0(ot + s->mem_index); gen_op_mov_reg_T0(ot, R_EAX); - gen_op_movl_T0_Dshift[ot](); -#ifdef TARGET_X86_64 - if (s->aflag == 2) { - gen_op_addq_ESI_T0(); - } else -#endif - if (s->aflag) { - gen_op_addl_ESI_T0(); - } else { - gen_op_addw_ESI_T0(); - } + gen_op_movl_T0_Dshift(ot); + gen_op_add_reg_T0(s->aflag, R_ESI); } static inline void gen_scas(DisasContext *s, int ot) @@ -871,17 +1173,8 @@ static inline void gen_scas(DisasContext *s, int ot) gen_string_movl_A0_EDI(s); gen_op_ld_T1_A0(ot + s->mem_index); gen_op_cmpl_T0_T1_cc(); - gen_op_movl_T0_Dshift[ot](); -#ifdef TARGET_X86_64 - if (s->aflag == 2) { - gen_op_addq_EDI_T0(); - } else -#endif - if (s->aflag) { - gen_op_addl_EDI_T0(); - } else { - gen_op_addw_EDI_T0(); - } + gen_op_movl_T0_Dshift(ot); + gen_op_add_reg_T0(s->aflag, R_EDI); } static inline void gen_cmps(DisasContext *s, int ot) @@ -891,47 +1184,35 @@ static inline void gen_cmps(DisasContext *s, int ot) gen_string_movl_A0_EDI(s); gen_op_ld_T1_A0(ot + s->mem_index); gen_op_cmpl_T0_T1_cc(); - gen_op_movl_T0_Dshift[ot](); -#ifdef TARGET_X86_64 - if (s->aflag == 2) { - gen_op_addq_ESI_T0(); - gen_op_addq_EDI_T0(); - } else -#endif - if (s->aflag) { - gen_op_addl_ESI_T0(); - gen_op_addl_EDI_T0(); - } else { - gen_op_addw_ESI_T0(); - gen_op_addw_EDI_T0(); - } + gen_op_movl_T0_Dshift(ot); + gen_op_add_reg_T0(s->aflag, R_ESI); + gen_op_add_reg_T0(s->aflag, R_EDI); } static inline void gen_ins(DisasContext *s, int ot) { + if (use_icount) + gen_io_start(); gen_string_movl_A0_EDI(s); + /* Note: we must do this dummy write first to be restartable in + case of page fault. */ gen_op_movl_T0_0(); gen_op_st_T0_A0(ot + s->mem_index); gen_op_mov_TN_reg(OT_WORD, 1, R_EDX); tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[1]); tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff); - tcg_gen_helper_1_1(helper_in_func[ot], cpu_T[0], cpu_tmp2_i32); + gen_helper_in_func(ot, cpu_T[0], cpu_tmp2_i32); gen_op_st_T0_A0(ot + s->mem_index); - gen_op_movl_T0_Dshift[ot](); -#ifdef TARGET_X86_64 - if (s->aflag == 2) { - gen_op_addq_EDI_T0(); - } else -#endif - if (s->aflag) { - gen_op_addl_EDI_T0(); - } else { - gen_op_addw_EDI_T0(); - } + gen_op_movl_T0_Dshift(ot); + gen_op_add_reg_T0(s->aflag, R_EDI); + if (use_icount) + gen_io_end(); } static inline void gen_outs(DisasContext *s, int ot) { + if (use_icount) + gen_io_start(); gen_string_movl_A0_ESI(s); gen_op_ld_T0_A0(ot + s->mem_index); @@ -939,19 +1220,12 @@ static inline void gen_outs(DisasContext *s, int ot) tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[1]); tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff); tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[0]); - tcg_gen_helper_0_2(helper_out_func[ot], cpu_tmp2_i32, cpu_tmp3_i32); + gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32); - gen_op_movl_T0_Dshift[ot](); -#ifdef TARGET_X86_64 - if (s->aflag == 2) { - gen_op_addq_ESI_T0(); - } else -#endif - if (s->aflag) { - gen_op_addl_ESI_T0(); - } else { - gen_op_addw_ESI_T0(); - } + gen_op_movl_T0_Dshift(ot); + gen_op_add_reg_T0(s->aflag, R_ESI); + if (use_icount) + gen_io_end(); } /* same method as Valgrind : we generate jumps to current or next @@ -964,236 +1238,66 @@ static inline void gen_repz_ ## op(DisasContext *s, int ot, \ gen_update_cc_op(s); \ l2 = gen_jz_ecx_string(s, next_eip); \ gen_ ## op(s, ot); \ - gen_op_dec_ECX[s->aflag](); \ + gen_op_add_reg_im(s->aflag, R_ECX, -1); \ /* a loop would cause two single step exceptions if ECX = 1 \ before rep string_insn */ \ - if (!s->jmp_opt) \ - gen_op_jz_ecx[s->aflag](l2); \ - gen_jmp(s, cur_eip); \ -} - -#define GEN_REPZ2(op) \ -static inline void gen_repz_ ## op(DisasContext *s, int ot, \ - target_ulong cur_eip, \ - target_ulong next_eip, \ - int nz) \ -{ \ - int l2;\ - gen_update_cc_op(s); \ - l2 = gen_jz_ecx_string(s, next_eip); \ - gen_ ## op(s, ot); \ - gen_op_dec_ECX[s->aflag](); \ - gen_op_set_cc_op(CC_OP_SUBB + ot); \ - gen_op_string_jnz_sub[nz][ot](l2);\ - if (!s->jmp_opt) \ - gen_op_jz_ecx[s->aflag](l2); \ - gen_jmp(s, cur_eip); \ -} - -GEN_REPZ(movs) -GEN_REPZ(stos) -GEN_REPZ(lods) -GEN_REPZ(ins) -GEN_REPZ(outs) -GEN_REPZ2(scas) -GEN_REPZ2(cmps) - -enum { - JCC_O, - JCC_B, - JCC_Z, - JCC_BE, - JCC_S, - JCC_P, - JCC_L, - JCC_LE, -}; - -static GenOpFunc1 *gen_jcc_sub[4][8] = { - [OT_BYTE] = { - NULL, - gen_op_jb_subb, - gen_op_jz_subb, - gen_op_jbe_subb, - gen_op_js_subb, - NULL, - gen_op_jl_subb, - gen_op_jle_subb, - }, - [OT_WORD] = { - NULL, - gen_op_jb_subw, - gen_op_jz_subw, - gen_op_jbe_subw, - gen_op_js_subw, - NULL, - gen_op_jl_subw, - gen_op_jle_subw, - }, - [OT_LONG] = { - NULL, - gen_op_jb_subl, - gen_op_jz_subl, - gen_op_jbe_subl, - gen_op_js_subl, - NULL, - gen_op_jl_subl, - gen_op_jle_subl, - }, -#ifdef TARGET_X86_64 - [OT_QUAD] = { - NULL, - BUGGY_64(gen_op_jb_subq), - gen_op_jz_subq, - BUGGY_64(gen_op_jbe_subq), - gen_op_js_subq, - NULL, - BUGGY_64(gen_op_jl_subq), - BUGGY_64(gen_op_jle_subq), - }, -#endif -}; -static GenOpFunc1 *gen_op_loop[3][4] = { - [0] = { - gen_op_loopnzw, - gen_op_loopzw, - gen_op_jnz_ecxw, - }, - [1] = { - gen_op_loopnzl, - gen_op_loopzl, - gen_op_jnz_ecxl, - }, -#ifdef TARGET_X86_64 - [2] = { - gen_op_loopnzq, - gen_op_loopzq, - gen_op_jnz_ecxq, - }, -#endif -}; - -static GenOpFunc *gen_setcc_slow[8] = { - gen_op_seto_T0_cc, - gen_op_setb_T0_cc, - gen_op_setz_T0_cc, - gen_op_setbe_T0_cc, - gen_op_sets_T0_cc, - gen_op_setp_T0_cc, - gen_op_setl_T0_cc, - gen_op_setle_T0_cc, -}; - -static GenOpFunc *gen_setcc_sub[4][8] = { - [OT_BYTE] = { - NULL, - gen_op_setb_T0_subb, - gen_op_setz_T0_subb, - gen_op_setbe_T0_subb, - gen_op_sets_T0_subb, - NULL, - gen_op_setl_T0_subb, - gen_op_setle_T0_subb, - }, - [OT_WORD] = { - NULL, - gen_op_setb_T0_subw, - gen_op_setz_T0_subw, - gen_op_setbe_T0_subw, - gen_op_sets_T0_subw, - NULL, - gen_op_setl_T0_subw, - gen_op_setle_T0_subw, - }, - [OT_LONG] = { - NULL, - gen_op_setb_T0_subl, - gen_op_setz_T0_subl, - gen_op_setbe_T0_subl, - gen_op_sets_T0_subl, - NULL, - gen_op_setl_T0_subl, - gen_op_setle_T0_subl, - }, -#ifdef TARGET_X86_64 - [OT_QUAD] = { - NULL, - gen_op_setb_T0_subq, - gen_op_setz_T0_subq, - gen_op_setbe_T0_subq, - gen_op_sets_T0_subq, - NULL, - gen_op_setl_T0_subq, - gen_op_setle_T0_subq, - }, -#endif -}; + if (!s->jmp_opt) \ + gen_op_jz_ecx(s->aflag, l2); \ + gen_jmp(s, cur_eip); \ +} -static void *helper_fp_arith_ST0_FT0[8] = { - helper_fadd_ST0_FT0, - helper_fmul_ST0_FT0, - helper_fcom_ST0_FT0, - helper_fcom_ST0_FT0, - helper_fsub_ST0_FT0, - helper_fsubr_ST0_FT0, - helper_fdiv_ST0_FT0, - helper_fdivr_ST0_FT0, -}; +#define GEN_REPZ2(op) \ +static inline void gen_repz_ ## op(DisasContext *s, int ot, \ + target_ulong cur_eip, \ + target_ulong next_eip, \ + int nz) \ +{ \ + int l2;\ + gen_update_cc_op(s); \ + l2 = gen_jz_ecx_string(s, next_eip); \ + gen_ ## op(s, ot); \ + gen_op_add_reg_im(s->aflag, R_ECX, -1); \ + gen_op_set_cc_op(CC_OP_SUBB + ot); \ + gen_jcc1(s, CC_OP_SUBB + ot, (JCC_Z << 1) | (nz ^ 1), l2); \ + if (!s->jmp_opt) \ + gen_op_jz_ecx(s->aflag, l2); \ + gen_jmp(s, cur_eip); \ +} -/* NOTE the exception in "r" op ordering */ -static void *helper_fp_arith_STN_ST0[8] = { - helper_fadd_STN_ST0, - helper_fmul_STN_ST0, - NULL, - NULL, - helper_fsubr_STN_ST0, - helper_fsub_STN_ST0, - helper_fdivr_STN_ST0, - helper_fdiv_STN_ST0, -}; +GEN_REPZ(movs) +GEN_REPZ(stos) +GEN_REPZ(lods) +GEN_REPZ(ins) +GEN_REPZ(outs) +GEN_REPZ2(scas) +GEN_REPZ2(cmps) -/* compute eflags.C to reg */ -static void gen_compute_eflags_c(TCGv reg) +static void gen_helper_fp_arith_ST0_FT0(int op) { -#if TCG_TARGET_REG_BITS == 32 - tcg_gen_shli_i32(cpu_tmp2_i32, cpu_cc_op, 3); - tcg_gen_addi_i32(cpu_tmp2_i32, cpu_tmp2_i32, - (long)cc_table + offsetof(CCTable, compute_c)); - tcg_gen_ld_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0); - tcg_gen_call(&tcg_ctx, cpu_tmp2_i32, TCG_CALL_PURE, - 1, &cpu_tmp2_i32, 0, NULL); -#else - tcg_gen_extu_i32_tl(cpu_tmp1_i64, cpu_cc_op); - tcg_gen_shli_i64(cpu_tmp1_i64, cpu_tmp1_i64, 4); - tcg_gen_addi_i64(cpu_tmp1_i64, cpu_tmp1_i64, - (long)cc_table + offsetof(CCTable, compute_c)); - tcg_gen_ld_i64(cpu_tmp1_i64, cpu_tmp1_i64, 0); - tcg_gen_call(&tcg_ctx, cpu_tmp1_i64, TCG_CALL_PURE, - 1, &cpu_tmp2_i32, 0, NULL); -#endif - tcg_gen_extu_i32_tl(reg, cpu_tmp2_i32); + switch (op) { + case 0: gen_helper_fadd_ST0_FT0(); break; + case 1: gen_helper_fmul_ST0_FT0(); break; + case 2: gen_helper_fcom_ST0_FT0(); break; + case 3: gen_helper_fcom_ST0_FT0(); break; + case 4: gen_helper_fsub_ST0_FT0(); break; + case 5: gen_helper_fsubr_ST0_FT0(); break; + case 6: gen_helper_fdiv_ST0_FT0(); break; + case 7: gen_helper_fdivr_ST0_FT0(); break; + } } -/* compute all eflags to cc_src */ -static void gen_compute_eflags(TCGv reg) +/* NOTE the exception in "r" op ordering */ +static void gen_helper_fp_arith_STN_ST0(int op, int opreg) { -#if TCG_TARGET_REG_BITS == 32 - tcg_gen_shli_i32(cpu_tmp2_i32, cpu_cc_op, 3); - tcg_gen_addi_i32(cpu_tmp2_i32, cpu_tmp2_i32, - (long)cc_table + offsetof(CCTable, compute_all)); - tcg_gen_ld_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0); - tcg_gen_call(&tcg_ctx, cpu_tmp2_i32, TCG_CALL_PURE, - 1, &cpu_tmp2_i32, 0, NULL); -#else - tcg_gen_extu_i32_tl(cpu_tmp1_i64, cpu_cc_op); - tcg_gen_shli_i64(cpu_tmp1_i64, cpu_tmp1_i64, 4); - tcg_gen_addi_i64(cpu_tmp1_i64, cpu_tmp1_i64, - (long)cc_table + offsetof(CCTable, compute_all)); - tcg_gen_ld_i64(cpu_tmp1_i64, cpu_tmp1_i64, 0); - tcg_gen_call(&tcg_ctx, cpu_tmp1_i64, TCG_CALL_PURE, - 1, &cpu_tmp2_i32, 0, NULL); -#endif - tcg_gen_extu_i32_tl(reg, cpu_tmp2_i32); + TCGv_i32 tmp = tcg_const_i32(opreg); + switch (op) { + case 0: gen_helper_fadd_STN_ST0(tmp); break; + case 1: gen_helper_fmul_STN_ST0(tmp); break; + case 4: gen_helper_fsubr_STN_ST0(tmp); break; + case 5: gen_helper_fsub_STN_ST0(tmp); break; + case 6: gen_helper_fdivr_STN_ST0(tmp); break; + case 7: gen_helper_fdiv_STN_ST0(tmp); break; + } } /* if d == OR_TMP0, it means memory operand (address in A0) */ @@ -1312,51 +1416,17 @@ static void gen_inc(DisasContext *s1, int ot, int d, int c) gen_op_mov_reg_T0(ot, d); else gen_op_st_T0_A0(ot + s1->mem_index); - tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); gen_compute_eflags_c(cpu_cc_src); + tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); } -static void gen_extu(int ot, TCGv reg) -{ - switch(ot) { - case OT_BYTE: - tcg_gen_ext8u_tl(reg, reg); - break; - case OT_WORD: - tcg_gen_ext16u_tl(reg, reg); - break; - case OT_LONG: - tcg_gen_ext32u_tl(reg, reg); - break; - default: - break; - } -} - -static void gen_exts(int ot, TCGv reg) -{ - switch(ot) { - case OT_BYTE: - tcg_gen_ext8s_tl(reg, reg); - break; - case OT_WORD: - tcg_gen_ext16s_tl(reg, reg); - break; - case OT_LONG: - tcg_gen_ext32s_tl(reg, reg); - break; - default: - break; - } -} - -/* XXX: add faster immediate case */ static void gen_shift_rm_T1(DisasContext *s, int ot, int op1, int is_right, int is_arith) { target_ulong mask; int shift_label; - + TCGv t0, t1; + if (ot == OT_QUAD) mask = 0x3f; else @@ -1397,11 +1467,18 @@ static void gen_shift_rm_T1(DisasContext *s, int ot, int op1, if (s->cc_op != CC_OP_DYNAMIC) gen_op_set_cc_op(s->cc_op); + /* XXX: inefficient */ + t0 = tcg_temp_local_new(); + t1 = tcg_temp_local_new(); + + tcg_gen_mov_tl(t0, cpu_T[0]); + tcg_gen_mov_tl(t1, cpu_T3); + shift_label = gen_new_label(); - tcg_gen_brcond_tl(TCG_COND_EQ, cpu_T[1], tcg_const_tl(0), shift_label); + tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_T[1], 0, shift_label); - tcg_gen_mov_tl(cpu_cc_src, cpu_T3); - tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); + tcg_gen_mov_tl(cpu_cc_src, t1); + tcg_gen_mov_tl(cpu_cc_dst, t0); if (is_right) tcg_gen_movi_i32(cpu_cc_op, CC_OP_SARB + ot); else @@ -1409,6 +1486,60 @@ static void gen_shift_rm_T1(DisasContext *s, int ot, int op1, gen_set_label(shift_label); s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */ + + tcg_temp_free(t0); + tcg_temp_free(t1); +} + +static void gen_shift_rm_im(DisasContext *s, int ot, int op1, int op2, + int is_right, int is_arith) +{ + int mask; + + if (ot == OT_QUAD) + mask = 0x3f; + else + mask = 0x1f; + + /* load */ + if (op1 == OR_TMP0) + gen_op_ld_T0_A0(ot + s->mem_index); + else + gen_op_mov_TN_reg(ot, 0, op1); + + op2 &= mask; + if (op2 != 0) { + if (is_right) { + if (is_arith) { + gen_exts(ot, cpu_T[0]); + tcg_gen_sari_tl(cpu_tmp4, cpu_T[0], op2 - 1); + tcg_gen_sari_tl(cpu_T[0], cpu_T[0], op2); + } else { + gen_extu(ot, cpu_T[0]); + tcg_gen_shri_tl(cpu_tmp4, cpu_T[0], op2 - 1); + tcg_gen_shri_tl(cpu_T[0], cpu_T[0], op2); + } + } else { + tcg_gen_shli_tl(cpu_tmp4, cpu_T[0], op2 - 1); + tcg_gen_shli_tl(cpu_T[0], cpu_T[0], op2); + } + } + + /* store */ + if (op1 == OR_TMP0) + gen_op_st_T0_A0(ot + s->mem_index); + else + gen_op_mov_reg_T0(ot, op1); + + /* update eflags if non zero shift */ + if (op2 != 0) { + tcg_gen_mov_tl(cpu_cc_src, cpu_tmp4); + tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); + if (is_right) + s->cc_op = CC_OP_SARB + ot; + else + s->cc_op = CC_OP_SHLB + ot; + } } static inline void tcg_gen_lshift(TCGv ret, TCGv arg1, target_long arg2) @@ -1419,96 +1550,178 @@ static inline void tcg_gen_lshift(TCGv ret, TCGv arg1, target_long arg2) tcg_gen_shri_tl(ret, arg1, -arg2); } -/* XXX: add faster immediate case */ static void gen_rot_rm_T1(DisasContext *s, int ot, int op1, int is_right) { target_ulong mask; int label1, label2, data_bits; - + TCGv t0, t1, t2, a0; + + /* XXX: inefficient, but we must use local temps */ + t0 = tcg_temp_local_new(); + t1 = tcg_temp_local_new(); + t2 = tcg_temp_local_new(); + a0 = tcg_temp_local_new(); + if (ot == OT_QUAD) mask = 0x3f; else mask = 0x1f; /* load */ - if (op1 == OR_TMP0) - gen_op_ld_T0_A0(ot + s->mem_index); - else - gen_op_mov_TN_reg(ot, 0, op1); + if (op1 == OR_TMP0) { + tcg_gen_mov_tl(a0, cpu_A0); + gen_op_ld_v(ot + s->mem_index, t0, a0); + } else { + gen_op_mov_v_reg(ot, t0, op1); + } - tcg_gen_andi_tl(cpu_T[1], cpu_T[1], mask); + tcg_gen_mov_tl(t1, cpu_T[1]); + + tcg_gen_andi_tl(t1, t1, mask); /* Must test zero case to avoid using undefined behaviour in TCG shifts. */ label1 = gen_new_label(); - tcg_gen_brcond_tl(TCG_COND_EQ, cpu_T[1], tcg_const_tl(0), label1); + tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, label1); if (ot <= OT_WORD) - tcg_gen_andi_tl(cpu_tmp0, cpu_T[1], (1 << (3 + ot)) - 1); + tcg_gen_andi_tl(cpu_tmp0, t1, (1 << (3 + ot)) - 1); else - tcg_gen_mov_tl(cpu_tmp0, cpu_T[1]); + tcg_gen_mov_tl(cpu_tmp0, t1); - gen_extu(ot, cpu_T[0]); - tcg_gen_mov_tl(cpu_T3, cpu_T[0]); + gen_extu(ot, t0); + tcg_gen_mov_tl(t2, t0); data_bits = 8 << ot; /* XXX: rely on behaviour of shifts when operand 2 overflows (XXX: fix TCG definition) */ if (is_right) { - tcg_gen_shr_tl(cpu_tmp4, cpu_T[0], cpu_tmp0); + tcg_gen_shr_tl(cpu_tmp4, t0, cpu_tmp0); tcg_gen_sub_tl(cpu_tmp0, tcg_const_tl(data_bits), cpu_tmp0); - tcg_gen_shl_tl(cpu_T[0], cpu_T[0], cpu_tmp0); + tcg_gen_shl_tl(t0, t0, cpu_tmp0); } else { - tcg_gen_shl_tl(cpu_tmp4, cpu_T[0], cpu_tmp0); + tcg_gen_shl_tl(cpu_tmp4, t0, cpu_tmp0); tcg_gen_sub_tl(cpu_tmp0, tcg_const_tl(data_bits), cpu_tmp0); - tcg_gen_shr_tl(cpu_T[0], cpu_T[0], cpu_tmp0); + tcg_gen_shr_tl(t0, t0, cpu_tmp0); } - tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_tmp4); + tcg_gen_or_tl(t0, t0, cpu_tmp4); gen_set_label(label1); /* store */ - if (op1 == OR_TMP0) - gen_op_st_T0_A0(ot + s->mem_index); - else - gen_op_mov_reg_T0(ot, op1); + if (op1 == OR_TMP0) { + gen_op_st_v(ot + s->mem_index, t0, a0); + } else { + gen_op_mov_reg_v(ot, op1, t0); + } /* update eflags */ if (s->cc_op != CC_OP_DYNAMIC) gen_op_set_cc_op(s->cc_op); label2 = gen_new_label(); - tcg_gen_brcond_tl(TCG_COND_EQ, cpu_T[1], tcg_const_tl(0), label2); + tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, label2); gen_compute_eflags(cpu_cc_src); tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~(CC_O | CC_C)); - tcg_gen_xor_tl(cpu_tmp0, cpu_T3, cpu_T[0]); + tcg_gen_xor_tl(cpu_tmp0, t2, t0); tcg_gen_lshift(cpu_tmp0, cpu_tmp0, 11 - (data_bits - 1)); tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, CC_O); tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_tmp0); if (is_right) { - tcg_gen_shri_tl(cpu_T[0], cpu_T[0], data_bits - 1); + tcg_gen_shri_tl(t0, t0, data_bits - 1); } - tcg_gen_andi_tl(cpu_T[0], cpu_T[0], CC_C); - tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_T[0]); + tcg_gen_andi_tl(t0, t0, CC_C); + tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, t0); tcg_gen_discard_tl(cpu_cc_dst); tcg_gen_movi_i32(cpu_cc_op, CC_OP_EFLAGS); gen_set_label(label2); s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */ + + tcg_temp_free(t0); + tcg_temp_free(t1); + tcg_temp_free(t2); + tcg_temp_free(a0); } -static void *helper_rotc[8] = { - helper_rclb, - helper_rclw, - helper_rcll, - X86_64_ONLY(helper_rclq), - helper_rcrb, - helper_rcrw, - helper_rcrl, - X86_64_ONLY(helper_rcrq), -}; +static void gen_rot_rm_im(DisasContext *s, int ot, int op1, int op2, + int is_right) +{ + int mask; + int data_bits; + TCGv t0, t1, a0; + + /* XXX: inefficient, but we must use local temps */ + t0 = tcg_temp_local_new(); + t1 = tcg_temp_local_new(); + a0 = tcg_temp_local_new(); + + if (ot == OT_QUAD) + mask = 0x3f; + else + mask = 0x1f; + + /* load */ + if (op1 == OR_TMP0) { + tcg_gen_mov_tl(a0, cpu_A0); + gen_op_ld_v(ot + s->mem_index, t0, a0); + } else { + gen_op_mov_v_reg(ot, t0, op1); + } + + gen_extu(ot, t0); + tcg_gen_mov_tl(t1, t0); + + op2 &= mask; + data_bits = 8 << ot; + if (op2 != 0) { + int shift = op2 & ((1 << (3 + ot)) - 1); + if (is_right) { + tcg_gen_shri_tl(cpu_tmp4, t0, shift); + tcg_gen_shli_tl(t0, t0, data_bits - shift); + } + else { + tcg_gen_shli_tl(cpu_tmp4, t0, shift); + tcg_gen_shri_tl(t0, t0, data_bits - shift); + } + tcg_gen_or_tl(t0, t0, cpu_tmp4); + } + + /* store */ + if (op1 == OR_TMP0) { + gen_op_st_v(ot + s->mem_index, t0, a0); + } else { + gen_op_mov_reg_v(ot, op1, t0); + } + + if (op2 != 0) { + /* update eflags */ + if (s->cc_op != CC_OP_DYNAMIC) + gen_op_set_cc_op(s->cc_op); + + gen_compute_eflags(cpu_cc_src); + tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~(CC_O | CC_C)); + tcg_gen_xor_tl(cpu_tmp0, t1, t0); + tcg_gen_lshift(cpu_tmp0, cpu_tmp0, 11 - (data_bits - 1)); + tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, CC_O); + tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_tmp0); + if (is_right) { + tcg_gen_shri_tl(t0, t0, data_bits - 1); + } + tcg_gen_andi_tl(t0, t0, CC_C); + tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, t0); + + tcg_gen_discard_tl(cpu_cc_dst); + tcg_gen_movi_i32(cpu_cc_op, CC_OP_EFLAGS); + s->cc_op = CC_OP_EFLAGS; + } + + tcg_temp_free(t0); + tcg_temp_free(t1); + tcg_temp_free(a0); +} /* XXX: add faster immediate = 1 case */ static void gen_rotc_rm_T1(DisasContext *s, int ot, int op1, @@ -1525,8 +1738,25 @@ static void gen_rotc_rm_T1(DisasContext *s, int ot, int op1, else gen_op_mov_TN_reg(ot, 0, op1); - tcg_gen_helper_1_2(helper_rotc[ot + (is_right * 4)], - cpu_T[0], cpu_T[0], cpu_T[1]); + if (is_right) { + switch (ot) { + case 0: gen_helper_rcrb(cpu_T[0], cpu_T[0], cpu_T[1]); break; + case 1: gen_helper_rcrw(cpu_T[0], cpu_T[0], cpu_T[1]); break; + case 2: gen_helper_rcrl(cpu_T[0], cpu_T[0], cpu_T[1]); break; +#ifdef TARGET_X86_64 + case 3: gen_helper_rcrq(cpu_T[0], cpu_T[0], cpu_T[1]); break; +#endif + } + } else { + switch (ot) { + case 0: gen_helper_rclb(cpu_T[0], cpu_T[0], cpu_T[1]); break; + case 1: gen_helper_rclw(cpu_T[0], cpu_T[0], cpu_T[1]); break; + case 2: gen_helper_rcll(cpu_T[0], cpu_T[0], cpu_T[1]); break; +#ifdef TARGET_X86_64 + case 3: gen_helper_rclq(cpu_T[0], cpu_T[0], cpu_T[1]); break; +#endif + } + } /* store */ if (op1 == OR_TMP0) gen_op_st_T0_A0(ot + s->mem_index); @@ -1535,9 +1765,9 @@ static void gen_rotc_rm_T1(DisasContext *s, int ot, int op1, /* update eflags */ label1 = gen_new_label(); - tcg_gen_brcond_tl(TCG_COND_EQ, cpu_T3, tcg_const_tl(-1), label1); + tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_cc_tmp, -1, label1); - tcg_gen_mov_tl(cpu_cc_src, cpu_T3); + tcg_gen_mov_tl(cpu_cc_src, cpu_cc_tmp); tcg_gen_discard_tl(cpu_cc_dst); tcg_gen_movi_i32(cpu_cc_op, CC_OP_EFLAGS); @@ -1551,6 +1781,12 @@ static void gen_shiftd_rm_T1_T3(DisasContext *s, int ot, int op1, { int label1, label2, data_bits; target_ulong mask; + TCGv t0, t1, t2, a0; + + t0 = tcg_temp_local_new(); + t1 = tcg_temp_local_new(); + t2 = tcg_temp_local_new(); + a0 = tcg_temp_local_new(); if (ot == OT_QUAD) mask = 0x3f; @@ -1558,95 +1794,102 @@ static void gen_shiftd_rm_T1_T3(DisasContext *s, int ot, int op1, mask = 0x1f; /* load */ - if (op1 == OR_TMP0) - gen_op_ld_T0_A0(ot + s->mem_index); - else - gen_op_mov_TN_reg(ot, 0, op1); + if (op1 == OR_TMP0) { + tcg_gen_mov_tl(a0, cpu_A0); + gen_op_ld_v(ot + s->mem_index, t0, a0); + } else { + gen_op_mov_v_reg(ot, t0, op1); + } tcg_gen_andi_tl(cpu_T3, cpu_T3, mask); + + tcg_gen_mov_tl(t1, cpu_T[1]); + tcg_gen_mov_tl(t2, cpu_T3); + /* Must test zero case to avoid using undefined behaviour in TCG shifts. */ label1 = gen_new_label(); - tcg_gen_brcond_tl(TCG_COND_EQ, cpu_T3, tcg_const_tl(0), label1); + tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, label1); - tcg_gen_addi_tl(cpu_tmp5, cpu_T3, -1); + tcg_gen_addi_tl(cpu_tmp5, t2, -1); if (ot == OT_WORD) { /* Note: we implement the Intel behaviour for shift count > 16 */ if (is_right) { - tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff); - tcg_gen_shli_tl(cpu_tmp0, cpu_T[1], 16); - tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_tmp0); - tcg_gen_ext32u_tl(cpu_T[0], cpu_T[0]); + tcg_gen_andi_tl(t0, t0, 0xffff); + tcg_gen_shli_tl(cpu_tmp0, t1, 16); + tcg_gen_or_tl(t0, t0, cpu_tmp0); + tcg_gen_ext32u_tl(t0, t0); - tcg_gen_shr_tl(cpu_tmp4, cpu_T[0], cpu_tmp5); + tcg_gen_shr_tl(cpu_tmp4, t0, cpu_tmp5); /* only needed if count > 16, but a test would complicate */ - tcg_gen_sub_tl(cpu_tmp5, tcg_const_tl(32), cpu_T3); - tcg_gen_shl_tl(cpu_tmp0, cpu_T[0], cpu_tmp5); + tcg_gen_sub_tl(cpu_tmp5, tcg_const_tl(32), t2); + tcg_gen_shl_tl(cpu_tmp0, t0, cpu_tmp5); - tcg_gen_shr_tl(cpu_T[0], cpu_T[0], cpu_T3); + tcg_gen_shr_tl(t0, t0, t2); - tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_tmp0); + tcg_gen_or_tl(t0, t0, cpu_tmp0); } else { /* XXX: not optimal */ - tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff); - tcg_gen_shli_tl(cpu_T[1], cpu_T[1], 16); - tcg_gen_or_tl(cpu_T[1], cpu_T[1], cpu_T[0]); - tcg_gen_ext32u_tl(cpu_T[1], cpu_T[1]); + tcg_gen_andi_tl(t0, t0, 0xffff); + tcg_gen_shli_tl(t1, t1, 16); + tcg_gen_or_tl(t1, t1, t0); + tcg_gen_ext32u_tl(t1, t1); - tcg_gen_shl_tl(cpu_tmp4, cpu_T[0], cpu_tmp5); + tcg_gen_shl_tl(cpu_tmp4, t0, cpu_tmp5); tcg_gen_sub_tl(cpu_tmp0, tcg_const_tl(32), cpu_tmp5); - tcg_gen_shr_tl(cpu_tmp6, cpu_T[1], cpu_tmp0); + tcg_gen_shr_tl(cpu_tmp6, t1, cpu_tmp0); tcg_gen_or_tl(cpu_tmp4, cpu_tmp4, cpu_tmp6); - tcg_gen_shl_tl(cpu_T[0], cpu_T[0], cpu_T3); - tcg_gen_sub_tl(cpu_tmp5, tcg_const_tl(32), cpu_T3); - tcg_gen_shr_tl(cpu_T[1], cpu_T[1], cpu_tmp5); - tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]); + tcg_gen_shl_tl(t0, t0, t2); + tcg_gen_sub_tl(cpu_tmp5, tcg_const_tl(32), t2); + tcg_gen_shr_tl(t1, t1, cpu_tmp5); + tcg_gen_or_tl(t0, t0, t1); } } else { data_bits = 8 << ot; if (is_right) { if (ot == OT_LONG) - tcg_gen_ext32u_tl(cpu_T[0], cpu_T[0]); + tcg_gen_ext32u_tl(t0, t0); - tcg_gen_shr_tl(cpu_tmp4, cpu_T[0], cpu_tmp5); + tcg_gen_shr_tl(cpu_tmp4, t0, cpu_tmp5); - tcg_gen_shr_tl(cpu_T[0], cpu_T[0], cpu_T3); - tcg_gen_sub_tl(cpu_tmp5, tcg_const_tl(data_bits), cpu_T3); - tcg_gen_shl_tl(cpu_T[1], cpu_T[1], cpu_tmp5); - tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]); + tcg_gen_shr_tl(t0, t0, t2); + tcg_gen_sub_tl(cpu_tmp5, tcg_const_tl(data_bits), t2); + tcg_gen_shl_tl(t1, t1, cpu_tmp5); + tcg_gen_or_tl(t0, t0, t1); } else { if (ot == OT_LONG) - tcg_gen_ext32u_tl(cpu_T[1], cpu_T[1]); + tcg_gen_ext32u_tl(t1, t1); - tcg_gen_shl_tl(cpu_tmp4, cpu_T[0], cpu_tmp5); + tcg_gen_shl_tl(cpu_tmp4, t0, cpu_tmp5); - tcg_gen_shl_tl(cpu_T[0], cpu_T[0], cpu_T3); - tcg_gen_sub_tl(cpu_tmp5, tcg_const_tl(data_bits), cpu_T3); - tcg_gen_shr_tl(cpu_T[1], cpu_T[1], cpu_tmp5); - tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]); + tcg_gen_shl_tl(t0, t0, t2); + tcg_gen_sub_tl(cpu_tmp5, tcg_const_tl(data_bits), t2); + tcg_gen_shr_tl(t1, t1, cpu_tmp5); + tcg_gen_or_tl(t0, t0, t1); } } - tcg_gen_mov_tl(cpu_T[1], cpu_tmp4); + tcg_gen_mov_tl(t1, cpu_tmp4); gen_set_label(label1); /* store */ - if (op1 == OR_TMP0) - gen_op_st_T0_A0(ot + s->mem_index); - else - gen_op_mov_reg_T0(ot, op1); + if (op1 == OR_TMP0) { + gen_op_st_v(ot + s->mem_index, t0, a0); + } else { + gen_op_mov_reg_v(ot, op1, t0); + } /* update eflags */ if (s->cc_op != CC_OP_DYNAMIC) gen_op_set_cc_op(s->cc_op); label2 = gen_new_label(); - tcg_gen_brcond_tl(TCG_COND_EQ, cpu_T3, tcg_const_tl(0), label2); + tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, label2); - tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]); - tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); + tcg_gen_mov_tl(cpu_cc_src, t1); + tcg_gen_mov_tl(cpu_cc_dst, t0); if (is_right) { tcg_gen_movi_i32(cpu_cc_op, CC_OP_SARB + ot); } else { @@ -1654,6 +1897,11 @@ static void gen_shiftd_rm_T1_T3(DisasContext *s, int ot, int op1, } gen_set_label(label2); s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */ + + tcg_temp_free(t0); + tcg_temp_free(t1); + tcg_temp_free(t2); + tcg_temp_free(a0); } static void gen_shift(DisasContext *s1, int op, int ot, int d, int s) @@ -1688,9 +1936,29 @@ static void gen_shift(DisasContext *s1, int op, int ot, int d, int s) static void gen_shifti(DisasContext *s1, int op, int ot, int d, int c) { - /* currently not optimized */ - gen_op_movl_T1_im(c); - gen_shift(s1, op, ot, d, OR_TMP1); + switch(op) { + case OP_ROL: + gen_rot_rm_im(s1, ot, d, c, 0); + break; + case OP_ROR: + gen_rot_rm_im(s1, ot, d, c, 1); + break; + case OP_SHL: + case OP_SHL1: + gen_shift_rm_im(s1, ot, d, c, 0, 0); + break; + case OP_SHR: + gen_shift_rm_im(s1, ot, d, c, 1, 0); + break; + case OP_SAR: + gen_shift_rm_im(s1, ot, d, c, 1, 1); + break; + default: + /* currently not optimized */ + gen_op_movl_T1_im(c); + gen_shift(s1, op, ot, d, OR_TMP1); + break; + } } static void gen_lea_modrm(DisasContext *s, int modrm, int *reg_ptr, int *offset_ptr) @@ -1951,7 +2219,7 @@ static void gen_add_A0_ds_seg(DisasContext *s) } } -/* generate modrm memory load or store of 'reg'. TMP0 is used if reg != +/* generate modrm memory load or store of 'reg'. TMP0 is used if reg == OR_TMP0 */ static void gen_ldst_modrm(DisasContext *s, int modrm, int ot, int reg, int is_store) { @@ -2025,137 +2293,43 @@ static inline void gen_goto_tb(DisasContext *s, int tb_num, target_ulong eip) (pc & TARGET_PAGE_MASK) == ((s->pc - 1) & TARGET_PAGE_MASK)) { /* jump to same page: we can use a direct jump */ tcg_gen_goto_tb(tb_num); - gen_jmp_im(eip); - tcg_gen_exit_tb((long)tb + tb_num); - } else { - /* jump to another page: currently not optimized */ - gen_jmp_im(eip); - gen_eob(s); - } -} - -static inline void gen_jcc(DisasContext *s, int b, - target_ulong val, target_ulong next_eip) -{ - TranslationBlock *tb; - int inv, jcc_op; - GenOpFunc1 *func; - target_ulong tmp; - int l1, l2; - - inv = b & 1; - jcc_op = (b >> 1) & 7; - - if (s->jmp_opt) { - switch(s->cc_op) { - /* we optimize the cmp/jcc case */ - case CC_OP_SUBB: - case CC_OP_SUBW: - case CC_OP_SUBL: - case CC_OP_SUBQ: - func = gen_jcc_sub[s->cc_op - CC_OP_SUBB][jcc_op]; - break; - - /* some jumps are easy to compute */ - case CC_OP_ADDB: - case CC_OP_ADDW: - case CC_OP_ADDL: - case CC_OP_ADDQ: - - case CC_OP_ADCB: - case CC_OP_ADCW: - case CC_OP_ADCL: - case CC_OP_ADCQ: - - case CC_OP_SBBB: - case CC_OP_SBBW: - case CC_OP_SBBL: - case CC_OP_SBBQ: - - case CC_OP_LOGICB: - case CC_OP_LOGICW: - case CC_OP_LOGICL: - case CC_OP_LOGICQ: - - case CC_OP_INCB: - case CC_OP_INCW: - case CC_OP_INCL: - case CC_OP_INCQ: - - case CC_OP_DECB: - case CC_OP_DECW: - case CC_OP_DECL: - case CC_OP_DECQ: - - case CC_OP_SHLB: - case CC_OP_SHLW: - case CC_OP_SHLL: - case CC_OP_SHLQ: - - case CC_OP_SARB: - case CC_OP_SARW: - case CC_OP_SARL: - case CC_OP_SARQ: - switch(jcc_op) { - case JCC_Z: - func = gen_jcc_sub[(s->cc_op - CC_OP_ADDB) % 4][jcc_op]; - break; - case JCC_S: - func = gen_jcc_sub[(s->cc_op - CC_OP_ADDB) % 4][jcc_op]; - break; - default: - func = NULL; - break; - } - break; - default: - func = NULL; - break; - } - - if (s->cc_op != CC_OP_DYNAMIC) { - gen_op_set_cc_op(s->cc_op); - s->cc_op = CC_OP_DYNAMIC; - } - - if (!func) { - gen_setcc_slow[jcc_op](); - func = gen_op_jnz_T0_label; - } + gen_jmp_im(eip); + tcg_gen_exit_tb((long)tb + tb_num); + } else { + /* jump to another page: currently not optimized */ + gen_jmp_im(eip); + gen_eob(s); + } +} - if (inv) { - tmp = val; - val = next_eip; - next_eip = tmp; - } - tb = s->tb; +static inline void gen_jcc(DisasContext *s, int b, + target_ulong val, target_ulong next_eip) +{ + int l1, l2, cc_op; + cc_op = s->cc_op; + if (s->cc_op != CC_OP_DYNAMIC) { + gen_op_set_cc_op(s->cc_op); + s->cc_op = CC_OP_DYNAMIC; + } + if (s->jmp_opt) { l1 = gen_new_label(); - func(l1); - + gen_jcc1(s, cc_op, b, l1); + gen_goto_tb(s, 0, next_eip); gen_set_label(l1); gen_goto_tb(s, 1, val); - s->is_jmp = 3; } else { - if (s->cc_op != CC_OP_DYNAMIC) { - gen_op_set_cc_op(s->cc_op); - s->cc_op = CC_OP_DYNAMIC; - } - gen_setcc_slow[jcc_op](); - if (inv) { - tmp = val; - val = next_eip; - next_eip = tmp; - } l1 = gen_new_label(); l2 = gen_new_label(); - gen_op_jnz_T0_label(l1); + gen_jcc1(s, cc_op, b, l1); + gen_jmp_im(next_eip); - gen_op_jmp_label(l2); + tcg_gen_br(l2); + gen_set_label(l1); gen_jmp_im(val); gen_set_label(l2); @@ -2165,71 +2339,49 @@ static inline void gen_jcc(DisasContext *s, int b, static void gen_setcc(DisasContext *s, int b) { - int inv, jcc_op; - GenOpFunc *func; - - inv = b & 1; - jcc_op = (b >> 1) & 7; - switch(s->cc_op) { - /* we optimize the cmp/jcc case */ - case CC_OP_SUBB: - case CC_OP_SUBW: - case CC_OP_SUBL: - case CC_OP_SUBQ: - func = gen_setcc_sub[s->cc_op - CC_OP_SUBB][jcc_op]; - if (!func) - goto slow_jcc; - break; - - /* some jumps are easy to compute */ - case CC_OP_ADDB: - case CC_OP_ADDW: - case CC_OP_ADDL: - case CC_OP_ADDQ: - - case CC_OP_LOGICB: - case CC_OP_LOGICW: - case CC_OP_LOGICL: - case CC_OP_LOGICQ: - - case CC_OP_INCB: - case CC_OP_INCW: - case CC_OP_INCL: - case CC_OP_INCQ: - - case CC_OP_DECB: - case CC_OP_DECW: - case CC_OP_DECL: - case CC_OP_DECQ: - - case CC_OP_SHLB: - case CC_OP_SHLW: - case CC_OP_SHLL: - case CC_OP_SHLQ: - switch(jcc_op) { - case JCC_Z: - func = gen_setcc_sub[(s->cc_op - CC_OP_ADDB) % 4][jcc_op]; - break; - case JCC_S: - func = gen_setcc_sub[(s->cc_op - CC_OP_ADDB) % 4][jcc_op]; - break; - default: - goto slow_jcc; + int inv, jcc_op, l1; + TCGv t0; + + if (is_fast_jcc_case(s, b)) { + /* nominal case: we use a jump */ + /* XXX: make it faster by adding new instructions in TCG */ + t0 = tcg_temp_local_new(); + tcg_gen_movi_tl(t0, 0); + l1 = gen_new_label(); + gen_jcc1(s, s->cc_op, b ^ 1, l1); + tcg_gen_movi_tl(t0, 1); + gen_set_label(l1); + tcg_gen_mov_tl(cpu_T[0], t0); + tcg_temp_free(t0); + } else { + /* slow case: it is more efficient not to generate a jump, + although it is questionnable whether this optimization is + worth to */ + inv = b & 1; + jcc_op = (b >> 1) & 7; + gen_setcc_slow_T0(s, jcc_op); + if (inv) { + tcg_gen_xori_tl(cpu_T[0], cpu_T[0], 1); } - break; - default: - slow_jcc: - if (s->cc_op != CC_OP_DYNAMIC) - gen_op_set_cc_op(s->cc_op); - func = gen_setcc_slow[jcc_op]; - break; - } - func(); - if (inv) { - gen_op_xor_T0_1(); } } +static inline void gen_op_movl_T0_seg(int seg_reg) +{ + tcg_gen_ld32u_tl(cpu_T[0], cpu_env, + offsetof(CPUX86State,segs[seg_reg].selector)); +} + +static inline void gen_op_movl_seg_T0_vm(int seg_reg) +{ + tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff); + tcg_gen_st32_tl(cpu_T[0], cpu_env, + offsetof(CPUX86State,segs[seg_reg].selector)); + tcg_gen_shli_tl(cpu_T[0], cpu_T[0], 4); + tcg_gen_st_tl(cpu_T[0], cpu_env, + offsetof(CPUX86State,segs[seg_reg].base)); +} + /* move T0 to seg_reg and compute if the CPU state may change. Never call this function with seg_reg == R_CS */ static void gen_movl_seg_T0(DisasContext *s, int seg_reg, target_ulong cur_eip) @@ -2240,7 +2392,7 @@ static void gen_movl_seg_T0(DisasContext *s, int seg_reg, target_ulong cur_eip) gen_op_set_cc_op(s->cc_op); gen_jmp_im(cur_eip); tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); - tcg_gen_helper_0_2(helper_load_seg, tcg_const_i32(seg_reg), cpu_tmp2_i32); + gen_helper_load_seg(tcg_const_i32(seg_reg), cpu_tmp2_i32); /* abort translation because the addseg value may change or because ss32 may change. For R_SS, translation must always stop as a special handling must be done to disable hardware @@ -2248,7 +2400,7 @@ static void gen_movl_seg_T0(DisasContext *s, int seg_reg, target_ulong cur_eip) if (seg_reg == R_SS || (s->code32 && seg_reg < R_FS)) s->is_jmp = 3; } else { - gen_op_movl_seg_T0_vm(offsetof(CPUX86State,segs[seg_reg])); + gen_op_movl_seg_T0_vm(seg_reg); if (seg_reg == R_SS) s->is_jmp = 3; } @@ -2259,72 +2411,37 @@ static inline int svm_is_rep(int prefixes) return ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) ? 8 : 0); } -static inline int +static inline void gen_svm_check_intercept_param(DisasContext *s, target_ulong pc_start, uint32_t type, uint64_t param) { - if(!(s->flags & (INTERCEPT_SVM_MASK))) - /* no SVM activated */ - return 0; - switch(type) { - /* CRx and DRx reads/writes */ - case SVM_EXIT_READ_CR0 ... SVM_EXIT_EXCP_BASE - 1: - if (s->cc_op != CC_OP_DYNAMIC) { - gen_op_set_cc_op(s->cc_op); - } - gen_jmp_im(pc_start - s->cs_base); - tcg_gen_helper_0_2(helper_svm_check_intercept_param, - tcg_const_i32(type), tcg_const_i64(param)); - /* this is a special case as we do not know if the interception occurs - so we assume there was none */ - return 0; - case SVM_EXIT_MSR: - if(s->flags & (1ULL << INTERCEPT_MSR_PROT)) { - if (s->cc_op != CC_OP_DYNAMIC) { - gen_op_set_cc_op(s->cc_op); - } - gen_jmp_im(pc_start - s->cs_base); - tcg_gen_helper_0_2(helper_svm_check_intercept_param, - tcg_const_i32(type), tcg_const_i64(param)); - /* this is a special case as we do not know if the interception occurs - so we assume there was none */ - return 0; - } - break; - default: - if(s->flags & (1ULL << ((type - SVM_EXIT_INTR) + INTERCEPT_INTR))) { - if (s->cc_op != CC_OP_DYNAMIC) { - gen_op_set_cc_op(s->cc_op); - } - gen_jmp_im(pc_start - s->cs_base); - tcg_gen_helper_0_2(helper_vmexit, - tcg_const_i32(type), tcg_const_i64(param)); - /* we can optimize this one so TBs don't get longer - than up to vmexit */ - gen_eob(s); - return 1; - } - } - return 0; + /* no SVM activated; fast case */ + if (likely(!(s->flags & HF_SVMI_MASK))) + return; + if (s->cc_op != CC_OP_DYNAMIC) + gen_op_set_cc_op(s->cc_op); + gen_jmp_im(pc_start - s->cs_base); + gen_helper_svm_check_intercept_param(tcg_const_i32(type), + tcg_const_i64(param)); } -static inline int +static inline void gen_svm_check_intercept(DisasContext *s, target_ulong pc_start, uint64_t type) { - return gen_svm_check_intercept_param(s, pc_start, type, 0); + gen_svm_check_intercept_param(s, pc_start, type, 0); } static inline void gen_stack_update(DisasContext *s, int addend) { #ifdef TARGET_X86_64 if (CODE64(s)) { - gen_op_addq_ESP_im(addend); + gen_op_add_reg_im(2, R_ESP, addend); } else #endif if (s->ss32) { - gen_op_addl_ESP_im(addend); + gen_op_add_reg_im(1, R_ESP, addend); } else { - gen_op_addw_ESP_im(addend); + gen_op_add_reg_im(0, R_ESP, addend); } } @@ -2512,10 +2629,9 @@ static void gen_enter(DisasContext *s, int esp_addend, int level) gen_op_st_T0_A0(ot + s->mem_index); if (level) { /* XXX: must save state */ - tcg_gen_helper_0_3(helper_enter64_level, - tcg_const_i32(level), - tcg_const_i32((ot == OT_QUAD)), - cpu_T[1]); + gen_helper_enter64_level(tcg_const_i32(level), + tcg_const_i32((ot == OT_QUAD)), + cpu_T[1]); } gen_op_mov_reg_T1(ot, R_EBP); tcg_gen_addi_tl(cpu_T[1], cpu_T[1], -esp_addend + (-opsize * level)); @@ -2538,10 +2654,9 @@ static void gen_enter(DisasContext *s, int esp_addend, int level) gen_op_st_T0_A0(ot + s->mem_index); if (level) { /* XXX: must save state */ - tcg_gen_helper_0_3(helper_enter_level, - tcg_const_i32(level), - tcg_const_i32(s->dflag), - cpu_T[1]); + gen_helper_enter_level(tcg_const_i32(level), + tcg_const_i32(s->dflag), + cpu_T[1]); } gen_op_mov_reg_T1(ot, R_EBP); tcg_gen_addi_tl(cpu_T[1], cpu_T[1], -esp_addend + (-opsize * level)); @@ -2554,7 +2669,7 @@ static void gen_exception(DisasContext *s, int trapno, target_ulong cur_eip) if (s->cc_op != CC_OP_DYNAMIC) gen_op_set_cc_op(s->cc_op); gen_jmp_im(cur_eip); - tcg_gen_helper_0_1(helper_raise_exception, tcg_const_i32(trapno)); + gen_helper_raise_exception(tcg_const_i32(trapno)); s->is_jmp = 3; } @@ -2566,9 +2681,8 @@ static void gen_interrupt(DisasContext *s, int intno, if (s->cc_op != CC_OP_DYNAMIC) gen_op_set_cc_op(s->cc_op); gen_jmp_im(cur_eip); - tcg_gen_helper_0_2(helper_raise_interrupt, - tcg_const_i32(intno), - tcg_const_i32(next_eip - cur_eip)); + gen_helper_raise_interrupt(tcg_const_i32(intno), + tcg_const_i32(next_eip - cur_eip)); s->is_jmp = 3; } @@ -2577,7 +2691,7 @@ static void gen_debug(DisasContext *s, target_ulong cur_eip) if (s->cc_op != CC_OP_DYNAMIC) gen_op_set_cc_op(s->cc_op); gen_jmp_im(cur_eip); - tcg_gen_helper_0_0(helper_debug); + gen_helper_debug(); s->is_jmp = 3; } @@ -2588,12 +2702,15 @@ static void gen_eob(DisasContext *s) if (s->cc_op != CC_OP_DYNAMIC) gen_op_set_cc_op(s->cc_op); if (s->tb->flags & HF_INHIBIT_IRQ_MASK) { - tcg_gen_helper_0_0(helper_reset_inhibit_irq); + gen_helper_reset_inhibit_irq(); + } + if (s->tb->flags & HF_RF_MASK) { + gen_helper_reset_rf(); } if (s->singlestep_enabled) { - tcg_gen_helper_0_0(helper_debug); + gen_helper_debug(); } else if (s->tf) { - tcg_gen_helper_0_0(helper_single_step); + gen_helper_single_step(); } else { tcg_gen_exit_tb(0); } @@ -2685,9 +2802,9 @@ static inline void gen_op_movq_env_0(int d_offset) #define SSE_SPECIAL ((void *)1) #define SSE_DUMMY ((void *)2) -#define MMX_OP2(x) { helper_ ## x ## _mmx, helper_ ## x ## _xmm } -#define SSE_FOP(x) { helper_ ## x ## ps, helper_ ## x ## pd, \ - helper_ ## x ## ss, helper_ ## x ## sd, } +#define MMX_OP2(x) { gen_helper_ ## x ## _mmx, gen_helper_ ## x ## _xmm } +#define SSE_FOP(x) { gen_helper_ ## x ## ps, gen_helper_ ## x ## pd, \ + gen_helper_ ## x ## ss, gen_helper_ ## x ## sd, } static void *sse_op_table1[256][4] = { /* 3DNow! extensions */ @@ -2698,8 +2815,8 @@ static void *sse_op_table1[256][4] = { [0x11] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movups, movupd, movss, movsd */ [0x12] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movlps, movlpd, movsldup, movddup */ [0x13] = { SSE_SPECIAL, SSE_SPECIAL }, /* movlps, movlpd */ - [0x14] = { helper_punpckldq_xmm, helper_punpcklqdq_xmm }, - [0x15] = { helper_punpckhdq_xmm, helper_punpckhqdq_xmm }, + [0x14] = { gen_helper_punpckldq_xmm, gen_helper_punpcklqdq_xmm }, + [0x15] = { gen_helper_punpckhdq_xmm, gen_helper_punpckhqdq_xmm }, [0x16] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movhps, movhpd, movshdup */ [0x17] = { SSE_SPECIAL, SSE_SPECIAL }, /* movhps, movhpd */ @@ -2709,28 +2826,31 @@ static void *sse_op_table1[256][4] = { [0x2b] = { SSE_SPECIAL, SSE_SPECIAL }, /* movntps, movntpd */ [0x2c] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* cvttps2pi, cvttpd2pi, cvttsd2si, cvttss2si */ [0x2d] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* cvtps2pi, cvtpd2pi, cvtsd2si, cvtss2si */ - [0x2e] = { helper_ucomiss, helper_ucomisd }, - [0x2f] = { helper_comiss, helper_comisd }, + [0x2e] = { gen_helper_ucomiss, gen_helper_ucomisd }, + [0x2f] = { gen_helper_comiss, gen_helper_comisd }, [0x50] = { SSE_SPECIAL, SSE_SPECIAL }, /* movmskps, movmskpd */ [0x51] = SSE_FOP(sqrt), - [0x52] = { helper_rsqrtps, NULL, helper_rsqrtss, NULL }, - [0x53] = { helper_rcpps, NULL, helper_rcpss, NULL }, - [0x54] = { helper_pand_xmm, helper_pand_xmm }, /* andps, andpd */ - [0x55] = { helper_pandn_xmm, helper_pandn_xmm }, /* andnps, andnpd */ - [0x56] = { helper_por_xmm, helper_por_xmm }, /* orps, orpd */ - [0x57] = { helper_pxor_xmm, helper_pxor_xmm }, /* xorps, xorpd */ + [0x52] = { gen_helper_rsqrtps, NULL, gen_helper_rsqrtss, NULL }, + [0x53] = { gen_helper_rcpps, NULL, gen_helper_rcpss, NULL }, + [0x54] = { gen_helper_pand_xmm, gen_helper_pand_xmm }, /* andps, andpd */ + [0x55] = { gen_helper_pandn_xmm, gen_helper_pandn_xmm }, /* andnps, andnpd */ + [0x56] = { gen_helper_por_xmm, gen_helper_por_xmm }, /* orps, orpd */ + [0x57] = { gen_helper_pxor_xmm, gen_helper_pxor_xmm }, /* xorps, xorpd */ [0x58] = SSE_FOP(add), [0x59] = SSE_FOP(mul), - [0x5a] = { helper_cvtps2pd, helper_cvtpd2ps, - helper_cvtss2sd, helper_cvtsd2ss }, - [0x5b] = { helper_cvtdq2ps, helper_cvtps2dq, helper_cvttps2dq }, + [0x5a] = { gen_helper_cvtps2pd, gen_helper_cvtpd2ps, + gen_helper_cvtss2sd, gen_helper_cvtsd2ss }, + [0x5b] = { gen_helper_cvtdq2ps, gen_helper_cvtps2dq, gen_helper_cvttps2dq }, [0x5c] = SSE_FOP(sub), [0x5d] = SSE_FOP(min), [0x5e] = SSE_FOP(div), [0x5f] = SSE_FOP(max), [0xc2] = SSE_FOP(cmpeq), - [0xc6] = { helper_shufps, helper_shufpd }, + [0xc6] = { gen_helper_shufps, gen_helper_shufpd }, + + [0x38] = { SSE_SPECIAL, SSE_SPECIAL, NULL, SSE_SPECIAL }, /* SSSE3/SSE4 */ + [0x3a] = { SSE_SPECIAL, SSE_SPECIAL }, /* SSSE3/SSE4 */ /* MMX ops and their SSE extensions */ [0x60] = MMX_OP2(punpcklbw), @@ -2745,14 +2865,14 @@ static void *sse_op_table1[256][4] = { [0x69] = MMX_OP2(punpckhwd), [0x6a] = MMX_OP2(punpckhdq), [0x6b] = MMX_OP2(packssdw), - [0x6c] = { NULL, helper_punpcklqdq_xmm }, - [0x6d] = { NULL, helper_punpckhqdq_xmm }, + [0x6c] = { NULL, gen_helper_punpcklqdq_xmm }, + [0x6d] = { NULL, gen_helper_punpckhqdq_xmm }, [0x6e] = { SSE_SPECIAL, SSE_SPECIAL }, /* movd mm, ea */ [0x6f] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movq, movdqa, , movqdu */ - [0x70] = { helper_pshufw_mmx, - helper_pshufd_xmm, - helper_pshufhw_xmm, - helper_pshuflw_xmm }, + [0x70] = { gen_helper_pshufw_mmx, + gen_helper_pshufd_xmm, + gen_helper_pshufhw_xmm, + gen_helper_pshuflw_xmm }, [0x71] = { SSE_SPECIAL, SSE_SPECIAL }, /* shiftw */ [0x72] = { SSE_SPECIAL, SSE_SPECIAL }, /* shiftd */ [0x73] = { SSE_SPECIAL, SSE_SPECIAL }, /* shiftq */ @@ -2760,13 +2880,13 @@ static void *sse_op_table1[256][4] = { [0x75] = MMX_OP2(pcmpeqw), [0x76] = MMX_OP2(pcmpeql), [0x77] = { SSE_DUMMY }, /* emms */ - [0x7c] = { NULL, helper_haddpd, NULL, helper_haddps }, - [0x7d] = { NULL, helper_hsubpd, NULL, helper_hsubps }, + [0x7c] = { NULL, gen_helper_haddpd, NULL, gen_helper_haddps }, + [0x7d] = { NULL, gen_helper_hsubpd, NULL, gen_helper_hsubps }, [0x7e] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movd, movd, , movq */ [0x7f] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movq, movdqa, movdqu */ [0xc4] = { SSE_SPECIAL, SSE_SPECIAL }, /* pinsrw */ [0xc5] = { SSE_SPECIAL, SSE_SPECIAL }, /* pextrw */ - [0xd0] = { NULL, helper_addsubpd, NULL, helper_addsubps }, + [0xd0] = { NULL, gen_helper_addsubpd, NULL, gen_helper_addsubps }, [0xd1] = MMX_OP2(psrlw), [0xd2] = MMX_OP2(psrld), [0xd3] = MMX_OP2(psrlq), @@ -2788,7 +2908,7 @@ static void *sse_op_table1[256][4] = { [0xe3] = MMX_OP2(pavgw), [0xe4] = MMX_OP2(pmulhuw), [0xe5] = MMX_OP2(pmulhw), - [0xe6] = { NULL, helper_cvttpd2dq, helper_cvtdq2pd, helper_cvtpd2dq }, + [0xe6] = { NULL, gen_helper_cvttpd2dq, gen_helper_cvtdq2pd, gen_helper_cvtpd2dq }, [0xe7] = { SSE_SPECIAL , SSE_SPECIAL }, /* movntq, movntq */ [0xe8] = MMX_OP2(psubsb), [0xe9] = MMX_OP2(psubsw), @@ -2823,26 +2943,26 @@ static void *sse_op_table2[3 * 8][2] = { [8 + 4] = MMX_OP2(psrad), [8 + 6] = MMX_OP2(pslld), [16 + 2] = MMX_OP2(psrlq), - [16 + 3] = { NULL, helper_psrldq_xmm }, + [16 + 3] = { NULL, gen_helper_psrldq_xmm }, [16 + 6] = MMX_OP2(psllq), - [16 + 7] = { NULL, helper_pslldq_xmm }, + [16 + 7] = { NULL, gen_helper_pslldq_xmm }, }; static void *sse_op_table3[4 * 3] = { - helper_cvtsi2ss, - helper_cvtsi2sd, - X86_64_ONLY(helper_cvtsq2ss), - X86_64_ONLY(helper_cvtsq2sd), - - helper_cvttss2si, - helper_cvttsd2si, - X86_64_ONLY(helper_cvttss2sq), - X86_64_ONLY(helper_cvttsd2sq), - - helper_cvtss2si, - helper_cvtsd2si, - X86_64_ONLY(helper_cvtss2sq), - X86_64_ONLY(helper_cvtsd2sq), + gen_helper_cvtsi2ss, + gen_helper_cvtsi2sd, + X86_64_ONLY(gen_helper_cvtsq2ss), + X86_64_ONLY(gen_helper_cvtsq2sd), + + gen_helper_cvttss2si, + gen_helper_cvttsd2si, + X86_64_ONLY(gen_helper_cvttss2sq), + X86_64_ONLY(gen_helper_cvttsd2sq), + + gen_helper_cvtss2si, + gen_helper_cvtsd2si, + X86_64_ONLY(gen_helper_cvtss2sq), + X86_64_ONLY(gen_helper_cvtsd2sq), }; static void *sse_op_table4[8][4] = { @@ -2857,30 +2977,111 @@ static void *sse_op_table4[8][4] = { }; static void *sse_op_table5[256] = { - [0x0c] = helper_pi2fw, - [0x0d] = helper_pi2fd, - [0x1c] = helper_pf2iw, - [0x1d] = helper_pf2id, - [0x8a] = helper_pfnacc, - [0x8e] = helper_pfpnacc, - [0x90] = helper_pfcmpge, - [0x94] = helper_pfmin, - [0x96] = helper_pfrcp, - [0x97] = helper_pfrsqrt, - [0x9a] = helper_pfsub, - [0x9e] = helper_pfadd, - [0xa0] = helper_pfcmpgt, - [0xa4] = helper_pfmax, - [0xa6] = helper_movq, /* pfrcpit1; no need to actually increase precision */ - [0xa7] = helper_movq, /* pfrsqit1 */ - [0xaa] = helper_pfsubr, - [0xae] = helper_pfacc, - [0xb0] = helper_pfcmpeq, - [0xb4] = helper_pfmul, - [0xb6] = helper_movq, /* pfrcpit2 */ - [0xb7] = helper_pmulhrw_mmx, - [0xbb] = helper_pswapd, - [0xbf] = helper_pavgb_mmx /* pavgusb */ + [0x0c] = gen_helper_pi2fw, + [0x0d] = gen_helper_pi2fd, + [0x1c] = gen_helper_pf2iw, + [0x1d] = gen_helper_pf2id, + [0x8a] = gen_helper_pfnacc, + [0x8e] = gen_helper_pfpnacc, + [0x90] = gen_helper_pfcmpge, + [0x94] = gen_helper_pfmin, + [0x96] = gen_helper_pfrcp, + [0x97] = gen_helper_pfrsqrt, + [0x9a] = gen_helper_pfsub, + [0x9e] = gen_helper_pfadd, + [0xa0] = gen_helper_pfcmpgt, + [0xa4] = gen_helper_pfmax, + [0xa6] = gen_helper_movq, /* pfrcpit1; no need to actually increase precision */ + [0xa7] = gen_helper_movq, /* pfrsqit1 */ + [0xaa] = gen_helper_pfsubr, + [0xae] = gen_helper_pfacc, + [0xb0] = gen_helper_pfcmpeq, + [0xb4] = gen_helper_pfmul, + [0xb6] = gen_helper_movq, /* pfrcpit2 */ + [0xb7] = gen_helper_pmulhrw_mmx, + [0xbb] = gen_helper_pswapd, + [0xbf] = gen_helper_pavgb_mmx /* pavgusb */ +}; + +struct sse_op_helper_s { + void *op[2]; uint32_t ext_mask; +}; +#define SSSE3_OP(x) { MMX_OP2(x), CPUID_EXT_SSSE3 } +#define SSE41_OP(x) { { NULL, gen_helper_ ## x ## _xmm }, CPUID_EXT_SSE41 } +#define SSE42_OP(x) { { NULL, gen_helper_ ## x ## _xmm }, CPUID_EXT_SSE42 } +#define SSE41_SPECIAL { { NULL, SSE_SPECIAL }, CPUID_EXT_SSE41 } +static struct sse_op_helper_s sse_op_table6[256] = { + [0x00] = SSSE3_OP(pshufb), + [0x01] = SSSE3_OP(phaddw), + [0x02] = SSSE3_OP(phaddd), + [0x03] = SSSE3_OP(phaddsw), + [0x04] = SSSE3_OP(pmaddubsw), + [0x05] = SSSE3_OP(phsubw), + [0x06] = SSSE3_OP(phsubd), + [0x07] = SSSE3_OP(phsubsw), + [0x08] = SSSE3_OP(psignb), + [0x09] = SSSE3_OP(psignw), + [0x0a] = SSSE3_OP(psignd), + [0x0b] = SSSE3_OP(pmulhrsw), + [0x10] = SSE41_OP(pblendvb), + [0x14] = SSE41_OP(blendvps), + [0x15] = SSE41_OP(blendvpd), + [0x17] = SSE41_OP(ptest), + [0x1c] = SSSE3_OP(pabsb), + [0x1d] = SSSE3_OP(pabsw), + [0x1e] = SSSE3_OP(pabsd), + [0x20] = SSE41_OP(pmovsxbw), + [0x21] = SSE41_OP(pmovsxbd), + [0x22] = SSE41_OP(pmovsxbq), + [0x23] = SSE41_OP(pmovsxwd), + [0x24] = SSE41_OP(pmovsxwq), + [0x25] = SSE41_OP(pmovsxdq), + [0x28] = SSE41_OP(pmuldq), + [0x29] = SSE41_OP(pcmpeqq), + [0x2a] = SSE41_SPECIAL, /* movntqda */ + [0x2b] = SSE41_OP(packusdw), + [0x30] = SSE41_OP(pmovzxbw), + [0x31] = SSE41_OP(pmovzxbd), + [0x32] = SSE41_OP(pmovzxbq), + [0x33] = SSE41_OP(pmovzxwd), + [0x34] = SSE41_OP(pmovzxwq), + [0x35] = SSE41_OP(pmovzxdq), + [0x37] = SSE42_OP(pcmpgtq), + [0x38] = SSE41_OP(pminsb), + [0x39] = SSE41_OP(pminsd), + [0x3a] = SSE41_OP(pminuw), + [0x3b] = SSE41_OP(pminud), + [0x3c] = SSE41_OP(pmaxsb), + [0x3d] = SSE41_OP(pmaxsd), + [0x3e] = SSE41_OP(pmaxuw), + [0x3f] = SSE41_OP(pmaxud), + [0x40] = SSE41_OP(pmulld), + [0x41] = SSE41_OP(phminposuw), +}; + +static struct sse_op_helper_s sse_op_table7[256] = { + [0x08] = SSE41_OP(roundps), + [0x09] = SSE41_OP(roundpd), + [0x0a] = SSE41_OP(roundss), + [0x0b] = SSE41_OP(roundsd), + [0x0c] = SSE41_OP(blendps), + [0x0d] = SSE41_OP(blendpd), + [0x0e] = SSE41_OP(pblendw), + [0x0f] = SSSE3_OP(palignr), + [0x14] = SSE41_SPECIAL, /* pextrb */ + [0x15] = SSE41_SPECIAL, /* pextrw */ + [0x16] = SSE41_SPECIAL, /* pextrd/pextrq */ + [0x17] = SSE41_SPECIAL, /* extractps */ + [0x20] = SSE41_SPECIAL, /* pinsrb */ + [0x21] = SSE41_SPECIAL, /* insertps */ + [0x22] = SSE41_SPECIAL, /* pinsrd/pinsrq */ + [0x40] = SSE41_OP(dpps), + [0x41] = SSE41_OP(dppd), + [0x42] = SSE41_OP(mpsadbw), + [0x60] = SSE42_OP(pcmpestrm), + [0x61] = SSE42_OP(pcmpestri), + [0x62] = SSE42_OP(pcmpistrm), + [0x63] = SSE42_OP(pcmpistri), }; static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r) @@ -2922,23 +3123,24 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r) return; } if (is_xmm && !(s->flags & HF_OSFXSR_MASK)) - goto illegal_op; + if ((b != 0x38 && b != 0x3a) || (s->prefix & PREFIX_DATA)) + goto illegal_op; if (b == 0x0e) { if (!(s->cpuid_ext2_features & CPUID_EXT2_3DNOW)) goto illegal_op; /* femms */ - tcg_gen_helper_0_0(helper_emms); + gen_helper_emms(); return; } if (b == 0x77) { /* emms */ - tcg_gen_helper_0_0(helper_emms); + gen_helper_emms(); return; } /* prepare MMX state (XXX: optimize by storing fptt and fptags in the static cpu state) */ if (!is_xmm) { - tcg_gen_helper_0_0(helper_enter_mmx); + gen_helper_enter_mmx(); } modrm = ldub_code(s->pc++); @@ -2975,7 +3177,8 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r) gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 0); tcg_gen_addi_ptr(cpu_ptr0, cpu_env, offsetof(CPUX86State,fpregs[reg].mmx)); - tcg_gen_helper_0_2(helper_movl_mm_T0_mmx, cpu_ptr0, cpu_T[0]); + tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); + gen_helper_movl_mm_T0_mmx(cpu_ptr0, cpu_tmp2_i32); } break; case 0x16e: /* movd xmm, ea */ @@ -2984,7 +3187,7 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r) gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 0); tcg_gen_addi_ptr(cpu_ptr0, cpu_env, offsetof(CPUX86State,xmm_regs[reg])); - tcg_gen_helper_0_2(helper_movq_mm_T0_xmm, cpu_ptr0, cpu_T[0]); + gen_helper_movq_mm_T0_xmm(cpu_ptr0, cpu_T[0]); } else #endif { @@ -2992,7 +3195,7 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r) tcg_gen_addi_ptr(cpu_ptr0, cpu_env, offsetof(CPUX86State,xmm_regs[reg])); tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); - tcg_gen_helper_0_2(helper_movl_mm_T0_xmm, cpu_ptr0, cpu_tmp2_i32); + gen_helper_movl_mm_T0_xmm(cpu_ptr0, cpu_tmp2_i32); } break; case 0x6f: /* movq mm, ea */ @@ -3026,11 +3229,11 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r) if (mod != 3) { gen_lea_modrm(s, modrm, ®_addr, &offset_addr); gen_op_ld_T0_A0(OT_LONG + s->mem_index); - gen_op_movl_env_T0(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0))); + tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(0))); gen_op_movl_T0_0(); - gen_op_movl_env_T0(offsetof(CPUX86State,xmm_regs[reg].XMM_L(1))); - gen_op_movl_env_T0(offsetof(CPUX86State,xmm_regs[reg].XMM_L(2))); - gen_op_movl_env_T0(offsetof(CPUX86State,xmm_regs[reg].XMM_L(3))); + tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(1))); + tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(2))); + tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(3))); } else { rm = (modrm & 7) | REX_B(s); gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)), @@ -3042,8 +3245,8 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r) gen_lea_modrm(s, modrm, ®_addr, &offset_addr); gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))); gen_op_movl_T0_0(); - gen_op_movl_env_T0(offsetof(CPUX86State,xmm_regs[reg].XMM_L(2))); - gen_op_movl_env_T0(offsetof(CPUX86State,xmm_regs[reg].XMM_L(3))); + tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(2))); + tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(3))); } else { rm = (modrm & 7) | REX_B(s); gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)), @@ -3185,7 +3388,7 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r) case 0x211: /* movss ea, xmm */ if (mod != 3) { gen_lea_modrm(s, modrm, ®_addr, &offset_addr); - gen_op_movl_T0_env(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0))); + tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(0))); gen_op_st_T0_A0(OT_LONG + s->mem_index); } else { rm = (modrm & 7) | REX_B(s); @@ -3230,15 +3433,15 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r) val = ldub_code(s->pc++); if (is_xmm) { gen_op_movl_T0_im(val); - gen_op_movl_env_T0(offsetof(CPUX86State,xmm_t0.XMM_L(0))); + tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0))); gen_op_movl_T0_0(); - gen_op_movl_env_T0(offsetof(CPUX86State,xmm_t0.XMM_L(1))); + tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(1))); op1_offset = offsetof(CPUX86State,xmm_t0); } else { gen_op_movl_T0_im(val); - gen_op_movl_env_T0(offsetof(CPUX86State,mmx_t0.MMX_L(0))); + tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,mmx_t0.MMX_L(0))); gen_op_movl_T0_0(); - gen_op_movl_env_T0(offsetof(CPUX86State,mmx_t0.MMX_L(1))); + tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,mmx_t0.MMX_L(1))); op1_offset = offsetof(CPUX86State,mmx_t0); } sse_op2 = sse_op_table2[((b - 1) & 3) * 8 + (((modrm >> 3)) & 7)][b1]; @@ -3253,13 +3456,13 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r) } tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op2_offset); tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op1_offset); - tcg_gen_helper_0_2(sse_op2, cpu_ptr0, cpu_ptr1); + ((void (*)(TCGv_ptr, TCGv_ptr))sse_op2)(cpu_ptr0, cpu_ptr1); break; case 0x050: /* movmskps */ rm = (modrm & 7) | REX_B(s); tcg_gen_addi_ptr(cpu_ptr0, cpu_env, offsetof(CPUX86State,xmm_regs[rm])); - tcg_gen_helper_1_1(helper_movmskps, cpu_tmp2_i32, cpu_ptr0); + gen_helper_movmskps(cpu_tmp2_i32, cpu_ptr0); tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); gen_op_mov_reg_T0(OT_LONG, reg); break; @@ -3267,13 +3470,13 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r) rm = (modrm & 7) | REX_B(s); tcg_gen_addi_ptr(cpu_ptr0, cpu_env, offsetof(CPUX86State,xmm_regs[rm])); - tcg_gen_helper_1_1(helper_movmskpd, cpu_tmp2_i32, cpu_ptr0); + gen_helper_movmskpd(cpu_tmp2_i32, cpu_ptr0); tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); gen_op_mov_reg_T0(OT_LONG, reg); break; case 0x02a: /* cvtpi2ps */ case 0x12a: /* cvtpi2pd */ - tcg_gen_helper_0_0(helper_enter_mmx); + gen_helper_enter_mmx(); if (mod != 3) { gen_lea_modrm(s, modrm, ®_addr, &offset_addr); op2_offset = offsetof(CPUX86State,mmx_t0); @@ -3287,11 +3490,11 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r) tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset); switch(b >> 8) { case 0x0: - tcg_gen_helper_0_2(helper_cvtpi2ps, cpu_ptr0, cpu_ptr1); + gen_helper_cvtpi2ps(cpu_ptr0, cpu_ptr1); break; default: case 0x1: - tcg_gen_helper_0_2(helper_cvtpi2pd, cpu_ptr0, cpu_ptr1); + gen_helper_cvtpi2pd(cpu_ptr0, cpu_ptr1); break; } break; @@ -3302,14 +3505,18 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r) op1_offset = offsetof(CPUX86State,xmm_regs[reg]); tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); sse_op2 = sse_op_table3[(s->dflag == 2) * 2 + ((b >> 8) - 2)]; - tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); - tcg_gen_helper_0_2(sse_op2, cpu_ptr0, cpu_tmp2_i32); + if (ot == OT_LONG) { + tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); + ((void (*)(TCGv_ptr, TCGv_i32))sse_op2)(cpu_ptr0, cpu_tmp2_i32); + } else { + ((void (*)(TCGv_ptr, TCGv))sse_op2)(cpu_ptr0, cpu_T[0]); + } break; case 0x02c: /* cvttps2pi */ case 0x12c: /* cvttpd2pi */ case 0x02d: /* cvtps2pi */ case 0x12d: /* cvtpd2pi */ - tcg_gen_helper_0_0(helper_enter_mmx); + gen_helper_enter_mmx(); if (mod != 3) { gen_lea_modrm(s, modrm, ®_addr, &offset_addr); op2_offset = offsetof(CPUX86State,xmm_t0); @@ -3323,16 +3530,16 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r) tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset); switch(b) { case 0x02c: - tcg_gen_helper_0_2(helper_cvttps2pi, cpu_ptr0, cpu_ptr1); + gen_helper_cvttps2pi(cpu_ptr0, cpu_ptr1); break; case 0x12c: - tcg_gen_helper_0_2(helper_cvttpd2pi, cpu_ptr0, cpu_ptr1); + gen_helper_cvttpd2pi(cpu_ptr0, cpu_ptr1); break; case 0x02d: - tcg_gen_helper_0_2(helper_cvtps2pi, cpu_ptr0, cpu_ptr1); + gen_helper_cvtps2pi(cpu_ptr0, cpu_ptr1); break; case 0x12d: - tcg_gen_helper_0_2(helper_cvtpd2pi, cpu_ptr0, cpu_ptr1); + gen_helper_cvtpd2pi(cpu_ptr0, cpu_ptr1); break; } break; @@ -3347,7 +3554,7 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r) gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_t0.XMM_Q(0))); } else { gen_op_ld_T0_A0(OT_LONG + s->mem_index); - gen_op_movl_env_T0(offsetof(CPUX86State,xmm_t0.XMM_L(0))); + tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0))); } op2_offset = offsetof(CPUX86State,xmm_t0); } else { @@ -3358,10 +3565,10 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r) (b & 1) * 4]; tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op2_offset); if (ot == OT_LONG) { - tcg_gen_helper_1_1(sse_op2, cpu_tmp2_i32, cpu_ptr0); + ((void (*)(TCGv_i32, TCGv_ptr))sse_op2)(cpu_tmp2_i32, cpu_ptr0); tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); } else { - tcg_gen_helper_1_1(sse_op2, cpu_T[0], cpu_ptr0); + ((void (*)(TCGv, TCGv_ptr))sse_op2)(cpu_T[0], cpu_ptr0); } gen_op_mov_reg_T0(ot, reg); break; @@ -3384,6 +3591,7 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r) case 0x1c5: if (mod != 3) goto illegal_op; + ot = (s->dflag == 2) ? OT_QUAD : OT_LONG; val = ldub_code(s->pc++); if (b1) { val &= 7; @@ -3397,7 +3605,7 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r) offsetof(CPUX86State,fpregs[rm].mmx.MMX_W(val))); } reg = ((modrm >> 3) & 7) | rex_r; - gen_op_mov_reg_T0(OT_LONG, reg); + gen_op_mov_reg_T0(ot, reg); break; case 0x1d6: /* movq ea, xmm */ if (mod != 3) { @@ -3411,14 +3619,14 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r) } break; case 0x2d6: /* movq2dq */ - tcg_gen_helper_0_0(helper_enter_mmx); + gen_helper_enter_mmx(); rm = (modrm & 7); gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)), offsetof(CPUX86State,fpregs[rm].mmx)); gen_op_movq_env_0(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1))); break; case 0x3d6: /* movdq2q */ - tcg_gen_helper_0_0(helper_enter_mmx); + gen_helper_enter_mmx(); rm = (modrm & 7) | REX_B(s); gen_op_movq(offsetof(CPUX86State,fpregs[reg & 7].mmx), offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0))); @@ -3430,16 +3638,294 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r) if (b1) { rm = (modrm & 7) | REX_B(s); tcg_gen_addi_ptr(cpu_ptr0, cpu_env, offsetof(CPUX86State,xmm_regs[rm])); - tcg_gen_helper_1_1(helper_pmovmskb_xmm, cpu_tmp2_i32, cpu_ptr0); + gen_helper_pmovmskb_xmm(cpu_tmp2_i32, cpu_ptr0); } else { rm = (modrm & 7); tcg_gen_addi_ptr(cpu_ptr0, cpu_env, offsetof(CPUX86State,fpregs[rm].mmx)); - tcg_gen_helper_1_1(helper_pmovmskb_mmx, cpu_tmp2_i32, cpu_ptr0); + gen_helper_pmovmskb_mmx(cpu_tmp2_i32, cpu_ptr0); } tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); reg = ((modrm >> 3) & 7) | rex_r; gen_op_mov_reg_T0(OT_LONG, reg); break; + case 0x138: + if (s->prefix & PREFIX_REPNZ) + goto crc32; + case 0x038: + b = modrm; + modrm = ldub_code(s->pc++); + rm = modrm & 7; + reg = ((modrm >> 3) & 7) | rex_r; + mod = (modrm >> 6) & 3; + + sse_op2 = sse_op_table6[b].op[b1]; + if (!sse_op2) + goto illegal_op; + if (!(s->cpuid_ext_features & sse_op_table6[b].ext_mask)) + goto illegal_op; + + if (b1) { + op1_offset = offsetof(CPUX86State,xmm_regs[reg]); + if (mod == 3) { + op2_offset = offsetof(CPUX86State,xmm_regs[rm | REX_B(s)]); + } else { + op2_offset = offsetof(CPUX86State,xmm_t0); + gen_lea_modrm(s, modrm, ®_addr, &offset_addr); + switch (b) { + case 0x20: case 0x30: /* pmovsxbw, pmovzxbw */ + case 0x23: case 0x33: /* pmovsxwd, pmovzxwd */ + case 0x25: case 0x35: /* pmovsxdq, pmovzxdq */ + gen_ldq_env_A0(s->mem_index, op2_offset + + offsetof(XMMReg, XMM_Q(0))); + break; + case 0x21: case 0x31: /* pmovsxbd, pmovzxbd */ + case 0x24: case 0x34: /* pmovsxwq, pmovzxwq */ + tcg_gen_qemu_ld32u(cpu_tmp0, cpu_A0, + (s->mem_index >> 2) - 1); + tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp0); + tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, op2_offset + + offsetof(XMMReg, XMM_L(0))); + break; + case 0x22: case 0x32: /* pmovsxbq, pmovzxbq */ + tcg_gen_qemu_ld16u(cpu_tmp0, cpu_A0, + (s->mem_index >> 2) - 1); + tcg_gen_st16_tl(cpu_tmp0, cpu_env, op2_offset + + offsetof(XMMReg, XMM_W(0))); + break; + case 0x2a: /* movntqda */ + gen_ldo_env_A0(s->mem_index, op1_offset); + return; + default: + gen_ldo_env_A0(s->mem_index, op2_offset); + } + } + } else { + op1_offset = offsetof(CPUX86State,fpregs[reg].mmx); + if (mod == 3) { + op2_offset = offsetof(CPUX86State,fpregs[rm].mmx); + } else { + op2_offset = offsetof(CPUX86State,mmx_t0); + gen_lea_modrm(s, modrm, ®_addr, &offset_addr); + gen_ldq_env_A0(s->mem_index, op2_offset); + } + } + if (sse_op2 == SSE_SPECIAL) + goto illegal_op; + + tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); + tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset); + ((void (*)(TCGv_ptr, TCGv_ptr))sse_op2)(cpu_ptr0, cpu_ptr1); + + if (b == 0x17) + s->cc_op = CC_OP_EFLAGS; + break; + case 0x338: /* crc32 */ + crc32: + b = modrm; + modrm = ldub_code(s->pc++); + reg = ((modrm >> 3) & 7) | rex_r; + + if (b != 0xf0 && b != 0xf1) + goto illegal_op; + if (!(s->cpuid_ext_features & CPUID_EXT_SSE42)) + goto illegal_op; + + if (b == 0xf0) + ot = OT_BYTE; + else if (b == 0xf1 && s->dflag != 2) + if (s->prefix & PREFIX_DATA) + ot = OT_WORD; + else + ot = OT_LONG; + else + ot = OT_QUAD; + + gen_op_mov_TN_reg(OT_LONG, 0, reg); + tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); + gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0); + gen_helper_crc32(cpu_T[0], cpu_tmp2_i32, + cpu_T[0], tcg_const_i32(8 << ot)); + + ot = (s->dflag == 2) ? OT_QUAD : OT_LONG; + gen_op_mov_reg_T0(ot, reg); + break; + case 0x03a: + case 0x13a: + b = modrm; + modrm = ldub_code(s->pc++); + rm = modrm & 7; + reg = ((modrm >> 3) & 7) | rex_r; + mod = (modrm >> 6) & 3; + + sse_op2 = sse_op_table7[b].op[b1]; + if (!sse_op2) + goto illegal_op; + if (!(s->cpuid_ext_features & sse_op_table7[b].ext_mask)) + goto illegal_op; + + if (sse_op2 == SSE_SPECIAL) { + ot = (s->dflag == 2) ? OT_QUAD : OT_LONG; + rm = (modrm & 7) | REX_B(s); + if (mod != 3) + gen_lea_modrm(s, modrm, ®_addr, &offset_addr); + reg = ((modrm >> 3) & 7) | rex_r; + val = ldub_code(s->pc++); + switch (b) { + case 0x14: /* pextrb */ + tcg_gen_ld8u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, + xmm_regs[reg].XMM_B(val & 15))); + if (mod == 3) + gen_op_mov_reg_T0(ot, rm); + else + tcg_gen_qemu_st8(cpu_T[0], cpu_A0, + (s->mem_index >> 2) - 1); + break; + case 0x15: /* pextrw */ + tcg_gen_ld16u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, + xmm_regs[reg].XMM_W(val & 7))); + if (mod == 3) + gen_op_mov_reg_T0(ot, rm); + else + tcg_gen_qemu_st16(cpu_T[0], cpu_A0, + (s->mem_index >> 2) - 1); + break; + case 0x16: + if (ot == OT_LONG) { /* pextrd */ + tcg_gen_ld_i32(cpu_tmp2_i32, cpu_env, + offsetof(CPUX86State, + xmm_regs[reg].XMM_L(val & 3))); + tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); + if (mod == 3) + gen_op_mov_reg_v(ot, rm, cpu_T[0]); + else + tcg_gen_qemu_st32(cpu_T[0], cpu_A0, + (s->mem_index >> 2) - 1); + } else { /* pextrq */ +#ifdef TARGET_X86_64 + tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, + offsetof(CPUX86State, + xmm_regs[reg].XMM_Q(val & 1))); + if (mod == 3) + gen_op_mov_reg_v(ot, rm, cpu_tmp1_i64); + else + tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, + (s->mem_index >> 2) - 1); +#else + goto illegal_op; +#endif + } + break; + case 0x17: /* extractps */ + tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, + xmm_regs[reg].XMM_L(val & 3))); + if (mod == 3) + gen_op_mov_reg_T0(ot, rm); + else + tcg_gen_qemu_st32(cpu_T[0], cpu_A0, + (s->mem_index >> 2) - 1); + break; + case 0x20: /* pinsrb */ + if (mod == 3) + gen_op_mov_TN_reg(OT_LONG, 0, rm); + else + tcg_gen_qemu_ld8u(cpu_tmp0, cpu_A0, + (s->mem_index >> 2) - 1); + tcg_gen_st8_tl(cpu_tmp0, cpu_env, offsetof(CPUX86State, + xmm_regs[reg].XMM_B(val & 15))); + break; + case 0x21: /* insertps */ + if (mod == 3) { + tcg_gen_ld_i32(cpu_tmp2_i32, cpu_env, + offsetof(CPUX86State,xmm_regs[rm] + .XMM_L((val >> 6) & 3))); + } else { + tcg_gen_qemu_ld32u(cpu_tmp0, cpu_A0, + (s->mem_index >> 2) - 1); + tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp0); + } + tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, + offsetof(CPUX86State,xmm_regs[reg] + .XMM_L((val >> 4) & 3))); + if ((val >> 0) & 1) + tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/), + cpu_env, offsetof(CPUX86State, + xmm_regs[reg].XMM_L(0))); + if ((val >> 1) & 1) + tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/), + cpu_env, offsetof(CPUX86State, + xmm_regs[reg].XMM_L(1))); + if ((val >> 2) & 1) + tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/), + cpu_env, offsetof(CPUX86State, + xmm_regs[reg].XMM_L(2))); + if ((val >> 3) & 1) + tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/), + cpu_env, offsetof(CPUX86State, + xmm_regs[reg].XMM_L(3))); + break; + case 0x22: + if (ot == OT_LONG) { /* pinsrd */ + if (mod == 3) + gen_op_mov_v_reg(ot, cpu_tmp0, rm); + else + tcg_gen_qemu_ld32u(cpu_tmp0, cpu_A0, + (s->mem_index >> 2) - 1); + tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp0); + tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, + offsetof(CPUX86State, + xmm_regs[reg].XMM_L(val & 3))); + } else { /* pinsrq */ +#ifdef TARGET_X86_64 + if (mod == 3) + gen_op_mov_v_reg(ot, cpu_tmp1_i64, rm); + else + tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, + (s->mem_index >> 2) - 1); + tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, + offsetof(CPUX86State, + xmm_regs[reg].XMM_Q(val & 1))); +#else + goto illegal_op; +#endif + } + break; + } + return; + } + + if (b1) { + op1_offset = offsetof(CPUX86State,xmm_regs[reg]); + if (mod == 3) { + op2_offset = offsetof(CPUX86State,xmm_regs[rm | REX_B(s)]); + } else { + op2_offset = offsetof(CPUX86State,xmm_t0); + gen_lea_modrm(s, modrm, ®_addr, &offset_addr); + gen_ldo_env_A0(s->mem_index, op2_offset); + } + } else { + op1_offset = offsetof(CPUX86State,fpregs[reg].mmx); + if (mod == 3) { + op2_offset = offsetof(CPUX86State,fpregs[rm].mmx); + } else { + op2_offset = offsetof(CPUX86State,mmx_t0); + gen_lea_modrm(s, modrm, ®_addr, &offset_addr); + gen_ldq_env_A0(s->mem_index, op2_offset); + } + } + val = ldub_code(s->pc++); + + if ((b & 0xfc) == 0x60) { /* pcmpXstrX */ + s->cc_op = CC_OP_EFLAGS; + + if (s->dflag == 2) + /* The helper must use entire 64-bit gp registers */ + val |= 1 << 8; + } + + tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); + tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset); + ((void (*)(TCGv_ptr, TCGv_ptr, TCGv_i32))sse_op2)(cpu_ptr0, cpu_ptr1, tcg_const_i32(val)); + break; default: goto illegal_op; } @@ -3465,7 +3951,7 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r) if (b1 == 2) { /* 32 bit access */ gen_op_ld_T0_A0(OT_LONG + s->mem_index); - gen_op_movl_env_T0(offsetof(CPUX86State,xmm_t0.XMM_L(0))); + tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0))); } else { /* 64 bit access */ gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_t0.XMM_D(0))); @@ -3498,14 +3984,14 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r) goto illegal_op; tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset); - tcg_gen_helper_0_2(sse_op2, cpu_ptr0, cpu_ptr1); + ((void (*)(TCGv_ptr, TCGv_ptr))sse_op2)(cpu_ptr0, cpu_ptr1); break; case 0x70: /* pshufx insn */ case 0xc6: /* pshufx insn */ val = ldub_code(s->pc++); tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset); - tcg_gen_helper_0_3(sse_op2, cpu_ptr0, cpu_ptr1, tcg_const_i32(val)); + ((void (*)(TCGv_ptr, TCGv_ptr, TCGv_i32))sse_op2)(cpu_ptr0, cpu_ptr1, tcg_const_i32(val)); break; case 0xc2: /* compare insns */ @@ -3515,7 +4001,7 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r) sse_op2 = sse_op_table4[val][b1]; tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset); - tcg_gen_helper_0_2(sse_op2, cpu_ptr0, cpu_ptr1); + ((void (*)(TCGv_ptr, TCGv_ptr))sse_op2)(cpu_ptr0, cpu_ptr1); break; case 0xf7: /* maskmov : we must prepare A0 */ @@ -3535,17 +4021,15 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r) tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset); - tcg_gen_helper_0_3(sse_op2, cpu_ptr0, cpu_ptr1, cpu_A0); + ((void (*)(TCGv_ptr, TCGv_ptr, TCGv))sse_op2)(cpu_ptr0, cpu_ptr1, cpu_A0); break; default: tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset); - tcg_gen_helper_0_2(sse_op2, cpu_ptr0, cpu_ptr1); + ((void (*)(TCGv_ptr, TCGv_ptr))sse_op2)(cpu_ptr0, cpu_ptr1); break; } if (b == 0x2e || b == 0x2f) { - /* just to keep the EFLAGS optimization correct */ - gen_op_com_dummy(); s->cc_op = CC_OP_EFLAGS; } } @@ -3561,6 +4045,8 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) target_ulong next_eip, tval; int rex_w, rex_r; + if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) + tcg_gen_debug_insn_start(pc_start); s->pc = pc_start; prefixes = 0; aflag = s->code32; @@ -3682,7 +4168,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) /* lock generation */ if (prefixes & PREFIX_LOCK) - tcg_gen_helper_0_0(helper_lock); + gen_helper_lock(); /* now check op code */ reswitch: @@ -3760,9 +4246,11 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) } break; + case 0x82: + if (CODE64(s)) + goto illegal_op; case 0x80: /* GRP1 */ case 0x81: - case 0x82: case 0x83: { int val; @@ -3862,21 +4350,64 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) case 4: /* mul */ switch(ot) { case OT_BYTE: - gen_op_mulb_AL_T0(); + gen_op_mov_TN_reg(OT_BYTE, 1, R_EAX); + tcg_gen_ext8u_tl(cpu_T[0], cpu_T[0]); + tcg_gen_ext8u_tl(cpu_T[1], cpu_T[1]); + /* XXX: use 32 bit mul which could be faster */ + tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]); + gen_op_mov_reg_T0(OT_WORD, R_EAX); + tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); + tcg_gen_andi_tl(cpu_cc_src, cpu_T[0], 0xff00); s->cc_op = CC_OP_MULB; break; case OT_WORD: - gen_op_mulw_AX_T0(); + gen_op_mov_TN_reg(OT_WORD, 1, R_EAX); + tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]); + tcg_gen_ext16u_tl(cpu_T[1], cpu_T[1]); + /* XXX: use 32 bit mul which could be faster */ + tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]); + gen_op_mov_reg_T0(OT_WORD, R_EAX); + tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); + tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 16); + gen_op_mov_reg_T0(OT_WORD, R_EDX); + tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]); s->cc_op = CC_OP_MULW; break; default: case OT_LONG: - gen_op_mull_EAX_T0(); +#ifdef TARGET_X86_64 + gen_op_mov_TN_reg(OT_LONG, 1, R_EAX); + tcg_gen_ext32u_tl(cpu_T[0], cpu_T[0]); + tcg_gen_ext32u_tl(cpu_T[1], cpu_T[1]); + tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]); + gen_op_mov_reg_T0(OT_LONG, R_EAX); + tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); + tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 32); + gen_op_mov_reg_T0(OT_LONG, R_EDX); + tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]); +#else + { + TCGv_i64 t0, t1; + t0 = tcg_temp_new_i64(); + t1 = tcg_temp_new_i64(); + gen_op_mov_TN_reg(OT_LONG, 1, R_EAX); + tcg_gen_extu_i32_i64(t0, cpu_T[0]); + tcg_gen_extu_i32_i64(t1, cpu_T[1]); + tcg_gen_mul_i64(t0, t0, t1); + tcg_gen_trunc_i64_i32(cpu_T[0], t0); + gen_op_mov_reg_T0(OT_LONG, R_EAX); + tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); + tcg_gen_shri_i64(t0, t0, 32); + tcg_gen_trunc_i64_i32(cpu_T[0], t0); + gen_op_mov_reg_T0(OT_LONG, R_EDX); + tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]); + } +#endif s->cc_op = CC_OP_MULL; break; #ifdef TARGET_X86_64 case OT_QUAD: - gen_op_mulq_EAX_T0(); + gen_helper_mulq_EAX_T0(cpu_T[0]); s->cc_op = CC_OP_MULQ; break; #endif @@ -3885,21 +4416,68 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) case 5: /* imul */ switch(ot) { case OT_BYTE: - gen_op_imulb_AL_T0(); + gen_op_mov_TN_reg(OT_BYTE, 1, R_EAX); + tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]); + tcg_gen_ext8s_tl(cpu_T[1], cpu_T[1]); + /* XXX: use 32 bit mul which could be faster */ + tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]); + gen_op_mov_reg_T0(OT_WORD, R_EAX); + tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); + tcg_gen_ext8s_tl(cpu_tmp0, cpu_T[0]); + tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0); s->cc_op = CC_OP_MULB; break; case OT_WORD: - gen_op_imulw_AX_T0(); + gen_op_mov_TN_reg(OT_WORD, 1, R_EAX); + tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]); + tcg_gen_ext16s_tl(cpu_T[1], cpu_T[1]); + /* XXX: use 32 bit mul which could be faster */ + tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]); + gen_op_mov_reg_T0(OT_WORD, R_EAX); + tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); + tcg_gen_ext16s_tl(cpu_tmp0, cpu_T[0]); + tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0); + tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 16); + gen_op_mov_reg_T0(OT_WORD, R_EDX); s->cc_op = CC_OP_MULW; break; default: case OT_LONG: - gen_op_imull_EAX_T0(); +#ifdef TARGET_X86_64 + gen_op_mov_TN_reg(OT_LONG, 1, R_EAX); + tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]); + tcg_gen_ext32s_tl(cpu_T[1], cpu_T[1]); + tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]); + gen_op_mov_reg_T0(OT_LONG, R_EAX); + tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); + tcg_gen_ext32s_tl(cpu_tmp0, cpu_T[0]); + tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0); + tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 32); + gen_op_mov_reg_T0(OT_LONG, R_EDX); +#else + { + TCGv_i64 t0, t1; + t0 = tcg_temp_new_i64(); + t1 = tcg_temp_new_i64(); + gen_op_mov_TN_reg(OT_LONG, 1, R_EAX); + tcg_gen_ext_i32_i64(t0, cpu_T[0]); + tcg_gen_ext_i32_i64(t1, cpu_T[1]); + tcg_gen_mul_i64(t0, t0, t1); + tcg_gen_trunc_i64_i32(cpu_T[0], t0); + gen_op_mov_reg_T0(OT_LONG, R_EAX); + tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); + tcg_gen_sari_tl(cpu_tmp0, cpu_T[0], 31); + tcg_gen_shri_i64(t0, t0, 32); + tcg_gen_trunc_i64_i32(cpu_T[0], t0); + gen_op_mov_reg_T0(OT_LONG, R_EDX); + tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0); + } +#endif s->cc_op = CC_OP_MULL; break; #ifdef TARGET_X86_64 case OT_QUAD: - gen_op_imulq_EAX_T0(); + gen_helper_imulq_EAX_T0(cpu_T[0]); s->cc_op = CC_OP_MULQ; break; #endif @@ -3909,21 +4487,21 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) switch(ot) { case OT_BYTE: gen_jmp_im(pc_start - s->cs_base); - tcg_gen_helper_0_1(helper_divb_AL, cpu_T[0]); + gen_helper_divb_AL(cpu_T[0]); break; case OT_WORD: gen_jmp_im(pc_start - s->cs_base); - tcg_gen_helper_0_1(helper_divw_AX, cpu_T[0]); + gen_helper_divw_AX(cpu_T[0]); break; default: case OT_LONG: gen_jmp_im(pc_start - s->cs_base); - tcg_gen_helper_0_1(helper_divl_EAX, cpu_T[0]); + gen_helper_divl_EAX(cpu_T[0]); break; #ifdef TARGET_X86_64 case OT_QUAD: gen_jmp_im(pc_start - s->cs_base); - tcg_gen_helper_0_1(helper_divq_EAX, cpu_T[0]); + gen_helper_divq_EAX(cpu_T[0]); break; #endif } @@ -3932,21 +4510,21 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) switch(ot) { case OT_BYTE: gen_jmp_im(pc_start - s->cs_base); - tcg_gen_helper_0_1(helper_idivb_AL, cpu_T[0]); + gen_helper_idivb_AL(cpu_T[0]); break; case OT_WORD: gen_jmp_im(pc_start - s->cs_base); - tcg_gen_helper_0_1(helper_idivw_AX, cpu_T[0]); + gen_helper_idivw_AX(cpu_T[0]); break; default: case OT_LONG: gen_jmp_im(pc_start - s->cs_base); - tcg_gen_helper_0_1(helper_idivl_EAX, cpu_T[0]); + gen_helper_idivl_EAX(cpu_T[0]); break; #ifdef TARGET_X86_64 case OT_QUAD: gen_jmp_im(pc_start - s->cs_base); - tcg_gen_helper_0_1(helper_idivq_EAX, cpu_T[0]); + gen_helper_idivq_EAX(cpu_T[0]); break; #endif } @@ -4026,16 +4604,14 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) gen_op_set_cc_op(s->cc_op); gen_jmp_im(pc_start - s->cs_base); tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); - tcg_gen_helper_0_4(helper_lcall_protected, - cpu_tmp2_i32, cpu_T[1], - tcg_const_i32(dflag), - tcg_const_i32(s->pc - pc_start)); + gen_helper_lcall_protected(cpu_tmp2_i32, cpu_T[1], + tcg_const_i32(dflag), + tcg_const_i32(s->pc - pc_start)); } else { tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); - tcg_gen_helper_0_4(helper_lcall_real, - cpu_tmp2_i32, cpu_T[1], - tcg_const_i32(dflag), - tcg_const_i32(s->pc - s->cs_base)); + gen_helper_lcall_real(cpu_tmp2_i32, cpu_T[1], + tcg_const_i32(dflag), + tcg_const_i32(s->pc - s->cs_base)); } gen_eob(s); break; @@ -4055,12 +4631,10 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) gen_op_set_cc_op(s->cc_op); gen_jmp_im(pc_start - s->cs_base); tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); - tcg_gen_helper_0_3(helper_ljmp_protected, - cpu_tmp2_i32, - cpu_T[1], - tcg_const_i32(s->pc - pc_start)); + gen_helper_ljmp_protected(cpu_tmp2_i32, cpu_T[1], + tcg_const_i32(s->pc - pc_start)); } else { - gen_op_movl_seg_T0_vm(offsetof(CPUX86State,segs[R_CS])); + gen_op_movl_seg_T0_vm(R_CS); gen_op_movl_T0_T1(); gen_op_jmp_T0(); } @@ -4167,13 +4741,41 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) #ifdef TARGET_X86_64 if (ot == OT_QUAD) { - gen_op_imulq_T0_T1(); + gen_helper_imulq_T0_T1(cpu_T[0], cpu_T[0], cpu_T[1]); } else #endif if (ot == OT_LONG) { - gen_op_imull_T0_T1(); +#ifdef TARGET_X86_64 + tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]); + tcg_gen_ext32s_tl(cpu_T[1], cpu_T[1]); + tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]); + tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); + tcg_gen_ext32s_tl(cpu_tmp0, cpu_T[0]); + tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0); +#else + { + TCGv_i64 t0, t1; + t0 = tcg_temp_new_i64(); + t1 = tcg_temp_new_i64(); + tcg_gen_ext_i32_i64(t0, cpu_T[0]); + tcg_gen_ext_i32_i64(t1, cpu_T[1]); + tcg_gen_mul_i64(t0, t0, t1); + tcg_gen_trunc_i64_i32(cpu_T[0], t0); + tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); + tcg_gen_sari_tl(cpu_tmp0, cpu_T[0], 31); + tcg_gen_shri_i64(t0, t0, 32); + tcg_gen_trunc_i64_i32(cpu_T[1], t0); + tcg_gen_sub_tl(cpu_cc_src, cpu_T[1], cpu_tmp0); + } +#endif } else { - gen_op_imulw_T0_T1(); + tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]); + tcg_gen_ext16s_tl(cpu_T[1], cpu_T[1]); + /* XXX: use 32 bit mul which could be faster */ + tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]); + tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); + tcg_gen_ext16s_tl(cpu_tmp0, cpu_T[0]); + tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0); } gen_op_mov_reg_T0(ot, reg); s->cc_op = CC_OP_MULB + ot; @@ -4208,7 +4810,8 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) case 0x1b0: case 0x1b1: /* cmpxchg Ev, Gv */ { - int label1; + int label1, label2; + TCGv t0, t1, t2, a0; if ((b & 1) == 0) ot = OT_BYTE; @@ -4217,31 +4820,46 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) modrm = ldub_code(s->pc++); reg = ((modrm >> 3) & 7) | rex_r; mod = (modrm >> 6) & 3; - gen_op_mov_TN_reg(ot, 1, reg); + t0 = tcg_temp_local_new(); + t1 = tcg_temp_local_new(); + t2 = tcg_temp_local_new(); + a0 = tcg_temp_local_new(); + gen_op_mov_v_reg(ot, t1, reg); if (mod == 3) { rm = (modrm & 7) | REX_B(s); - gen_op_mov_TN_reg(ot, 0, rm); + gen_op_mov_v_reg(ot, t0, rm); } else { gen_lea_modrm(s, modrm, ®_addr, &offset_addr); - gen_op_ld_T0_A0(ot + s->mem_index); + tcg_gen_mov_tl(a0, cpu_A0); + gen_op_ld_v(ot + s->mem_index, t0, a0); rm = 0; /* avoid warning */ } label1 = gen_new_label(); - tcg_gen_ld_tl(cpu_T3, cpu_env, offsetof(CPUState, regs[R_EAX])); - tcg_gen_sub_tl(cpu_T3, cpu_T3, cpu_T[0]); - gen_extu(ot, cpu_T3); - tcg_gen_brcond_tl(TCG_COND_EQ, cpu_T3, tcg_const_tl(0), label1); - tcg_gen_mov_tl(cpu_T[1], cpu_T[0]); - gen_op_mov_reg_T0(ot, R_EAX); - gen_set_label(label1); + tcg_gen_ld_tl(t2, cpu_env, offsetof(CPUState, regs[R_EAX])); + tcg_gen_sub_tl(t2, t2, t0); + gen_extu(ot, t2); + tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, label1); if (mod == 3) { - gen_op_mov_reg_T1(ot, rm); + label2 = gen_new_label(); + gen_op_mov_reg_v(ot, R_EAX, t0); + tcg_gen_br(label2); + gen_set_label(label1); + gen_op_mov_reg_v(ot, rm, t1); + gen_set_label(label2); } else { - gen_op_st_T1_A0(ot + s->mem_index); + tcg_gen_mov_tl(t1, t0); + gen_op_mov_reg_v(ot, R_EAX, t0); + gen_set_label(label1); + /* always store */ + gen_op_st_v(ot + s->mem_index, t1, a0); } - tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]); - tcg_gen_mov_tl(cpu_cc_dst, cpu_T3); + tcg_gen_mov_tl(cpu_cc_src, t0); + tcg_gen_mov_tl(cpu_cc_dst, t2); s->cc_op = CC_OP_SUBB + ot; + tcg_temp_free(t0); + tcg_temp_free(t1); + tcg_temp_free(t2); + tcg_temp_free(a0); } break; case 0x1c7: /* cmpxchg8b */ @@ -4249,11 +4867,26 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) mod = (modrm >> 6) & 3; if ((mod == 3) || ((modrm & 0x38) != 0x8)) goto illegal_op; - gen_jmp_im(pc_start - s->cs_base); - if (s->cc_op != CC_OP_DYNAMIC) - gen_op_set_cc_op(s->cc_op); - gen_lea_modrm(s, modrm, ®_addr, &offset_addr); - gen_op_cmpxchg8b(); +#ifdef TARGET_X86_64 + if (dflag == 2) { + if (!(s->cpuid_ext_features & CPUID_EXT_CX16)) + goto illegal_op; + gen_jmp_im(pc_start - s->cs_base); + if (s->cc_op != CC_OP_DYNAMIC) + gen_op_set_cc_op(s->cc_op); + gen_lea_modrm(s, modrm, ®_addr, &offset_addr); + gen_helper_cmpxchg16b(cpu_A0); + } else +#endif + { + if (!(s->cpuid_features & CPUID_CX8)) + goto illegal_op; + gen_jmp_im(pc_start - s->cs_base); + if (s->cc_op != CC_OP_DYNAMIC) + gen_op_set_cc_op(s->cc_op); + gen_lea_modrm(s, modrm, ®_addr, &offset_addr); + gen_helper_cmpxchg8b(cpu_A0); + } s->cc_op = CC_OP_EFLAGS; break; @@ -4378,7 +5011,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) /* If several instructions disable interrupts, only the _first_ does it */ if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK)) - tcg_gen_helper_0_0(helper_set_inhibit_irq); + gen_helper_set_inhibit_irq(); s->tf = 0; } if (s->is_jmp) { @@ -4454,7 +5087,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) /* If several instructions disable interrupts, only the _first_ does it */ if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK)) - tcg_gen_helper_0_0(helper_set_inhibit_irq); + gen_helper_set_inhibit_irq(); s->tf = 0; } if (s->is_jmp) { @@ -4648,11 +5281,11 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) gen_op_mov_TN_reg(ot, 0, reg); /* for xchg, lock is implicit */ if (!(prefixes & PREFIX_LOCK)) - tcg_gen_helper_0_0(helper_lock); + gen_helper_lock(); gen_op_ld_T1_A0(ot + s->mem_index); gen_op_st_T0_A0(ot + s->mem_index); if (!(prefixes & PREFIX_LOCK)) - tcg_gen_helper_0_0(helper_unlock); + gen_helper_unlock(); gen_op_mov_reg_T1(ot, reg); } break; @@ -4811,30 +5444,30 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) case 0: gen_op_ld_T0_A0(OT_LONG + s->mem_index); tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); - tcg_gen_helper_0_1(helper_flds_FT0, cpu_tmp2_i32); + gen_helper_flds_FT0(cpu_tmp2_i32); break; case 1: gen_op_ld_T0_A0(OT_LONG + s->mem_index); tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); - tcg_gen_helper_0_1(helper_fildl_FT0, cpu_tmp2_i32); + gen_helper_fildl_FT0(cpu_tmp2_i32); break; case 2: tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, (s->mem_index >> 2) - 1); - tcg_gen_helper_0_1(helper_fldl_FT0, cpu_tmp1_i64); + gen_helper_fldl_FT0(cpu_tmp1_i64); break; case 3: default: gen_op_lds_T0_A0(OT_WORD + s->mem_index); tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); - tcg_gen_helper_0_1(helper_fildl_FT0, cpu_tmp2_i32); + gen_helper_fildl_FT0(cpu_tmp2_i32); break; } - tcg_gen_helper_0_0(helper_fp_arith_ST0_FT0[op1]); + gen_helper_fp_arith_ST0_FT0(op1); if (op1 == 3) { /* fcomp needs pop */ - tcg_gen_helper_0_0(helper_fpop); + gen_helper_fpop(); } } break; @@ -4850,23 +5483,23 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) case 0: gen_op_ld_T0_A0(OT_LONG + s->mem_index); tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); - tcg_gen_helper_0_1(helper_flds_ST0, cpu_tmp2_i32); + gen_helper_flds_ST0(cpu_tmp2_i32); break; case 1: gen_op_ld_T0_A0(OT_LONG + s->mem_index); tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); - tcg_gen_helper_0_1(helper_fildl_ST0, cpu_tmp2_i32); + gen_helper_fildl_ST0(cpu_tmp2_i32); break; case 2: tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, (s->mem_index >> 2) - 1); - tcg_gen_helper_0_1(helper_fldl_ST0, cpu_tmp1_i64); + gen_helper_fldl_ST0(cpu_tmp1_i64); break; case 3: default: gen_op_lds_T0_A0(OT_WORD + s->mem_index); tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); - tcg_gen_helper_0_1(helper_fildl_ST0, cpu_tmp2_i32); + gen_helper_fildl_ST0(cpu_tmp2_i32); break; } break; @@ -4874,50 +5507,50 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) /* XXX: the corresponding CPUID bit must be tested ! */ switch(op >> 4) { case 1: - tcg_gen_helper_1_0(helper_fisttl_ST0, cpu_tmp2_i32); + gen_helper_fisttl_ST0(cpu_tmp2_i32); tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); gen_op_st_T0_A0(OT_LONG + s->mem_index); break; case 2: - tcg_gen_helper_1_0(helper_fisttll_ST0, cpu_tmp1_i64); + gen_helper_fisttll_ST0(cpu_tmp1_i64); tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, (s->mem_index >> 2) - 1); break; case 3: default: - tcg_gen_helper_1_0(helper_fistt_ST0, cpu_tmp2_i32); + gen_helper_fistt_ST0(cpu_tmp2_i32); tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); gen_op_st_T0_A0(OT_WORD + s->mem_index); break; } - tcg_gen_helper_0_0(helper_fpop); + gen_helper_fpop(); break; default: switch(op >> 4) { case 0: - tcg_gen_helper_1_0(helper_fsts_ST0, cpu_tmp2_i32); + gen_helper_fsts_ST0(cpu_tmp2_i32); tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); gen_op_st_T0_A0(OT_LONG + s->mem_index); break; case 1: - tcg_gen_helper_1_0(helper_fistl_ST0, cpu_tmp2_i32); + gen_helper_fistl_ST0(cpu_tmp2_i32); tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); gen_op_st_T0_A0(OT_LONG + s->mem_index); break; case 2: - tcg_gen_helper_1_0(helper_fstl_ST0, cpu_tmp1_i64); + gen_helper_fstl_ST0(cpu_tmp1_i64); tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, (s->mem_index >> 2) - 1); break; case 3: default: - tcg_gen_helper_1_0(helper_fist_ST0, cpu_tmp2_i32); + gen_helper_fist_ST0(cpu_tmp2_i32); tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); gen_op_st_T0_A0(OT_WORD + s->mem_index); break; } if ((op & 7) == 3) - tcg_gen_helper_0_0(helper_fpop); + gen_helper_fpop(); break; } break; @@ -4925,23 +5558,22 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) if (s->cc_op != CC_OP_DYNAMIC) gen_op_set_cc_op(s->cc_op); gen_jmp_im(pc_start - s->cs_base); - tcg_gen_helper_0_2(helper_fldenv, + gen_helper_fldenv( cpu_A0, tcg_const_i32(s->dflag)); break; case 0x0d: /* fldcw mem */ gen_op_ld_T0_A0(OT_WORD + s->mem_index); tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); - tcg_gen_helper_0_1(helper_fldcw, cpu_tmp2_i32); + gen_helper_fldcw(cpu_tmp2_i32); break; case 0x0e: /* fnstenv mem */ if (s->cc_op != CC_OP_DYNAMIC) gen_op_set_cc_op(s->cc_op); gen_jmp_im(pc_start - s->cs_base); - tcg_gen_helper_0_2(helper_fstenv, - cpu_A0, tcg_const_i32(s->dflag)); + gen_helper_fstenv(cpu_A0, tcg_const_i32(s->dflag)); break; case 0x0f: /* fnstcw mem */ - tcg_gen_helper_1_0(helper_fnstcw, cpu_tmp2_i32); + gen_helper_fnstcw(cpu_tmp2_i32); tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); gen_op_st_T0_A0(OT_WORD + s->mem_index); break; @@ -4949,31 +5581,29 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) if (s->cc_op != CC_OP_DYNAMIC) gen_op_set_cc_op(s->cc_op); gen_jmp_im(pc_start - s->cs_base); - tcg_gen_helper_0_1(helper_fldt_ST0, cpu_A0); + gen_helper_fldt_ST0(cpu_A0); break; case 0x1f: /* fstpt mem */ if (s->cc_op != CC_OP_DYNAMIC) gen_op_set_cc_op(s->cc_op); gen_jmp_im(pc_start - s->cs_base); - tcg_gen_helper_0_1(helper_fstt_ST0, cpu_A0); - tcg_gen_helper_0_0(helper_fpop); + gen_helper_fstt_ST0(cpu_A0); + gen_helper_fpop(); break; case 0x2c: /* frstor mem */ if (s->cc_op != CC_OP_DYNAMIC) gen_op_set_cc_op(s->cc_op); gen_jmp_im(pc_start - s->cs_base); - tcg_gen_helper_0_2(helper_frstor, - cpu_A0, tcg_const_i32(s->dflag)); + gen_helper_frstor(cpu_A0, tcg_const_i32(s->dflag)); break; case 0x2e: /* fnsave mem */ if (s->cc_op != CC_OP_DYNAMIC) gen_op_set_cc_op(s->cc_op); gen_jmp_im(pc_start - s->cs_base); - tcg_gen_helper_0_2(helper_fsave, - cpu_A0, tcg_const_i32(s->dflag)); + gen_helper_fsave(cpu_A0, tcg_const_i32(s->dflag)); break; case 0x2f: /* fnstsw mem */ - tcg_gen_helper_1_0(helper_fnstsw, cpu_tmp2_i32); + gen_helper_fnstsw(cpu_tmp2_i32); tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); gen_op_st_T0_A0(OT_WORD + s->mem_index); break; @@ -4981,25 +5611,25 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) if (s->cc_op != CC_OP_DYNAMIC) gen_op_set_cc_op(s->cc_op); gen_jmp_im(pc_start - s->cs_base); - tcg_gen_helper_0_1(helper_fbld_ST0, cpu_A0); + gen_helper_fbld_ST0(cpu_A0); break; case 0x3e: /* fbstp */ if (s->cc_op != CC_OP_DYNAMIC) gen_op_set_cc_op(s->cc_op); gen_jmp_im(pc_start - s->cs_base); - tcg_gen_helper_0_1(helper_fbst_ST0, cpu_A0); - tcg_gen_helper_0_0(helper_fpop); + gen_helper_fbst_ST0(cpu_A0); + gen_helper_fpop(); break; case 0x3d: /* fildll */ tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, (s->mem_index >> 2) - 1); - tcg_gen_helper_0_1(helper_fildll_ST0, cpu_tmp1_i64); + gen_helper_fildll_ST0(cpu_tmp1_i64); break; case 0x3f: /* fistpll */ - tcg_gen_helper_1_0(helper_fistll_ST0, cpu_tmp1_i64); + gen_helper_fistll_ST0(cpu_tmp1_i64); tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, (s->mem_index >> 2) - 1); - tcg_gen_helper_0_0(helper_fpop); + gen_helper_fpop(); break; default: goto illegal_op; @@ -5010,13 +5640,13 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) switch(op) { case 0x08: /* fld sti */ - tcg_gen_helper_0_0(helper_fpush); - tcg_gen_helper_0_1(helper_fmov_ST0_STN, tcg_const_i32((opreg + 1) & 7)); + gen_helper_fpush(); + gen_helper_fmov_ST0_STN(tcg_const_i32((opreg + 1) & 7)); break; case 0x09: /* fxchg sti */ case 0x29: /* fxchg4 sti, undocumented op */ case 0x39: /* fxchg7 sti, undocumented op */ - tcg_gen_helper_0_1(helper_fxchg_ST0_STN, tcg_const_i32(opreg)); + gen_helper_fxchg_ST0_STN(tcg_const_i32(opreg)); break; case 0x0a: /* grp d9/2 */ switch(rm) { @@ -5025,7 +5655,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) if (s->cc_op != CC_OP_DYNAMIC) gen_op_set_cc_op(s->cc_op); gen_jmp_im(pc_start - s->cs_base); - tcg_gen_helper_0_0(helper_fwait); + gen_helper_fwait(); break; default: goto illegal_op; @@ -5034,17 +5664,17 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) case 0x0c: /* grp d9/4 */ switch(rm) { case 0: /* fchs */ - tcg_gen_helper_0_0(helper_fchs_ST0); + gen_helper_fchs_ST0(); break; case 1: /* fabs */ - tcg_gen_helper_0_0(helper_fabs_ST0); + gen_helper_fabs_ST0(); break; case 4: /* ftst */ - tcg_gen_helper_0_0(helper_fldz_FT0); - tcg_gen_helper_0_0(helper_fcom_ST0_FT0); + gen_helper_fldz_FT0(); + gen_helper_fcom_ST0_FT0(); break; case 5: /* fxam */ - tcg_gen_helper_0_0(helper_fxam_ST0); + gen_helper_fxam_ST0(); break; default: goto illegal_op; @@ -5054,32 +5684,32 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) { switch(rm) { case 0: - tcg_gen_helper_0_0(helper_fpush); - tcg_gen_helper_0_0(helper_fld1_ST0); + gen_helper_fpush(); + gen_helper_fld1_ST0(); break; case 1: - tcg_gen_helper_0_0(helper_fpush); - tcg_gen_helper_0_0(helper_fldl2t_ST0); + gen_helper_fpush(); + gen_helper_fldl2t_ST0(); break; case 2: - tcg_gen_helper_0_0(helper_fpush); - tcg_gen_helper_0_0(helper_fldl2e_ST0); + gen_helper_fpush(); + gen_helper_fldl2e_ST0(); break; case 3: - tcg_gen_helper_0_0(helper_fpush); - tcg_gen_helper_0_0(helper_fldpi_ST0); + gen_helper_fpush(); + gen_helper_fldpi_ST0(); break; case 4: - tcg_gen_helper_0_0(helper_fpush); - tcg_gen_helper_0_0(helper_fldlg2_ST0); + gen_helper_fpush(); + gen_helper_fldlg2_ST0(); break; case 5: - tcg_gen_helper_0_0(helper_fpush); - tcg_gen_helper_0_0(helper_fldln2_ST0); + gen_helper_fpush(); + gen_helper_fldln2_ST0(); break; case 6: - tcg_gen_helper_0_0(helper_fpush); - tcg_gen_helper_0_0(helper_fldz_ST0); + gen_helper_fpush(); + gen_helper_fldz_ST0(); break; default: goto illegal_op; @@ -5089,58 +5719,58 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) case 0x0e: /* grp d9/6 */ switch(rm) { case 0: /* f2xm1 */ - tcg_gen_helper_0_0(helper_f2xm1); + gen_helper_f2xm1(); break; case 1: /* fyl2x */ - tcg_gen_helper_0_0(helper_fyl2x); + gen_helper_fyl2x(); break; case 2: /* fptan */ - tcg_gen_helper_0_0(helper_fptan); + gen_helper_fptan(); break; case 3: /* fpatan */ - tcg_gen_helper_0_0(helper_fpatan); + gen_helper_fpatan(); break; case 4: /* fxtract */ - tcg_gen_helper_0_0(helper_fxtract); + gen_helper_fxtract(); break; case 5: /* fprem1 */ - tcg_gen_helper_0_0(helper_fprem1); + gen_helper_fprem1(); break; case 6: /* fdecstp */ - tcg_gen_helper_0_0(helper_fdecstp); + gen_helper_fdecstp(); break; default: case 7: /* fincstp */ - tcg_gen_helper_0_0(helper_fincstp); + gen_helper_fincstp(); break; } break; case 0x0f: /* grp d9/7 */ switch(rm) { case 0: /* fprem */ - tcg_gen_helper_0_0(helper_fprem); + gen_helper_fprem(); break; case 1: /* fyl2xp1 */ - tcg_gen_helper_0_0(helper_fyl2xp1); + gen_helper_fyl2xp1(); break; case 2: /* fsqrt */ - tcg_gen_helper_0_0(helper_fsqrt); + gen_helper_fsqrt(); break; case 3: /* fsincos */ - tcg_gen_helper_0_0(helper_fsincos); + gen_helper_fsincos(); break; case 5: /* fscale */ - tcg_gen_helper_0_0(helper_fscale); + gen_helper_fscale(); break; case 4: /* frndint */ - tcg_gen_helper_0_0(helper_frndint); + gen_helper_frndint(); break; case 6: /* fsin */ - tcg_gen_helper_0_0(helper_fsin); + gen_helper_fsin(); break; default: case 7: /* fcos */ - tcg_gen_helper_0_0(helper_fcos); + gen_helper_fcos(); break; } break; @@ -5152,34 +5782,34 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) op1 = op & 7; if (op >= 0x20) { - tcg_gen_helper_0_1(helper_fp_arith_STN_ST0[op1], tcg_const_i32(opreg)); + gen_helper_fp_arith_STN_ST0(op1, opreg); if (op >= 0x30) - tcg_gen_helper_0_0(helper_fpop); + gen_helper_fpop(); } else { - tcg_gen_helper_0_1(helper_fmov_FT0_STN, tcg_const_i32(opreg)); - tcg_gen_helper_0_0(helper_fp_arith_ST0_FT0[op1]); + gen_helper_fmov_FT0_STN(tcg_const_i32(opreg)); + gen_helper_fp_arith_ST0_FT0(op1); } } break; case 0x02: /* fcom */ case 0x22: /* fcom2, undocumented op */ - tcg_gen_helper_0_1(helper_fmov_FT0_STN, tcg_const_i32(opreg)); - tcg_gen_helper_0_0(helper_fcom_ST0_FT0); + gen_helper_fmov_FT0_STN(tcg_const_i32(opreg)); + gen_helper_fcom_ST0_FT0(); break; case 0x03: /* fcomp */ case 0x23: /* fcomp3, undocumented op */ case 0x32: /* fcomp5, undocumented op */ - tcg_gen_helper_0_1(helper_fmov_FT0_STN, tcg_const_i32(opreg)); - tcg_gen_helper_0_0(helper_fcom_ST0_FT0); - tcg_gen_helper_0_0(helper_fpop); + gen_helper_fmov_FT0_STN(tcg_const_i32(opreg)); + gen_helper_fcom_ST0_FT0(); + gen_helper_fpop(); break; case 0x15: /* da/5 */ switch(rm) { case 1: /* fucompp */ - tcg_gen_helper_0_1(helper_fmov_FT0_STN, tcg_const_i32(1)); - tcg_gen_helper_0_0(helper_fucom_ST0_FT0); - tcg_gen_helper_0_0(helper_fpop); - tcg_gen_helper_0_0(helper_fpop); + gen_helper_fmov_FT0_STN(tcg_const_i32(1)); + gen_helper_fucom_ST0_FT0(); + gen_helper_fpop(); + gen_helper_fpop(); break; default: goto illegal_op; @@ -5192,10 +5822,10 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) case 1: /* fdisi (287 only, just do nop here) */ break; case 2: /* fclex */ - tcg_gen_helper_0_0(helper_fclex); + gen_helper_fclex(); break; case 3: /* fninit */ - tcg_gen_helper_0_0(helper_fninit); + gen_helper_fninit(); break; case 4: /* fsetpm (287 only, just do nop here) */ break; @@ -5206,61 +5836,59 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) case 0x1d: /* fucomi */ if (s->cc_op != CC_OP_DYNAMIC) gen_op_set_cc_op(s->cc_op); - tcg_gen_helper_0_1(helper_fmov_FT0_STN, tcg_const_i32(opreg)); - tcg_gen_helper_0_0(helper_fucomi_ST0_FT0); - gen_op_fcomi_dummy(); + gen_helper_fmov_FT0_STN(tcg_const_i32(opreg)); + gen_helper_fucomi_ST0_FT0(); s->cc_op = CC_OP_EFLAGS; break; case 0x1e: /* fcomi */ if (s->cc_op != CC_OP_DYNAMIC) gen_op_set_cc_op(s->cc_op); - tcg_gen_helper_0_1(helper_fmov_FT0_STN, tcg_const_i32(opreg)); - tcg_gen_helper_0_0(helper_fcomi_ST0_FT0); - gen_op_fcomi_dummy(); + gen_helper_fmov_FT0_STN(tcg_const_i32(opreg)); + gen_helper_fcomi_ST0_FT0(); s->cc_op = CC_OP_EFLAGS; break; case 0x28: /* ffree sti */ - tcg_gen_helper_0_1(helper_ffree_STN, tcg_const_i32(opreg)); + gen_helper_ffree_STN(tcg_const_i32(opreg)); break; case 0x2a: /* fst sti */ - tcg_gen_helper_0_1(helper_fmov_STN_ST0, tcg_const_i32(opreg)); + gen_helper_fmov_STN_ST0(tcg_const_i32(opreg)); break; case 0x2b: /* fstp sti */ case 0x0b: /* fstp1 sti, undocumented op */ case 0x3a: /* fstp8 sti, undocumented op */ case 0x3b: /* fstp9 sti, undocumented op */ - tcg_gen_helper_0_1(helper_fmov_STN_ST0, tcg_const_i32(opreg)); - tcg_gen_helper_0_0(helper_fpop); + gen_helper_fmov_STN_ST0(tcg_const_i32(opreg)); + gen_helper_fpop(); break; case 0x2c: /* fucom st(i) */ - tcg_gen_helper_0_1(helper_fmov_FT0_STN, tcg_const_i32(opreg)); - tcg_gen_helper_0_0(helper_fucom_ST0_FT0); + gen_helper_fmov_FT0_STN(tcg_const_i32(opreg)); + gen_helper_fucom_ST0_FT0(); break; case 0x2d: /* fucomp st(i) */ - tcg_gen_helper_0_1(helper_fmov_FT0_STN, tcg_const_i32(opreg)); - tcg_gen_helper_0_0(helper_fucom_ST0_FT0); - tcg_gen_helper_0_0(helper_fpop); + gen_helper_fmov_FT0_STN(tcg_const_i32(opreg)); + gen_helper_fucom_ST0_FT0(); + gen_helper_fpop(); break; case 0x33: /* de/3 */ switch(rm) { case 1: /* fcompp */ - tcg_gen_helper_0_1(helper_fmov_FT0_STN, tcg_const_i32(1)); - tcg_gen_helper_0_0(helper_fcom_ST0_FT0); - tcg_gen_helper_0_0(helper_fpop); - tcg_gen_helper_0_0(helper_fpop); + gen_helper_fmov_FT0_STN(tcg_const_i32(1)); + gen_helper_fcom_ST0_FT0(); + gen_helper_fpop(); + gen_helper_fpop(); break; default: goto illegal_op; } break; case 0x38: /* ffreep sti, undocumented op */ - tcg_gen_helper_0_1(helper_ffree_STN, tcg_const_i32(opreg)); - tcg_gen_helper_0_0(helper_fpop); + gen_helper_ffree_STN(tcg_const_i32(opreg)); + gen_helper_fpop(); break; case 0x3c: /* df/4 */ switch(rm) { case 0: - tcg_gen_helper_1_0(helper_fnstsw, cpu_tmp2_i32); + gen_helper_fnstsw(cpu_tmp2_i32); tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); gen_op_mov_reg_T0(OT_WORD, R_EAX); break; @@ -5271,36 +5899,33 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) case 0x3d: /* fucomip */ if (s->cc_op != CC_OP_DYNAMIC) gen_op_set_cc_op(s->cc_op); - tcg_gen_helper_0_1(helper_fmov_FT0_STN, tcg_const_i32(opreg)); - tcg_gen_helper_0_0(helper_fucomi_ST0_FT0); - tcg_gen_helper_0_0(helper_fpop); - gen_op_fcomi_dummy(); + gen_helper_fmov_FT0_STN(tcg_const_i32(opreg)); + gen_helper_fucomi_ST0_FT0(); + gen_helper_fpop(); s->cc_op = CC_OP_EFLAGS; break; case 0x3e: /* fcomip */ if (s->cc_op != CC_OP_DYNAMIC) gen_op_set_cc_op(s->cc_op); - tcg_gen_helper_0_1(helper_fmov_FT0_STN, tcg_const_i32(opreg)); - tcg_gen_helper_0_0(helper_fcomi_ST0_FT0); - tcg_gen_helper_0_0(helper_fpop); - gen_op_fcomi_dummy(); + gen_helper_fmov_FT0_STN(tcg_const_i32(opreg)); + gen_helper_fcomi_ST0_FT0(); + gen_helper_fpop(); s->cc_op = CC_OP_EFLAGS; break; case 0x10 ... 0x13: /* fcmovxx */ case 0x18 ... 0x1b: { int op1, l1; - const static uint8_t fcmov_cc[8] = { + static const uint8_t fcmov_cc[8] = { (JCC_B << 1), (JCC_Z << 1), (JCC_BE << 1), (JCC_P << 1), }; - op1 = fcmov_cc[op & 3] | ((op >> 3) & 1); - gen_setcc(s, op1); + op1 = fcmov_cc[op & 3] | (((op >> 3) & 1) ^ 1); l1 = gen_new_label(); - tcg_gen_brcond_tl(TCG_COND_EQ, cpu_T[0], tcg_const_tl(0), l1); - tcg_gen_helper_0_1(helper_fmov_ST0_STN, tcg_const_i32(opreg)); + gen_jcc1(s, s->cc_op, op1, l1); + gen_helper_fmov_ST0_STN(tcg_const_i32(opreg)); gen_set_label(l1); } break; @@ -5396,6 +6021,9 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) gen_repz_ins(s, ot, pc_start - s->cs_base, s->pc - s->cs_base); } else { gen_ins(s, ot); + if (use_icount) { + gen_jmp(s, s->pc - s->cs_base); + } } break; case 0x6e: /* outsS */ @@ -5412,6 +6040,9 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) gen_repz_outs(s, ot, pc_start - s->cs_base, s->pc - s->cs_base); } else { gen_outs(s, ot); + if (use_icount) { + gen_jmp(s, s->pc - s->cs_base); + } } break; @@ -5428,9 +6059,15 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) gen_op_movl_T0_im(val); gen_check_io(s, ot, pc_start - s->cs_base, SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes)); + if (use_icount) + gen_io_start(); tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); - tcg_gen_helper_1_1(helper_in_func[ot], cpu_T[1], cpu_tmp2_i32); + gen_helper_in_func(ot, cpu_T[1], cpu_tmp2_i32); gen_op_mov_reg_T1(ot, R_EAX); + if (use_icount) { + gen_io_end(); + gen_jmp(s, s->pc - s->cs_base); + } break; case 0xe6: case 0xe7: @@ -5444,10 +6081,16 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) svm_is_rep(prefixes)); gen_op_mov_TN_reg(ot, 1, R_EAX); + if (use_icount) + gen_io_start(); tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff); tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[1]); - tcg_gen_helper_0_2(helper_out_func[ot], cpu_tmp2_i32, cpu_tmp3_i32); + gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32); + if (use_icount) { + gen_io_end(); + gen_jmp(s, s->pc - s->cs_base); + } break; case 0xec: case 0xed: @@ -5459,9 +6102,15 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) gen_op_andl_T0_ffff(); gen_check_io(s, ot, pc_start - s->cs_base, SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes)); + if (use_icount) + gen_io_start(); tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); - tcg_gen_helper_1_1(helper_in_func[ot], cpu_T[1], cpu_tmp2_i32); + gen_helper_in_func(ot, cpu_T[1], cpu_tmp2_i32); gen_op_mov_reg_T1(ot, R_EAX); + if (use_icount) { + gen_io_end(); + gen_jmp(s, s->pc - s->cs_base); + } break; case 0xee: case 0xef: @@ -5475,10 +6124,16 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) svm_is_rep(prefixes)); gen_op_mov_TN_reg(ot, 1, R_EAX); + if (use_icount) + gen_io_start(); tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff); tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[1]); - tcg_gen_helper_0_2(helper_out_func[ot], cpu_tmp2_i32, cpu_tmp3_i32); + gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32); + if (use_icount) { + gen_io_end(); + gen_jmp(s, s->pc - s->cs_base); + } break; /************************/ @@ -5511,9 +6166,8 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) if (s->cc_op != CC_OP_DYNAMIC) gen_op_set_cc_op(s->cc_op); gen_jmp_im(pc_start - s->cs_base); - tcg_gen_helper_0_2(helper_lret_protected, - tcg_const_i32(s->dflag), - tcg_const_i32(val)); + gen_helper_lret_protected(tcg_const_i32(s->dflag), + tcg_const_i32(val)); } else { gen_stack_A0(s); /* pop offset */ @@ -5526,7 +6180,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) /* pop selector */ gen_op_addl_A0_im(2 << s->dflag); gen_op_ld_T0_A0(1 + s->dflag + s->mem_index); - gen_op_movl_seg_T0_vm(offsetof(CPUX86State,segs[R_CS])); + gen_op_movl_seg_T0_vm(R_CS); /* add stack offset */ gen_stack_update(s, val + (4 << s->dflag)); } @@ -5536,26 +6190,24 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) val = 0; goto do_lret; case 0xcf: /* iret */ - if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_IRET)) - break; + gen_svm_check_intercept(s, pc_start, SVM_EXIT_IRET); if (!s->pe) { /* real mode */ - tcg_gen_helper_0_1(helper_iret_real, tcg_const_i32(s->dflag)); + gen_helper_iret_real(tcg_const_i32(s->dflag)); s->cc_op = CC_OP_EFLAGS; } else if (s->vm86) { if (s->iopl != 3) { gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); } else { - tcg_gen_helper_0_1(helper_iret_real, tcg_const_i32(s->dflag)); + gen_helper_iret_real(tcg_const_i32(s->dflag)); s->cc_op = CC_OP_EFLAGS; } } else { if (s->cc_op != CC_OP_DYNAMIC) gen_op_set_cc_op(s->cc_op); gen_jmp_im(pc_start - s->cs_base); - tcg_gen_helper_0_2(helper_iret_protected, - tcg_const_i32(s->dflag), - tcg_const_i32(s->pc - s->cs_base)); + gen_helper_iret_protected(tcg_const_i32(s->dflag), + tcg_const_i32(s->pc - s->cs_base)); s->cc_op = CC_OP_EFLAGS; } gen_eob(s); @@ -5597,6 +6249,8 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) tval += s->pc - s->cs_base; if (s->dflag == 0) tval &= 0xffff; + else if(!CODE64(s)) + tval &= 0xffffffff; gen_jmp(s, tval); break; case 0xea: /* ljmp im */ @@ -5643,60 +6297,86 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) gen_ldst_modrm(s, modrm, OT_BYTE, OR_TMP0, 1); break; case 0x140 ... 0x14f: /* cmov Gv, Ev */ - ot = dflag + OT_WORD; - modrm = ldub_code(s->pc++); - reg = ((modrm >> 3) & 7) | rex_r; - mod = (modrm >> 6) & 3; - gen_setcc(s, b); - if (mod != 3) { - gen_lea_modrm(s, modrm, ®_addr, &offset_addr); - gen_op_ld_T1_A0(ot + s->mem_index); - } else { - rm = (modrm & 7) | REX_B(s); - gen_op_mov_TN_reg(ot, 1, rm); + { + int l1; + TCGv t0; + + ot = dflag + OT_WORD; + modrm = ldub_code(s->pc++); + reg = ((modrm >> 3) & 7) | rex_r; + mod = (modrm >> 6) & 3; + t0 = tcg_temp_local_new(); + if (mod != 3) { + gen_lea_modrm(s, modrm, ®_addr, &offset_addr); + gen_op_ld_v(ot + s->mem_index, t0, cpu_A0); + } else { + rm = (modrm & 7) | REX_B(s); + gen_op_mov_v_reg(ot, t0, rm); + } +#ifdef TARGET_X86_64 + if (ot == OT_LONG) { + /* XXX: specific Intel behaviour ? */ + l1 = gen_new_label(); + gen_jcc1(s, s->cc_op, b ^ 1, l1); + tcg_gen_st32_tl(t0, cpu_env, offsetof(CPUState, regs[reg]) + REG_L_OFFSET); + gen_set_label(l1); + tcg_gen_movi_tl(cpu_tmp0, 0); + tcg_gen_st32_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]) + REG_LH_OFFSET); + } else +#endif + { + l1 = gen_new_label(); + gen_jcc1(s, s->cc_op, b ^ 1, l1); + gen_op_mov_reg_v(ot, reg, t0); + gen_set_label(l1); + } + tcg_temp_free(t0); } - gen_op_cmov_reg_T1_T0[ot - OT_WORD][reg](); break; /************************/ /* flags */ case 0x9c: /* pushf */ - if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_PUSHF)) - break; + gen_svm_check_intercept(s, pc_start, SVM_EXIT_PUSHF); if (s->vm86 && s->iopl != 3) { gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); } else { if (s->cc_op != CC_OP_DYNAMIC) gen_op_set_cc_op(s->cc_op); - gen_op_movl_T0_eflags(); + gen_helper_read_eflags(cpu_T[0]); gen_push_T0(s); } break; case 0x9d: /* popf */ - if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_POPF)) - break; + gen_svm_check_intercept(s, pc_start, SVM_EXIT_POPF); if (s->vm86 && s->iopl != 3) { gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); } else { gen_pop_T0(s); if (s->cpl == 0) { if (s->dflag) { - gen_op_movl_eflags_T0_cpl0(); + gen_helper_write_eflags(cpu_T[0], + tcg_const_i32((TF_MASK | AC_MASK | ID_MASK | NT_MASK | IF_MASK | IOPL_MASK))); } else { - gen_op_movw_eflags_T0_cpl0(); + gen_helper_write_eflags(cpu_T[0], + tcg_const_i32((TF_MASK | AC_MASK | ID_MASK | NT_MASK | IF_MASK | IOPL_MASK) & 0xffff)); } } else { if (s->cpl <= s->iopl) { if (s->dflag) { - gen_op_movl_eflags_T0_io(); + gen_helper_write_eflags(cpu_T[0], + tcg_const_i32((TF_MASK | AC_MASK | ID_MASK | NT_MASK | IF_MASK))); } else { - gen_op_movw_eflags_T0_io(); + gen_helper_write_eflags(cpu_T[0], + tcg_const_i32((TF_MASK | AC_MASK | ID_MASK | NT_MASK | IF_MASK) & 0xffff)); } } else { if (s->dflag) { - gen_op_movl_eflags_T0(); + gen_helper_write_eflags(cpu_T[0], + tcg_const_i32((TF_MASK | AC_MASK | ID_MASK | NT_MASK))); } else { - gen_op_movw_eflags_T0(); + gen_helper_write_eflags(cpu_T[0], + tcg_const_i32((TF_MASK | AC_MASK | ID_MASK | NT_MASK) & 0xffff)); } } } @@ -5708,38 +6388,46 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) } break; case 0x9e: /* sahf */ - if (CODE64(s)) + if (CODE64(s) && !(s->cpuid_ext3_features & CPUID_EXT3_LAHF_LM)) goto illegal_op; gen_op_mov_TN_reg(OT_BYTE, 0, R_AH); if (s->cc_op != CC_OP_DYNAMIC) gen_op_set_cc_op(s->cc_op); - gen_op_movb_eflags_T0(); + gen_compute_eflags(cpu_cc_src); + tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, CC_O); + tcg_gen_andi_tl(cpu_T[0], cpu_T[0], CC_S | CC_Z | CC_A | CC_P | CC_C); + tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_T[0]); s->cc_op = CC_OP_EFLAGS; break; case 0x9f: /* lahf */ - if (CODE64(s)) + if (CODE64(s) && !(s->cpuid_ext3_features & CPUID_EXT3_LAHF_LM)) goto illegal_op; if (s->cc_op != CC_OP_DYNAMIC) gen_op_set_cc_op(s->cc_op); - gen_op_movl_T0_eflags(); + gen_compute_eflags(cpu_T[0]); + /* Note: gen_compute_eflags() only gives the condition codes */ + tcg_gen_ori_tl(cpu_T[0], cpu_T[0], 0x02); gen_op_mov_reg_T0(OT_BYTE, R_AH); break; case 0xf5: /* cmc */ if (s->cc_op != CC_OP_DYNAMIC) gen_op_set_cc_op(s->cc_op); - gen_op_cmc(); + gen_compute_eflags(cpu_cc_src); + tcg_gen_xori_tl(cpu_cc_src, cpu_cc_src, CC_C); s->cc_op = CC_OP_EFLAGS; break; case 0xf8: /* clc */ if (s->cc_op != CC_OP_DYNAMIC) gen_op_set_cc_op(s->cc_op); - gen_op_clc(); + gen_compute_eflags(cpu_cc_src); + tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~CC_C); s->cc_op = CC_OP_EFLAGS; break; case 0xf9: /* stc */ if (s->cc_op != CC_OP_DYNAMIC) gen_op_set_cc_op(s->cc_op); - gen_op_stc(); + gen_compute_eflags(cpu_cc_src); + tcg_gen_ori_tl(cpu_cc_src, cpu_cc_src, CC_C); s->cc_op = CC_OP_EFLAGS; break; case 0xfc: /* cld */ @@ -5844,6 +6532,8 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) case 0x1bd: /* bsr */ { int label1; + TCGv t0; + ot = dflag + OT_WORD; modrm = ldub_code(s->pc++); reg = ((modrm >> 3) & 7) | rex_r; @@ -5851,17 +6541,20 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) gen_extu(ot, cpu_T[0]); label1 = gen_new_label(); tcg_gen_movi_tl(cpu_cc_dst, 0); - tcg_gen_brcond_tl(TCG_COND_EQ, cpu_T[0], tcg_const_tl(0), label1); + t0 = tcg_temp_local_new(); + tcg_gen_mov_tl(t0, cpu_T[0]); + tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, label1); if (b & 1) { - tcg_gen_helper_1_1(helper_bsr, cpu_T[0], cpu_T[0]); + gen_helper_bsr(cpu_T[0], t0); } else { - tcg_gen_helper_1_1(helper_bsf, cpu_T[0], cpu_T[0]); + gen_helper_bsf(cpu_T[0], t0); } gen_op_mov_reg_T0(ot, reg); tcg_gen_movi_tl(cpu_cc_dst, 1); gen_set_label(label1); tcg_gen_discard_tl(cpu_cc_src); s->cc_op = CC_OP_LOGICB + ot; + tcg_temp_free(t0); } break; /************************/ @@ -5871,7 +6564,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) goto illegal_op; if (s->cc_op != CC_OP_DYNAMIC) gen_op_set_cc_op(s->cc_op); - gen_op_daa(); + gen_helper_daa(); s->cc_op = CC_OP_EFLAGS; break; case 0x2f: /* das */ @@ -5879,7 +6572,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) goto illegal_op; if (s->cc_op != CC_OP_DYNAMIC) gen_op_set_cc_op(s->cc_op); - gen_op_das(); + gen_helper_das(); s->cc_op = CC_OP_EFLAGS; break; case 0x37: /* aaa */ @@ -5887,7 +6580,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) goto illegal_op; if (s->cc_op != CC_OP_DYNAMIC) gen_op_set_cc_op(s->cc_op); - gen_op_aaa(); + gen_helper_aaa(); s->cc_op = CC_OP_EFLAGS; break; case 0x3f: /* aas */ @@ -5895,7 +6588,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) goto illegal_op; if (s->cc_op != CC_OP_DYNAMIC) gen_op_set_cc_op(s->cc_op); - gen_op_aas(); + gen_helper_aas(); s->cc_op = CC_OP_EFLAGS; break; case 0xd4: /* aam */ @@ -5905,7 +6598,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) if (val == 0) { gen_exception(s, EXCP00_DIVZ, pc_start - s->cs_base); } else { - gen_op_aam(val); + gen_helper_aam(tcg_const_i32(val)); s->cc_op = CC_OP_LOGICB; } break; @@ -5913,7 +6606,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) if (CODE64(s)) goto illegal_op; val = ldub_code(s->pc++); - gen_op_aad(val); + gen_helper_aad(tcg_const_i32(val)); s->cc_op = CC_OP_LOGICB; break; /************************/ @@ -5935,18 +6628,14 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) if (s->cc_op != CC_OP_DYNAMIC) gen_op_set_cc_op(s->cc_op); gen_jmp_im(pc_start - s->cs_base); - tcg_gen_helper_0_0(helper_fwait); + gen_helper_fwait(); } break; case 0xcc: /* int3 */ - if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_SWINT)) - break; gen_interrupt(s, EXCP03_INT3, pc_start - s->cs_base, s->pc - s->cs_base); break; case 0xcd: /* int N */ val = ldub_code(s->pc++); - if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_SWINT)) - break; if (s->vm86 && s->iopl != 3) { gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); } else { @@ -5956,16 +6645,14 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) case 0xce: /* into */ if (CODE64(s)) goto illegal_op; - if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_SWINT)) - break; if (s->cc_op != CC_OP_DYNAMIC) gen_op_set_cc_op(s->cc_op); gen_jmp_im(pc_start - s->cs_base); - gen_op_into(s->pc - pc_start); + gen_helper_into(tcg_const_i32(s->pc - pc_start)); break; +#ifdef WANT_ICEBP case 0xf1: /* icebp (undocumented, exits to external debugger) */ - if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_ICEBP)) - break; + gen_svm_check_intercept(s, pc_start, SVM_EXIT_ICEBP); #if 1 gen_debug(s, pc_start - s->cs_base); #else @@ -5974,16 +6661,17 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) cpu_set_log(CPU_LOG_INT | CPU_LOG_TB_IN_ASM); #endif break; +#endif case 0xfa: /* cli */ if (!s->vm86) { if (s->cpl <= s->iopl) { - tcg_gen_helper_0_0(helper_cli); + gen_helper_cli(); } else { gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); } } else { if (s->iopl == 3) { - tcg_gen_helper_0_0(helper_cli); + gen_helper_cli(); } else { gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); } @@ -5993,12 +6681,12 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) if (!s->vm86) { if (s->cpl <= s->iopl) { gen_sti: - tcg_gen_helper_0_0(helper_sti); + gen_helper_sti(); /* interruptions are enabled only the first insn after sti */ /* If several instructions disable interrupts, only the _first_ does it */ if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK)) - tcg_gen_helper_0_0(helper_set_inhibit_irq); + gen_helper_set_inhibit_irq(); /* give a chance to handle pending irqs */ gen_jmp_im(s->pc - s->cs_base); gen_eob(s); @@ -6027,52 +6715,41 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) gen_jmp_im(pc_start - s->cs_base); tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); if (ot == OT_WORD) - tcg_gen_helper_0_2(helper_boundw, cpu_A0, cpu_tmp2_i32); + gen_helper_boundw(cpu_A0, cpu_tmp2_i32); else - tcg_gen_helper_0_2(helper_boundl, cpu_A0, cpu_tmp2_i32); + gen_helper_boundl(cpu_A0, cpu_tmp2_i32); break; case 0x1c8 ... 0x1cf: /* bswap reg */ reg = (b & 7) | REX_B(s); #ifdef TARGET_X86_64 if (dflag == 2) { gen_op_mov_TN_reg(OT_QUAD, 0, reg); - tcg_gen_bswap_i64(cpu_T[0], cpu_T[0]); + tcg_gen_bswap64_i64(cpu_T[0], cpu_T[0]); gen_op_mov_reg_T0(OT_QUAD, reg); } else - { - TCGv tmp0; - gen_op_mov_TN_reg(OT_LONG, 0, reg); - - tmp0 = tcg_temp_new(TCG_TYPE_I32); - tcg_gen_trunc_i64_i32(tmp0, cpu_T[0]); - tcg_gen_bswap_i32(tmp0, tmp0); - tcg_gen_extu_i32_i64(cpu_T[0], tmp0); - gen_op_mov_reg_T0(OT_LONG, reg); - } -#else +#endif { gen_op_mov_TN_reg(OT_LONG, 0, reg); - tcg_gen_bswap_i32(cpu_T[0], cpu_T[0]); + tcg_gen_ext32u_tl(cpu_T[0], cpu_T[0]); + tcg_gen_bswap32_tl(cpu_T[0], cpu_T[0]); gen_op_mov_reg_T0(OT_LONG, reg); } -#endif break; case 0xd6: /* salc */ if (CODE64(s)) goto illegal_op; if (s->cc_op != CC_OP_DYNAMIC) gen_op_set_cc_op(s->cc_op); - gen_op_salc(); + gen_compute_eflags_c(cpu_T[0]); + tcg_gen_neg_tl(cpu_T[0], cpu_T[0]); + gen_op_mov_reg_T0(OT_BYTE, R_EAX); break; case 0xe0: /* loopnz */ case 0xe1: /* loopz */ - if (s->cc_op != CC_OP_DYNAMIC) - gen_op_set_cc_op(s->cc_op); - /* FALL THRU */ case 0xe2: /* loop */ case 0xe3: /* jecxz */ { - int l1, l2; + int l1, l2, l3; tval = (int8_t)insn_get(s, OT_BYTE); next_eip = s->pc - s->cs_base; @@ -6082,18 +6759,37 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) l1 = gen_new_label(); l2 = gen_new_label(); + l3 = gen_new_label(); b &= 3; - if (b == 3) { - gen_op_jz_ecx[s->aflag](l1); - } else { - gen_op_dec_ECX[s->aflag](); - if (b <= 1) - gen_op_mov_T0_cc(); - gen_op_loop[s->aflag][b](l1); + switch(b) { + case 0: /* loopnz */ + case 1: /* loopz */ + if (s->cc_op != CC_OP_DYNAMIC) + gen_op_set_cc_op(s->cc_op); + gen_op_add_reg_im(s->aflag, R_ECX, -1); + gen_op_jz_ecx(s->aflag, l3); + gen_compute_eflags(cpu_tmp0); + tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, CC_Z); + if (b == 0) { + tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, l1); + } else { + tcg_gen_brcondi_tl(TCG_COND_NE, cpu_tmp0, 0, l1); + } + break; + case 2: /* loop */ + gen_op_add_reg_im(s->aflag, R_ECX, -1); + gen_op_jnz_ecx(s->aflag, l1); + break; + default: + case 3: /* jcxz */ + gen_op_jz_ecx(s->aflag, l1); + break; } + gen_set_label(l3); gen_jmp_im(next_eip); - gen_op_jmp_label(l2); + tcg_gen_br(l2); + gen_set_label(l1); gen_jmp_im(tval); gen_set_label(l2); @@ -6105,30 +6801,37 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) if (s->cpl != 0) { gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); } else { - int retval = 0; + if (s->cc_op != CC_OP_DYNAMIC) + gen_op_set_cc_op(s->cc_op); + gen_jmp_im(pc_start - s->cs_base); if (b & 2) { - retval = gen_svm_check_intercept_param(s, pc_start, SVM_EXIT_MSR, 0); - tcg_gen_helper_0_0(helper_rdmsr); + gen_helper_rdmsr(); } else { - retval = gen_svm_check_intercept_param(s, pc_start, SVM_EXIT_MSR, 1); - tcg_gen_helper_0_0(helper_wrmsr); + gen_helper_wrmsr(); } - if(retval) - gen_eob(s); } break; case 0x131: /* rdtsc */ - if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_RDTSC)) - break; + if (s->cc_op != CC_OP_DYNAMIC) + gen_op_set_cc_op(s->cc_op); gen_jmp_im(pc_start - s->cs_base); - tcg_gen_helper_0_0(helper_rdtsc); + if (use_icount) + gen_io_start(); + gen_helper_rdtsc(); + if (use_icount) { + gen_io_end(); + gen_jmp(s, s->pc - s->cs_base); + } break; case 0x133: /* rdpmc */ + if (s->cc_op != CC_OP_DYNAMIC) + gen_op_set_cc_op(s->cc_op); gen_jmp_im(pc_start - s->cs_base); - tcg_gen_helper_0_0(helper_rdpmc); + gen_helper_rdpmc(); break; case 0x134: /* sysenter */ - if (CODE64(s)) + /* For Intel SYSENTER is valid on 64-bit */ + if (CODE64(s) && cpu_single_env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1) goto illegal_op; if (!s->pe) { gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); @@ -6138,12 +6841,13 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) s->cc_op = CC_OP_DYNAMIC; } gen_jmp_im(pc_start - s->cs_base); - tcg_gen_helper_0_0(helper_sysenter); + gen_helper_sysenter(); gen_eob(s); } break; case 0x135: /* sysexit */ - if (CODE64(s)) + /* For Intel SYSEXIT is valid on 64-bit */ + if (CODE64(s) && cpu_single_env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1) goto illegal_op; if (!s->pe) { gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); @@ -6153,7 +6857,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) s->cc_op = CC_OP_DYNAMIC; } gen_jmp_im(pc_start - s->cs_base); - tcg_gen_helper_0_0(helper_sysexit); + gen_helper_sysexit(tcg_const_i32(dflag)); gen_eob(s); } break; @@ -6165,7 +6869,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) s->cc_op = CC_OP_DYNAMIC; } gen_jmp_im(pc_start - s->cs_base); - tcg_gen_helper_0_1(helper_syscall, tcg_const_i32(s->pc - pc_start)); + gen_helper_syscall(tcg_const_i32(s->pc - pc_start)); gen_eob(s); break; case 0x107: /* sysret */ @@ -6177,7 +6881,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) s->cc_op = CC_OP_DYNAMIC; } gen_jmp_im(pc_start - s->cs_base); - tcg_gen_helper_0_1(helper_sysret, tcg_const_i32(s->dflag)); + gen_helper_sysret(tcg_const_i32(s->dflag)); /* condition codes are modified only in long mode */ if (s->lma) s->cc_op = CC_OP_EFLAGS; @@ -6186,20 +6890,19 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) break; #endif case 0x1a2: /* cpuid */ - if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_CPUID)) - break; - tcg_gen_helper_0_0(helper_cpuid); + if (s->cc_op != CC_OP_DYNAMIC) + gen_op_set_cc_op(s->cc_op); + gen_jmp_im(pc_start - s->cs_base); + gen_helper_cpuid(); break; case 0xf4: /* hlt */ if (s->cpl != 0) { gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); } else { - if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_HLT)) - break; if (s->cc_op != CC_OP_DYNAMIC) gen_op_set_cc_op(s->cc_op); - gen_jmp_im(s->pc - s->cs_base); - tcg_gen_helper_0_0(helper_hlt); + gen_jmp_im(pc_start - s->cs_base); + gen_helper_hlt(tcg_const_i32(s->pc - pc_start)); s->is_jmp = 3; } break; @@ -6211,9 +6914,8 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) case 0: /* sldt */ if (!s->pe || s->vm86) goto illegal_op; - if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_LDTR_READ)) - break; - gen_op_movl_T0_env(offsetof(CPUX86State,ldt.selector)); + gen_svm_check_intercept(s, pc_start, SVM_EXIT_LDTR_READ); + tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,ldt.selector)); ot = OT_WORD; if (mod == 3) ot += s->dflag; @@ -6225,20 +6927,18 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) if (s->cpl != 0) { gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); } else { - if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_LDTR_WRITE)) - break; + gen_svm_check_intercept(s, pc_start, SVM_EXIT_LDTR_WRITE); gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0); gen_jmp_im(pc_start - s->cs_base); tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); - tcg_gen_helper_0_1(helper_lldt, cpu_tmp2_i32); + gen_helper_lldt(cpu_tmp2_i32); } break; case 1: /* str */ if (!s->pe || s->vm86) goto illegal_op; - if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_TR_READ)) - break; - gen_op_movl_T0_env(offsetof(CPUX86State,tr.selector)); + gen_svm_check_intercept(s, pc_start, SVM_EXIT_TR_READ); + tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,tr.selector)); ot = OT_WORD; if (mod == 3) ot += s->dflag; @@ -6250,12 +6950,11 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) if (s->cpl != 0) { gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); } else { - if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_TR_WRITE)) - break; + gen_svm_check_intercept(s, pc_start, SVM_EXIT_TR_WRITE); gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0); gen_jmp_im(pc_start - s->cs_base); tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); - tcg_gen_helper_0_1(helper_ltr, cpu_tmp2_i32); + gen_helper_ltr(cpu_tmp2_i32); } break; case 4: /* verr */ @@ -6266,9 +6965,9 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) if (s->cc_op != CC_OP_DYNAMIC) gen_op_set_cc_op(s->cc_op); if (op == 4) - gen_op_verr(); + gen_helper_verr(cpu_T[0]); else - gen_op_verw(); + gen_helper_verw(cpu_T[0]); s->cc_op = CC_OP_EFLAGS; break; default: @@ -6284,13 +6983,12 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) case 0: /* sgdt */ if (mod == 3) goto illegal_op; - if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_GDTR_READ)) - break; + gen_svm_check_intercept(s, pc_start, SVM_EXIT_GDTR_READ); gen_lea_modrm(s, modrm, ®_addr, &offset_addr); - gen_op_movl_T0_env(offsetof(CPUX86State, gdt.limit)); + tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, gdt.limit)); gen_op_st_T0_A0(OT_WORD + s->mem_index); gen_add_A0_im(s, 2); - gen_op_movtl_T0_env(offsetof(CPUX86State, gdt.base)); + tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, gdt.base)); if (!s->dflag) gen_op_andl_T0_im(0xffffff); gen_op_st_T0_A0(CODE64(s) + OT_LONG + s->mem_index); @@ -6302,8 +7000,8 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) if (!(s->cpuid_ext_features & CPUID_EXT_MONITOR) || s->cpl != 0) goto illegal_op; - if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_MONITOR)) - break; + if (s->cc_op != CC_OP_DYNAMIC) + gen_op_set_cc_op(s->cc_op); gen_jmp_im(pc_start - s->cs_base); #ifdef TARGET_X86_64 if (s->aflag == 2) { @@ -6316,7 +7014,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) gen_op_andl_A0_ffff(); } gen_add_A0_ds_seg(s); - tcg_gen_helper_0_1(helper_monitor, cpu_A0); + gen_helper_monitor(cpu_A0); break; case 1: /* mwait */ if (!(s->cpuid_ext_features & CPUID_EXT_MONITOR) || @@ -6326,23 +7024,20 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) gen_op_set_cc_op(s->cc_op); s->cc_op = CC_OP_DYNAMIC; } - if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_MWAIT)) - break; - gen_jmp_im(s->pc - s->cs_base); - tcg_gen_helper_0_0(helper_mwait); + gen_jmp_im(pc_start - s->cs_base); + gen_helper_mwait(tcg_const_i32(s->pc - pc_start)); gen_eob(s); break; default: goto illegal_op; } } else { /* sidt */ - if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_IDTR_READ)) - break; + gen_svm_check_intercept(s, pc_start, SVM_EXIT_IDTR_READ); gen_lea_modrm(s, modrm, ®_addr, &offset_addr); - gen_op_movl_T0_env(offsetof(CPUX86State, idt.limit)); + tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, idt.limit)); gen_op_st_T0_A0(OT_WORD + s->mem_index); gen_add_A0_im(s, 2); - gen_op_movtl_T0_env(offsetof(CPUX86State, idt.base)); + tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, idt.base)); if (!s->dflag) gen_op_andl_T0_im(0xffffff); gen_op_st_T0_A0(CODE64(s) + OT_LONG + s->mem_index); @@ -6351,52 +7046,86 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) case 2: /* lgdt */ case 3: /* lidt */ if (mod == 3) { + if (s->cc_op != CC_OP_DYNAMIC) + gen_op_set_cc_op(s->cc_op); + gen_jmp_im(pc_start - s->cs_base); switch(rm) { case 0: /* VMRUN */ - if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_VMRUN)) + if (!(s->flags & HF_SVME_MASK) || !s->pe) + goto illegal_op; + if (s->cpl != 0) { + gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); break; - if (s->cc_op != CC_OP_DYNAMIC) - gen_op_set_cc_op(s->cc_op); - gen_jmp_im(s->pc - s->cs_base); - tcg_gen_helper_0_0(helper_vmrun); - s->cc_op = CC_OP_EFLAGS; - gen_eob(s); + } else { + gen_helper_vmrun(tcg_const_i32(s->aflag), + tcg_const_i32(s->pc - pc_start)); + tcg_gen_exit_tb(0); + s->is_jmp = 3; + } break; case 1: /* VMMCALL */ - if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_VMMCALL)) - break; - /* FIXME: cause #UD if hflags & SVM */ - tcg_gen_helper_0_0(helper_vmmcall); + if (!(s->flags & HF_SVME_MASK)) + goto illegal_op; + gen_helper_vmmcall(); break; case 2: /* VMLOAD */ - if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_VMLOAD)) - break; - tcg_gen_helper_0_0(helper_vmload); + if (!(s->flags & HF_SVME_MASK) || !s->pe) + goto illegal_op; + if (s->cpl != 0) { + gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); + break; + } else { + gen_helper_vmload(tcg_const_i32(s->aflag)); + } break; case 3: /* VMSAVE */ - if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_VMSAVE)) - break; - tcg_gen_helper_0_0(helper_vmsave); + if (!(s->flags & HF_SVME_MASK) || !s->pe) + goto illegal_op; + if (s->cpl != 0) { + gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); + break; + } else { + gen_helper_vmsave(tcg_const_i32(s->aflag)); + } break; case 4: /* STGI */ - if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_STGI)) - break; - tcg_gen_helper_0_0(helper_stgi); + if ((!(s->flags & HF_SVME_MASK) && + !(s->cpuid_ext3_features & CPUID_EXT3_SKINIT)) || + !s->pe) + goto illegal_op; + if (s->cpl != 0) { + gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); + break; + } else { + gen_helper_stgi(); + } break; case 5: /* CLGI */ - if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_CLGI)) - break; - tcg_gen_helper_0_0(helper_clgi); + if (!(s->flags & HF_SVME_MASK) || !s->pe) + goto illegal_op; + if (s->cpl != 0) { + gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); + break; + } else { + gen_helper_clgi(); + } break; case 6: /* SKINIT */ - if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_SKINIT)) - break; - tcg_gen_helper_0_0(helper_skinit); + if ((!(s->flags & HF_SVME_MASK) && + !(s->cpuid_ext3_features & CPUID_EXT3_SKINIT)) || + !s->pe) + goto illegal_op; + gen_helper_skinit(); break; case 7: /* INVLPGA */ - if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_INVLPGA)) - break; - tcg_gen_helper_0_0(helper_invlpga); + if (!(s->flags & HF_SVME_MASK) || !s->pe) + goto illegal_op; + if (s->cpl != 0) { + gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); + break; + } else { + gen_helper_invlpga(tcg_const_i32(s->aflag)); + } break; default: goto illegal_op; @@ -6404,9 +7133,8 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) } else if (s->cpl != 0) { gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); } else { - if (gen_svm_check_intercept(s, pc_start, - op==2 ? SVM_EXIT_GDTR_WRITE : SVM_EXIT_IDTR_WRITE)) - break; + gen_svm_check_intercept(s, pc_start, + op==2 ? SVM_EXIT_GDTR_WRITE : SVM_EXIT_IDTR_WRITE); gen_lea_modrm(s, modrm, ®_addr, &offset_addr); gen_op_ld_T1_A0(OT_WORD + s->mem_index); gen_add_A0_im(s, 2); @@ -6414,28 +7142,30 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) if (!s->dflag) gen_op_andl_T0_im(0xffffff); if (op == 2) { - gen_op_movtl_env_T0(offsetof(CPUX86State,gdt.base)); - gen_op_movl_env_T1(offsetof(CPUX86State,gdt.limit)); + tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,gdt.base)); + tcg_gen_st32_tl(cpu_T[1], cpu_env, offsetof(CPUX86State,gdt.limit)); } else { - gen_op_movtl_env_T0(offsetof(CPUX86State,idt.base)); - gen_op_movl_env_T1(offsetof(CPUX86State,idt.limit)); + tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,idt.base)); + tcg_gen_st32_tl(cpu_T[1], cpu_env, offsetof(CPUX86State,idt.limit)); } } break; case 4: /* smsw */ - if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_READ_CR0)) - break; - gen_op_movl_T0_env(offsetof(CPUX86State,cr[0])); + gen_svm_check_intercept(s, pc_start, SVM_EXIT_READ_CR0); +#if defined TARGET_X86_64 && defined WORDS_BIGENDIAN + tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,cr[0]) + 4); +#else + tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,cr[0])); +#endif gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 1); break; case 6: /* lmsw */ if (s->cpl != 0) { gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); } else { - if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_CR0)) - break; + gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_CR0); gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0); - tcg_gen_helper_0_1(helper_lmsw, cpu_T[0]); + gen_helper_lmsw(cpu_T[0]); gen_jmp_im(s->pc - s->cs_base); gen_eob(s); } @@ -6448,20 +7178,21 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) #ifdef TARGET_X86_64 if (CODE64(s) && rm == 0) { /* swapgs */ - gen_op_movtl_T0_env(offsetof(CPUX86State,segs[R_GS].base)); - gen_op_movtl_T1_env(offsetof(CPUX86State,kernelgsbase)); - gen_op_movtl_env_T1(offsetof(CPUX86State,segs[R_GS].base)); - gen_op_movtl_env_T0(offsetof(CPUX86State,kernelgsbase)); + tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,segs[R_GS].base)); + tcg_gen_ld_tl(cpu_T[1], cpu_env, offsetof(CPUX86State,kernelgsbase)); + tcg_gen_st_tl(cpu_T[1], cpu_env, offsetof(CPUX86State,segs[R_GS].base)); + tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,kernelgsbase)); } else #endif { goto illegal_op; } } else { - if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_INVLPG)) - break; + if (s->cc_op != CC_OP_DYNAMIC) + gen_op_set_cc_op(s->cc_op); + gen_jmp_im(pc_start - s->cs_base); gen_lea_modrm(s, modrm, ®_addr, &offset_addr); - tcg_gen_helper_0_1(helper_invlpg, cpu_A0); + gen_helper_invlpg(cpu_A0); gen_jmp_im(s->pc - s->cs_base); gen_eob(s); } @@ -6476,8 +7207,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) if (s->cpl != 0) { gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); } else { - if (gen_svm_check_intercept(s, pc_start, (b & 2) ? SVM_EXIT_INVD : SVM_EXIT_WBINVD)) - break; + gen_svm_check_intercept(s, pc_start, (b & 2) ? SVM_EXIT_INVD : SVM_EXIT_WBINVD); /* nothing to do */ } break; @@ -6511,49 +7241,77 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) } else #endif { + int label1; + TCGv t0, t1, t2; + if (!s->pe || s->vm86) goto illegal_op; - ot = dflag ? OT_LONG : OT_WORD; + t0 = tcg_temp_local_new(); + t1 = tcg_temp_local_new(); + t2 = tcg_temp_local_new(); + ot = OT_WORD; modrm = ldub_code(s->pc++); reg = (modrm >> 3) & 7; mod = (modrm >> 6) & 3; rm = modrm & 7; if (mod != 3) { gen_lea_modrm(s, modrm, ®_addr, &offset_addr); - gen_op_ld_T0_A0(ot + s->mem_index); + gen_op_ld_v(ot + s->mem_index, t0, cpu_A0); } else { - gen_op_mov_TN_reg(ot, 0, rm); + gen_op_mov_v_reg(ot, t0, rm); } - gen_op_mov_TN_reg(ot, 1, reg); - if (s->cc_op != CC_OP_DYNAMIC) - gen_op_set_cc_op(s->cc_op); - gen_op_arpl(); - s->cc_op = CC_OP_EFLAGS; + gen_op_mov_v_reg(ot, t1, reg); + tcg_gen_andi_tl(cpu_tmp0, t0, 3); + tcg_gen_andi_tl(t1, t1, 3); + tcg_gen_movi_tl(t2, 0); + label1 = gen_new_label(); + tcg_gen_brcond_tl(TCG_COND_GE, cpu_tmp0, t1, label1); + tcg_gen_andi_tl(t0, t0, ~3); + tcg_gen_or_tl(t0, t0, t1); + tcg_gen_movi_tl(t2, CC_Z); + gen_set_label(label1); if (mod != 3) { - gen_op_st_T0_A0(ot + s->mem_index); + gen_op_st_v(ot + s->mem_index, t0, cpu_A0); } else { - gen_op_mov_reg_T0(ot, rm); + gen_op_mov_reg_v(ot, rm, t0); } - gen_op_arpl_update(); + if (s->cc_op != CC_OP_DYNAMIC) + gen_op_set_cc_op(s->cc_op); + gen_compute_eflags(cpu_cc_src); + tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~CC_Z); + tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, t2); + s->cc_op = CC_OP_EFLAGS; + tcg_temp_free(t0); + tcg_temp_free(t1); + tcg_temp_free(t2); } break; case 0x102: /* lar */ case 0x103: /* lsl */ - if (!s->pe || s->vm86) - goto illegal_op; - ot = dflag ? OT_LONG : OT_WORD; - modrm = ldub_code(s->pc++); - reg = ((modrm >> 3) & 7) | rex_r; - gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0); - gen_op_mov_TN_reg(ot, 1, reg); - if (s->cc_op != CC_OP_DYNAMIC) - gen_op_set_cc_op(s->cc_op); - if (b == 0x102) - gen_op_lar(); - else - gen_op_lsl(); - s->cc_op = CC_OP_EFLAGS; - gen_op_mov_reg_T1(ot, reg); + { + int label1; + TCGv t0; + if (!s->pe || s->vm86) + goto illegal_op; + ot = dflag ? OT_LONG : OT_WORD; + modrm = ldub_code(s->pc++); + reg = ((modrm >> 3) & 7) | rex_r; + gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0); + t0 = tcg_temp_local_new(); + if (s->cc_op != CC_OP_DYNAMIC) + gen_op_set_cc_op(s->cc_op); + if (b == 0x102) + gen_helper_lar(t0, cpu_T[0]); + else + gen_helper_lsl(t0, cpu_T[0]); + tcg_gen_andi_tl(cpu_tmp0, cpu_cc_src, CC_Z); + label1 = gen_new_label(); + tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, label1); + gen_op_mov_reg_v(ot, reg, t0); + gen_set_label(label1); + s->cc_op = CC_OP_EFLAGS; + tcg_temp_free(t0); + } break; case 0x118: modrm = ldub_code(s->pc++); @@ -6598,21 +7356,16 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) case 3: case 4: case 8: + if (s->cc_op != CC_OP_DYNAMIC) + gen_op_set_cc_op(s->cc_op); + gen_jmp_im(pc_start - s->cs_base); if (b & 2) { - gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_CR0 + reg); gen_op_mov_TN_reg(ot, 0, rm); - tcg_gen_helper_0_2(helper_movl_crN_T0, - tcg_const_i32(reg), cpu_T[0]); + gen_helper_write_crN(tcg_const_i32(reg), cpu_T[0]); gen_jmp_im(s->pc - s->cs_base); gen_eob(s); } else { - gen_svm_check_intercept(s, pc_start, SVM_EXIT_READ_CR0 + reg); -#if !defined(CONFIG_USER_ONLY) - if (reg == 8) - tcg_gen_helper_1_0(helper_movtl_T0_cr8, cpu_T[0]); - else -#endif - gen_op_movtl_T0_env(offsetof(CPUX86State,cr[reg])); + gen_helper_read_crN(cpu_T[0], tcg_const_i32(reg)); gen_op_mov_reg_T0(ot, rm); } break; @@ -6641,13 +7394,12 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) if (b & 2) { gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_DR0 + reg); gen_op_mov_TN_reg(ot, 0, rm); - tcg_gen_helper_0_2(helper_movl_drN_T0, - tcg_const_i32(reg), cpu_T[0]); + gen_helper_movl_drN_T0(tcg_const_i32(reg), cpu_T[0]); gen_jmp_im(s->pc - s->cs_base); gen_eob(s); } else { gen_svm_check_intercept(s, pc_start, SVM_EXIT_READ_DR0 + reg); - gen_op_movtl_T0_env(offsetof(CPUX86State,dr[reg])); + tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,dr[reg])); gen_op_mov_reg_T0(ot, rm); } } @@ -6657,13 +7409,13 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); } else { gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_CR0); - tcg_gen_helper_0_0(helper_clts); + gen_helper_clts(); /* abort block because static cpu state changed */ gen_jmp_im(s->pc - s->cs_base); gen_eob(s); } break; - /* MMX/3DNow!/SSE/SSE2/SSE3 support */ + /* MMX/3DNow!/SSE/SSE2/SSE3/SSSE3/SSE4 support */ case 0x1c3: /* MOVNTI reg, mem */ if (!(s->cpuid_features & CPUID_SSE2)) goto illegal_op; @@ -6693,8 +7445,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) if (s->cc_op != CC_OP_DYNAMIC) gen_op_set_cc_op(s->cc_op); gen_jmp_im(pc_start - s->cs_base); - tcg_gen_helper_0_2(helper_fxsave, - cpu_A0, tcg_const_i32((s->dflag == 2))); + gen_helper_fxsave(cpu_A0, tcg_const_i32((s->dflag == 2))); break; case 1: /* fxrstor */ if (mod == 3 || !(s->cpuid_features & CPUID_FXSR) || @@ -6708,8 +7459,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) if (s->cc_op != CC_OP_DYNAMIC) gen_op_set_cc_op(s->cc_op); gen_jmp_im(pc_start - s->cs_base); - tcg_gen_helper_0_2(helper_fxrstor, - cpu_A0, tcg_const_i32((s->dflag == 2))); + gen_helper_fxrstor(cpu_A0, tcg_const_i32((s->dflag == 2))); break; case 2: /* ldmxcsr */ case 3: /* stmxcsr */ @@ -6723,9 +7473,9 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) gen_lea_modrm(s, modrm, ®_addr, &offset_addr); if (op == 2) { gen_op_ld_T0_A0(OT_LONG + s->mem_index); - gen_op_movl_env_T0(offsetof(CPUX86State, mxcsr)); + tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, mxcsr)); } else { - gen_op_movl_T0_env(offsetof(CPUX86State, mxcsr)); + tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, mxcsr)); gen_op_st_T0_A0(OT_LONG + s->mem_index); } break; @@ -6760,8 +7510,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) /* ignore for now */ break; case 0x1aa: /* rsm */ - if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_RSM)) - break; + gen_svm_check_intercept(s, pc_start, SVM_EXIT_RSM); if (!(s->flags & HF_SMM_MASK)) goto illegal_op; if (s->cc_op != CC_OP_DYNAMIC) { @@ -6769,14 +7518,38 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) s->cc_op = CC_OP_DYNAMIC; } gen_jmp_im(s->pc - s->cs_base); - tcg_gen_helper_0_0(helper_rsm); + gen_helper_rsm(); gen_eob(s); break; + case 0x1b8: /* SSE4.2 popcnt */ + if ((prefixes & (PREFIX_REPZ | PREFIX_LOCK | PREFIX_REPNZ)) != + PREFIX_REPZ) + goto illegal_op; + if (!(s->cpuid_ext_features & CPUID_EXT_POPCNT)) + goto illegal_op; + + modrm = ldub_code(s->pc++); + reg = ((modrm >> 3) & 7); + + if (s->prefix & PREFIX_DATA) + ot = OT_WORD; + else if (s->dflag != 2) + ot = OT_LONG; + else + ot = OT_QUAD; + + gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0); + gen_helper_popcnt(cpu_T[0], cpu_T[0], tcg_const_i32(ot)); + gen_op_mov_reg_T0(ot, reg); + + s->cc_op = CC_OP_EFLAGS; + break; case 0x10e ... 0x10f: /* 3DNow! instructions, ignore prefixes */ s->prefix &= ~(PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA); case 0x110 ... 0x117: case 0x128 ... 0x12f: + case 0x138 ... 0x13a: case 0x150 ... 0x177: case 0x17c ... 0x17f: case 0x1c2: @@ -6789,27 +7562,16 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) } /* lock generation */ if (s->prefix & PREFIX_LOCK) - tcg_gen_helper_0_0(helper_unlock); + gen_helper_unlock(); return s->pc; illegal_op: if (s->prefix & PREFIX_LOCK) - tcg_gen_helper_0_0(helper_unlock); + gen_helper_unlock(); /* XXX: ensure that no lock was generated */ gen_exception(s, EXCP06_ILLOP, pc_start - s->cs_base); return s->pc; } -static void tcg_macro_func(TCGContext *s, int macro_id, const int *dead_args) -{ - switch(macro_id) { -#ifdef MACRO_TEST - case MACRO_TEST: - tcg_gen_helper_0_1(helper_divl_EAX_T0, cpu_T[0]); - break; -#endif - } -} - void optimize_flags_init(void) { #if TCG_TARGET_REG_BITS == 32 @@ -6817,49 +7579,38 @@ void optimize_flags_init(void) #else assert(sizeof(CCTable) == (1 << 4)); #endif - tcg_set_macro_func(&tcg_ctx, tcg_macro_func); - - cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env"); -#if TARGET_LONG_BITS > HOST_LONG_BITS - cpu_T[0] = tcg_global_mem_new(TCG_TYPE_TL, - TCG_AREG0, offsetof(CPUState, t0), "T0"); - cpu_T[1] = tcg_global_mem_new(TCG_TYPE_TL, - TCG_AREG0, offsetof(CPUState, t1), "T1"); - cpu_A0 = tcg_global_mem_new(TCG_TYPE_TL, - TCG_AREG0, offsetof(CPUState, t2), "A0"); -#else - cpu_T[0] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG1, "T0"); - cpu_T[1] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG2, "T1"); - cpu_A0 = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG3, "A0"); -#endif - cpu_T3 = tcg_global_mem_new(TCG_TYPE_TL, - TCG_AREG0, offsetof(CPUState, t3), "T3"); -#if defined(__i386__) && (TARGET_LONG_BITS <= HOST_LONG_BITS) - /* XXX: must be suppressed once there are less fixed registers */ - cpu_tmp1_i64 = tcg_global_reg2_new_hack(TCG_TYPE_I64, TCG_AREG1, TCG_AREG2, "tmp1"); -#endif - cpu_cc_op = tcg_global_mem_new(TCG_TYPE_I32, - TCG_AREG0, offsetof(CPUState, cc_op), "cc_op"); - cpu_cc_src = tcg_global_mem_new(TCG_TYPE_TL, - TCG_AREG0, offsetof(CPUState, cc_src), "cc_src"); - cpu_cc_dst = tcg_global_mem_new(TCG_TYPE_TL, - TCG_AREG0, offsetof(CPUState, cc_dst), "cc_dst"); + cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); + cpu_cc_op = tcg_global_mem_new_i32(TCG_AREG0, + offsetof(CPUState, cc_op), "cc_op"); + cpu_cc_src = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, cc_src), + "cc_src"); + cpu_cc_dst = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, cc_dst), + "cc_dst"); + cpu_cc_tmp = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, cc_tmp), + "cc_tmp"); + + /* register helpers */ +#define GEN_HELPER 2 +#include "helper.h" } /* generate intermediate code in gen_opc_buf and gen_opparam_buf for basic block 'tb'. If search_pc is TRUE, also generate PC information for each intermediate instruction. */ -static inline int gen_intermediate_code_internal(CPUState *env, - TranslationBlock *tb, - int search_pc) +static inline void gen_intermediate_code_internal(CPUState *env, + TranslationBlock *tb, + int search_pc) { DisasContext dc1, *dc = &dc1; target_ulong pc_ptr; uint16_t *gen_opc_end; + CPUBreakpoint *bp; int j, lj, cflags; uint64_t flags; target_ulong pc_start; target_ulong cs_base; + int num_insns; + int max_insns; /* generate intermediate code */ pc_start = tb->pc; @@ -6892,6 +7643,7 @@ static inline int gen_intermediate_code_internal(CPUState *env, dc->cpuid_features = env->cpuid_features; dc->cpuid_ext_features = env->cpuid_ext_features; dc->cpuid_ext2_features = env->cpuid_ext2_features; + dc->cpuid_ext3_features = env->cpuid_ext3_features; #ifdef TARGET_X86_64 dc->lma = (flags >> HF_LMA_SHIFT) & 1; dc->code64 = (flags >> HF_CS64_SHIFT) & 1; @@ -6909,28 +7661,37 @@ static inline int gen_intermediate_code_internal(CPUState *env, printf("ERROR addseg\n"); #endif - cpu_tmp0 = tcg_temp_new(TCG_TYPE_TL); -#if !(defined(__i386__) && (TARGET_LONG_BITS <= HOST_LONG_BITS)) - cpu_tmp1_i64 = tcg_temp_new(TCG_TYPE_I64); -#endif - cpu_tmp2_i32 = tcg_temp_new(TCG_TYPE_I32); - cpu_tmp3_i32 = tcg_temp_new(TCG_TYPE_I32); - cpu_tmp4 = tcg_temp_new(TCG_TYPE_TL); - cpu_tmp5 = tcg_temp_new(TCG_TYPE_TL); - cpu_tmp6 = tcg_temp_new(TCG_TYPE_TL); - cpu_ptr0 = tcg_temp_new(TCG_TYPE_PTR); - cpu_ptr1 = tcg_temp_new(TCG_TYPE_PTR); + cpu_T[0] = tcg_temp_new(); + cpu_T[1] = tcg_temp_new(); + cpu_A0 = tcg_temp_new(); + cpu_T3 = tcg_temp_new(); + + cpu_tmp0 = tcg_temp_new(); + cpu_tmp1_i64 = tcg_temp_new_i64(); + cpu_tmp2_i32 = tcg_temp_new_i32(); + cpu_tmp3_i32 = tcg_temp_new_i32(); + cpu_tmp4 = tcg_temp_new(); + cpu_tmp5 = tcg_temp_new(); + cpu_tmp6 = tcg_temp_new(); + cpu_ptr0 = tcg_temp_new_ptr(); + cpu_ptr1 = tcg_temp_new_ptr(); gen_opc_end = gen_opc_buf + OPC_MAX_SIZE; dc->is_jmp = DISAS_NEXT; pc_ptr = pc_start; lj = -1; + num_insns = 0; + max_insns = tb->cflags & CF_COUNT_MASK; + if (max_insns == 0) + max_insns = CF_COUNT_MASK; + gen_icount_start(); for(;;) { - if (env->nb_breakpoints > 0) { - for(j = 0; j < env->nb_breakpoints; j++) { - if (env->breakpoints[j] == pc_ptr) { + if (unlikely(!TAILQ_EMPTY(&env->breakpoints))) { + TAILQ_FOREACH(bp, &env->breakpoints, entry) { + if (bp->pc == pc_ptr && + !((bp->flags & BP_CPU) && (tb->flags & HF_RF_MASK))) { gen_debug(dc, pc_ptr - dc->cs_base); break; } @@ -6946,8 +7707,13 @@ static inline int gen_intermediate_code_internal(CPUState *env, gen_opc_pc[lj] = pc_ptr; gen_opc_cc_op[lj] = dc->cc_op; gen_opc_instr_start[lj] = 1; + gen_opc_icount[lj] = num_insns; } + if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) + gen_io_start(); + pc_ptr = disas_insn(dc, pc_ptr); + num_insns++; /* stop translation if indicated */ if (dc->is_jmp) break; @@ -6957,20 +7723,28 @@ static inline int gen_intermediate_code_internal(CPUState *env, the flag and abort the translation to give the irqs a change to be happen */ if (dc->tf || dc->singlestep_enabled || - (flags & HF_INHIBIT_IRQ_MASK) || - (cflags & CF_SINGLE_INSN)) { + (flags & HF_INHIBIT_IRQ_MASK)) { gen_jmp_im(pc_ptr - dc->cs_base); gen_eob(dc); break; } /* if too long translation, stop generation too */ if (gen_opc_ptr >= gen_opc_end || - (pc_ptr - pc_start) >= (TARGET_PAGE_SIZE - 32)) { + (pc_ptr - pc_start) >= (TARGET_PAGE_SIZE - 32) || + num_insns >= max_insns) { + gen_jmp_im(pc_ptr - dc->cs_base); + gen_eob(dc); + break; + } + if (singlestep) { gen_jmp_im(pc_ptr - dc->cs_base); gen_eob(dc); break; } } + if (tb->cflags & CF_LAST_IO) + gen_io_end(); + gen_icount_end(tb, num_insns); *gen_opc_ptr = INDEX_op_end; /* we don't forget to fill the last values */ if (search_pc) { @@ -6981,42 +7755,36 @@ static inline int gen_intermediate_code_internal(CPUState *env, } #ifdef DEBUG_DISAS - if (loglevel & CPU_LOG_TB_CPU) { - cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP); - } - if (loglevel & CPU_LOG_TB_IN_ASM) { + log_cpu_state_mask(CPU_LOG_TB_CPU, env, X86_DUMP_CCOP); + if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { int disas_flags; - fprintf(logfile, "----------------\n"); - fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start)); + qemu_log("----------------\n"); + qemu_log("IN: %s\n", lookup_symbol(pc_start)); #ifdef TARGET_X86_64 if (dc->code64) disas_flags = 2; else #endif disas_flags = !dc->code32; - target_disas(logfile, pc_start, pc_ptr - pc_start, disas_flags); - fprintf(logfile, "\n"); - if (loglevel & CPU_LOG_TB_OP_OPT) { - fprintf(logfile, "OP before opt:\n"); - tcg_dump_ops(&tcg_ctx, logfile); - fprintf(logfile, "\n"); - } + log_target_disas(pc_start, pc_ptr - pc_start, disas_flags); + qemu_log("\n"); } #endif - if (!search_pc) + if (!search_pc) { tb->size = pc_ptr - pc_start; - return 0; + tb->icount = num_insns; + } } -int gen_intermediate_code(CPUState *env, TranslationBlock *tb) +void gen_intermediate_code(CPUState *env, TranslationBlock *tb) { - return gen_intermediate_code_internal(env, tb, 0); + gen_intermediate_code_internal(env, tb, 0); } -int gen_intermediate_code_pc(CPUState *env, TranslationBlock *tb) +void gen_intermediate_code_pc(CPUState *env, TranslationBlock *tb) { - return gen_intermediate_code_internal(env, tb, 1); + gen_intermediate_code_internal(env, tb, 1); } void gen_pc_load(CPUState *env, TranslationBlock *tb, @@ -7024,15 +7792,15 @@ void gen_pc_load(CPUState *env, TranslationBlock *tb, { int cc_op; #ifdef DEBUG_DISAS - if (loglevel & CPU_LOG_TB_OP) { + if (qemu_loglevel_mask(CPU_LOG_TB_OP)) { int i; - fprintf(logfile, "RESTORE:\n"); + qemu_log("RESTORE:\n"); for(i = 0;i <= pc_pos; i++) { if (gen_opc_instr_start[i]) { - fprintf(logfile, "0x%04x: " TARGET_FMT_lx "\n", i, gen_opc_pc[i]); + qemu_log("0x%04x: " TARGET_FMT_lx "\n", i, gen_opc_pc[i]); } } - fprintf(logfile, "spc=0x%08lx pc_pos=0x%x eip=" TARGET_FMT_lx " cs_base=%x\n", + qemu_log("spc=0x%08lx pc_pos=0x%x eip=" TARGET_FMT_lx " cs_base=%x\n", searched_pc, pc_pos, gen_opc_pc[pc_pos] - tb->cs_base, (uint32_t)tb->cs_base); }