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Add TCG native negation op.
author
pbrook
<pbrook@c046a42c-6fe2-441c-8c8c-71466251a162>
Sun, 11 May 2008 14:35:37 +0000
(14:35 +0000)
committer
pbrook
<pbrook@c046a42c-6fe2-441c-8c8c-71466251a162>
Sun, 11 May 2008 14:35:37 +0000
(14:35 +0000)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4426
c046a42c
-6fe2-441c-8c8c-
71466251a162
target-arm/translate.c
patch
|
blob
|
history
target-cris/translate.c
patch
|
blob
|
history
tcg/README
patch
|
blob
|
history
tcg/tcg-op.h
patch
|
blob
|
history
tcg/tcg-opc.h
patch
|
blob
|
history
tcg/x86_64/tcg-target.c
patch
|
blob
|
history
tcg/x86_64/tcg-target.h
patch
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blob
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history
diff --git
a/target-arm/translate.c
b/target-arm/translate.c
index
711676f
..
ef46342
100644
(file)
--- a/
target-arm/translate.c
+++ b/
target-arm/translate.c
@@
-457,12
+457,6
@@
static inline void tcg_gen_not_i32(TCGv t0, TCGv t1)
tcg_gen_xori_i32(t0, t1, ~0);
}
tcg_gen_xori_i32(t0, t1, ~0);
}
-/* FIXME: Implement this natively. */
-static inline void tcg_gen_neg_i64(TCGv dest, TCGv src)
-{
- tcg_gen_sub_i64(dest, tcg_const_i64(0), src);
-}
-
/* T0 &= ~T1. Clobbers T1. */
/* FIXME: Implement bic natively. */
static inline void tcg_gen_bic_i32(TCGv dest, TCGv t0, TCGv t1)
/* T0 &= ~T1. Clobbers T1. */
/* FIXME: Implement bic natively. */
static inline void tcg_gen_bic_i32(TCGv dest, TCGv t0, TCGv t1)
@@
-8111,7
+8105,7
@@
static void disas_thumb_insn(CPUState *env, DisasContext *s)
break;
case 0x9: /* neg */
if (s->condexec_mask)
break;
case 0x9: /* neg */
if (s->condexec_mask)
- gen_op_subl_T0_T1();
+ tcg_gen_neg_i32(cpu_T[0], cpu_T[1]);
else
gen_op_subl_T0_T1_cc();
break;
else
gen_op_subl_T0_T1_cc();
break;
diff --git
a/target-cris/translate.c
b/target-cris/translate.c
index
89a0533
..
9551ea1
100644
(file)
--- a/
target-cris/translate.c
+++ b/
target-cris/translate.c
@@
-318,7
+318,7
@@
static void t_gen_lz_i32(TCGv d, TCGv x)
/* y = -(x >> 16) */
tcg_gen_shri_i32(y, x, 16);
/* y = -(x >> 16) */
tcg_gen_shri_i32(y, x, 16);
- tcg_gen_sub_i32(y, tcg_const_i32(0), y);
+ tcg_gen_neg_i32(y, y);
/* m = (y >> 16) & 16 */
tcg_gen_sari_i32(m, y, 16);
/* m = (y >> 16) & 16 */
tcg_gen_sari_i32(m, y, 16);
@@
-753,9
+753,9
@@
static void crisv32_alu_op(DisasContext *dc, int op, int rd, int size)
t_gen_add_flag(cpu_T[0], 8); /* R_FLAG. */
break;
case CC_OP_SUB:
t_gen_add_flag(cpu_T[0], 8); /* R_FLAG. */
break;
case CC_OP_SUB:
- tcg_gen_sub_tl(cpu_T[1], tcg_const_tl(0), cpu_T[1]);
+ tcg_gen_neg_tl(cpu_T[1], cpu_T[1]);
tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
- tcg_gen_sub_tl(cpu_T[1], tcg_const_tl(0), cpu_T[1]);
+ tcg_gen_neg_tl(cpu_T[1], cpu_T[1]);
/* CRIS flag evaluation needs ~src. */
tcg_gen_xori_tl(cpu_T[1], cpu_T[1], -1);
/* CRIS flag evaluation needs ~src. */
tcg_gen_xori_tl(cpu_T[1], cpu_T[1], -1);
@@
-784,9
+784,7
@@
static void crisv32_alu_op(DisasContext *dc, int op, int rd, int size)
t_gen_asr(cpu_T[0], cpu_T[0], cpu_T[1]);
break;
case CC_OP_NEG:
t_gen_asr(cpu_T[0], cpu_T[0], cpu_T[1]);
break;
case CC_OP_NEG:
- /* Hopefully the TCG backend recognizes this pattern
- and makes a real neg out of it. */
- tcg_gen_sub_tl(cpu_T[0], tcg_const_tl(0), cpu_T[1]);
+ tcg_gen_neg_tl(cpu_T[0], cpu_T[1]);
/* Extended arithmetics. */
t_gen_subx_carry(cpu_T[0]);
break;
/* Extended arithmetics. */
t_gen_subx_carry(cpu_T[0]);
break;
@@
-829,10
+827,10
@@
static void crisv32_alu_op(DisasContext *dc, int op, int rd, int size)
}
break;
case CC_OP_CMP:
}
break;
case CC_OP_CMP:
- tcg_gen_sub_tl(cpu_T[1], tcg_const_tl(0), cpu_T[1]);
+ tcg_gen_neg_tl(cpu_T[1], cpu_T[1]);
tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
/* CRIS flag evaluation needs ~src. */
tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
/* CRIS flag evaluation needs ~src. */
- tcg_gen_sub_tl(cpu_T[1], tcg_const_tl(0), cpu_T[1]);
+ tcg_gen_neg_tl(cpu_T[1], cpu_T[1]);
/* CRIS flag evaluation needs ~src. */
tcg_gen_xori_tl(cpu_T[1], cpu_T[1], -1);
/* CRIS flag evaluation needs ~src. */
tcg_gen_xori_tl(cpu_T[1], cpu_T[1], -1);
@@
-1642,7
+1640,7
@@
static unsigned int dec_abs_r(DisasContext *dc)
/* TODO: consider a branch free approach. */
l1 = gen_new_label();
tcg_gen_brcond_tl(TCG_COND_GE, cpu_T[1], tcg_const_tl(0), l1);
/* TODO: consider a branch free approach. */
l1 = gen_new_label();
tcg_gen_brcond_tl(TCG_COND_GE, cpu_T[1], tcg_const_tl(0), l1);
- tcg_gen_sub_tl(cpu_T[1], tcg_const_tl(0), cpu_T[1]);
+ tcg_gen_neg_tl(cpu_T[1], cpu_T[1]);
gen_set_label(l1);
crisv32_alu_op(dc, CC_OP_MOVE, dc->op2, 4);
return 2;
gen_set_label(l1);
crisv32_alu_op(dc, CC_OP_MOVE, dc->op2, 4);
return 2;
diff --git
a/tcg/README
b/tcg/README
index
c47d3b0
..
c879142
100644
(file)
--- a/
tcg/README
+++ b/
tcg/README
@@
-203,6
+203,10
@@
t0=t1+t2
t0=t1-t2
t0=t1-t2
+* neg_i32/i64 t0, t1
+
+t0=-t1 (two's complement)
+
* mul_i32/i64 t0, t1, t2
t0=t1*t2
* mul_i32/i64 t0, t1, t2
t0=t1*t2
diff --git
a/tcg/tcg-op.h
b/tcg/tcg-op.h
index
8ab9536
..
c8e398b
100644
(file)
--- a/
tcg/tcg-op.h
+++ b/
tcg/tcg-op.h
@@
-1208,6
+1208,24
@@
static inline void tcg_gen_bswap_i64(TCGv ret, TCGv arg)
#endif
#endif
+static inline void tcg_gen_neg_i32(TCGv ret, TCGv arg)
+{
+#ifdef TCG_TARGET_HAS_neg_i32
+ tcg_gen_op2(INDEX_op_neg_i32, ret, arg);
+#else
+ tcg_gen_sub_i32(ret, tcg_const_i32(0), arg);
+#endif
+}
+
+static inline void tcg_gen_neg_i64(TCGv ret, TCGv arg)
+{
+#ifdef TCG_TARGET_HAS_neg_i64
+ tcg_gen_op2(INDEX_op_neg_i64, ret, arg);
+#else
+ tcg_gen_sub_i64(ret, tcg_const_i64(0), arg);
+#endif
+}
+
static inline void tcg_gen_discard_i32(TCGv arg)
{
static inline void tcg_gen_discard_i32(TCGv arg)
{
@@
-1441,6
+1459,7
@@
static inline void tcg_gen_qemu_st64(TCGv arg, TCGv addr, int mem_index)
#define tcg_gen_add_tl tcg_gen_add_i64
#define tcg_gen_addi_tl tcg_gen_addi_i64
#define tcg_gen_sub_tl tcg_gen_sub_i64
#define tcg_gen_add_tl tcg_gen_add_i64
#define tcg_gen_addi_tl tcg_gen_addi_i64
#define tcg_gen_sub_tl tcg_gen_sub_i64
+#define tcg_gen_neg_tl tcg_gen_neg_i64
#define tcg_gen_subi_tl tcg_gen_subi_i64
#define tcg_gen_and_tl tcg_gen_and_i64
#define tcg_gen_andi_tl tcg_gen_andi_i64
#define tcg_gen_subi_tl tcg_gen_subi_i64
#define tcg_gen_and_tl tcg_gen_and_i64
#define tcg_gen_andi_tl tcg_gen_andi_i64
@@
-1483,6
+1502,7
@@
static inline void tcg_gen_qemu_st64(TCGv arg, TCGv addr, int mem_index)
#define tcg_gen_add_tl tcg_gen_add_i32
#define tcg_gen_addi_tl tcg_gen_addi_i32
#define tcg_gen_sub_tl tcg_gen_sub_i32
#define tcg_gen_add_tl tcg_gen_add_i32
#define tcg_gen_addi_tl tcg_gen_addi_i32
#define tcg_gen_sub_tl tcg_gen_sub_i32
+#define tcg_gen_neg_tl tcg_gen_neg_i32
#define tcg_gen_subi_tl tcg_gen_subi_i32
#define tcg_gen_and_tl tcg_gen_and_i32
#define tcg_gen_andi_tl tcg_gen_andi_i32
#define tcg_gen_subi_tl tcg_gen_subi_i32
#define tcg_gen_and_tl tcg_gen_and_i32
#define tcg_gen_andi_tl tcg_gen_andi_i32
diff --git
a/tcg/tcg-opc.h
b/tcg/tcg-opc.h
index
fb1a63c
..
a80056a
100644
(file)
--- a/
tcg/tcg-opc.h
+++ b/
tcg/tcg-opc.h
@@
-148,6
+148,12
@@
DEF2(ext32s_i64, 1, 1, 0, 0)
DEF2(bswap_i64, 1, 1, 0, 0)
#endif
#endif
DEF2(bswap_i64, 1, 1, 0, 0)
#endif
#endif
+#ifdef TCG_TARGET_HAS_neg_i32
+DEF2(neg_i32, 1, 1, 0, 0)
+#endif
+#ifdef TCG_TARGET_HAS_neg_i64
+DEF2(neg_i64, 1, 1, 0, 0)
+#endif
/* QEMU specific */
DEF2(exit_tb, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
/* QEMU specific */
DEF2(exit_tb, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
diff --git
a/tcg/x86_64/tcg-target.c
b/tcg/x86_64/tcg-target.c
index
f11bc66
..
7197f40
100644
(file)
--- a/
tcg/x86_64/tcg-target.c
+++ b/
tcg/x86_64/tcg-target.c
@@
-1092,6
+1092,13
@@
static inline void tcg_out_op(TCGContext *s, int opc, const TCGArg *args,
tcg_out_opc(s, (0xc8 + (args[0] & 7)) | P_EXT | P_REXW, 0, args[0], 0);
break;
tcg_out_opc(s, (0xc8 + (args[0] & 7)) | P_EXT | P_REXW, 0, args[0], 0);
break;
+ case INDEX_op_neg_i32:
+ tcg_out_modrm(s, 0xf7, 3, args[0]);
+ break;
+ case INDEX_op_neg_i64:
+ tcg_out_modrm(s, 0xf7 | P_REXW, 3, args[0]);
+ break;
+
case INDEX_op_qemu_ld8u:
tcg_out_qemu_ld(s, args, 0);
break;
case INDEX_op_qemu_ld8u:
tcg_out_qemu_ld(s, args, 0);
break;
@@
-1247,6
+1254,9
@@
static const TCGTargetOpDef x86_64_op_defs[] = {
{ INDEX_op_bswap_i32, { "r", "0" } },
{ INDEX_op_bswap_i64, { "r", "0" } },
{ INDEX_op_bswap_i32, { "r", "0" } },
{ INDEX_op_bswap_i64, { "r", "0" } },
+ { INDEX_op_neg_i32, { "r", "0" } },
+ { INDEX_op_neg_i64, { "r", "0" } },
+
{ INDEX_op_qemu_ld8u, { "r", "L" } },
{ INDEX_op_qemu_ld8s, { "r", "L" } },
{ INDEX_op_qemu_ld16u, { "r", "L" } },
{ INDEX_op_qemu_ld8u, { "r", "L" } },
{ INDEX_op_qemu_ld8s, { "r", "L" } },
{ INDEX_op_qemu_ld16u, { "r", "L" } },
diff --git
a/tcg/x86_64/tcg-target.h
b/tcg/x86_64/tcg-target.h
index
c8421f7
..
cdb66a5
100644
(file)
--- a/
tcg/x86_64/tcg-target.h
+++ b/
tcg/x86_64/tcg-target.h
@@
-57,6
+57,8
@@
enum {
/* optional instructions */
#define TCG_TARGET_HAS_bswap_i32
#define TCG_TARGET_HAS_bswap_i64
/* optional instructions */
#define TCG_TARGET_HAS_bswap_i32
#define TCG_TARGET_HAS_bswap_i64
+#define TCG_TARGET_HAS_neg_i32
+#define TCG_TARGET_HAS_neg_i64
/* Note: must be synced with dyngen-exec.h */
#define TCG_AREG0 TCG_REG_R14
/* Note: must be synced with dyngen-exec.h */
#define TCG_AREG0 TCG_REG_R14