target-sh4: fix 64-bit fmov to/from memory

When loading/storing a register pair, the even-numbered register
always maps to the low 32 bits of memory independently of target
endian configuration.

Signed-off-by: Mans Rullgard <mans@mansr.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5773 c046a42c-6fe2-441c-8c8c-71466251a162

diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index 84a3f40..bbfd745 100644 (file)
--- a/target-sh4/translate.c
+++ b/target-sh4/translate.c
@@ -991,31 +991,37 @@ static void _decode_opc(DisasContext * ctx)
        return;
     case 0xf00a: /* fmov {F,D,X}Rm,@Rn - FPSCR: Nothing */
        if (ctx->fpscr & FPSCR_SZ) {
-           TCGv_i64 fp = tcg_temp_new_i64();
-           gen_load_fpr64(fp, XREG(B7_4));
-           tcg_gen_qemu_st64(fp, REG(B11_8), ctx->memidx);
-           tcg_temp_free_i64(fp);
+           TCGv addr_hi = tcg_temp_new();
+           int fr = XREG(B7_4);
+           tcg_gen_addi_i32(addr_hi, REG(B11_8), 4);
+           tcg_gen_qemu_st32(cpu_fregs[fr  ], REG(B11_8), ctx->memidx);
+           tcg_gen_qemu_st32(cpu_fregs[fr+1], addr_hi,    ctx->memidx);
+           tcg_temp_free(addr_hi);
        } else {
            tcg_gen_qemu_st32(cpu_fregs[FREG(B7_4)], REG(B11_8), ctx->memidx);
        }
        return;
     case 0xf008: /* fmov @Rm,{F,D,X}Rn - FPSCR: Nothing */
        if (ctx->fpscr & FPSCR_SZ) {
-           TCGv_i64 fp = tcg_temp_new_i64();
-           tcg_gen_qemu_ld64(fp, REG(B7_4), ctx->memidx);
-           gen_store_fpr64(fp, XREG(B11_8));
-           tcg_temp_free_i64(fp);
+           TCGv addr_hi = tcg_temp_new();
+           int fr = XREG(B11_8);
+           tcg_gen_addi_i32(addr_hi, REG(B7_4), 4);
+           tcg_gen_qemu_ld32u(cpu_fregs[fr  ], REG(B7_4), ctx->memidx);
+           tcg_gen_qemu_ld32u(cpu_fregs[fr+1], addr_hi,   ctx->memidx);
+           tcg_temp_free(addr_hi);
        } else {
            tcg_gen_qemu_ld32u(cpu_fregs[FREG(B11_8)], REG(B7_4), ctx->memidx);
        }
        return;
     case 0xf009: /* fmov @Rm+,{F,D,X}Rn - FPSCR: Nothing */
        if (ctx->fpscr & FPSCR_SZ) {
-           TCGv_i64 fp = tcg_temp_new_i64();
-           tcg_gen_qemu_ld64(fp, REG(B7_4), ctx->memidx);
-           gen_store_fpr64(fp, XREG(B11_8));
-           tcg_temp_free_i64(fp);
-           tcg_gen_addi_i32(REG(B7_4),REG(B7_4), 8);
+           TCGv addr_hi = tcg_temp_new();
+           int fr = XREG(B11_8);
+           tcg_gen_addi_i32(addr_hi, REG(B7_4), 4);
+           tcg_gen_qemu_ld32u(cpu_fregs[fr  ], REG(B7_4), ctx->memidx);
+           tcg_gen_qemu_ld32u(cpu_fregs[fr+1], addr_hi,   ctx->memidx);
+           tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 8);
+           tcg_temp_free(addr_hi);
        } else {
            tcg_gen_qemu_ld32u(cpu_fregs[FREG(B11_8)], REG(B7_4), ctx->memidx);
            tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4);
@@ -1023,16 +1029,14 @@ static void _decode_opc(DisasContext * ctx)
        return;
     case 0xf00b: /* fmov {F,D,X}Rm,@-Rn - FPSCR: Nothing */
        if (ctx->fpscr & FPSCR_SZ) {
-           TCGv addr;
-            TCGv_i64 fp;
-           addr = tcg_temp_new();
+           TCGv addr = tcg_temp_new_i32();
+           int fr = XREG(B7_4);
+           tcg_gen_subi_i32(addr, REG(B11_8), 4);
+           tcg_gen_qemu_st32(cpu_fregs[fr+1], addr, ctx->memidx);
            tcg_gen_subi_i32(addr, REG(B11_8), 8);
-           fp = tcg_temp_new_i64();
-           gen_load_fpr64(fp, XREG(B7_4));
-           tcg_gen_qemu_st64(fp, addr, ctx->memidx);
-           tcg_temp_free_i64(fp);
+           tcg_gen_qemu_st32(cpu_fregs[fr  ], addr, ctx->memidx);
+           tcg_gen_mov_i32(REG(B11_8), addr);
            tcg_temp_free(addr);
-           tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 8);
        } else {
            TCGv addr;
            addr = tcg_temp_new_i32();
@@ -1047,10 +1051,10 @@ static void _decode_opc(DisasContext * ctx)
            TCGv addr = tcg_temp_new_i32();
            tcg_gen_add_i32(addr, REG(B7_4), REG(0));
            if (ctx->fpscr & FPSCR_SZ) {
-               TCGv_i64 fp = tcg_temp_new_i64();
-               tcg_gen_qemu_ld64(fp, addr, ctx->memidx);
-               gen_store_fpr64(fp, XREG(B11_8));
-               tcg_temp_free_i64(fp);
+               int fr = XREG(B11_8);
+               tcg_gen_qemu_ld32u(cpu_fregs[fr  ], addr, ctx->memidx);
+               tcg_gen_addi_i32(addr, addr, 4);
+               tcg_gen_qemu_ld32u(cpu_fregs[fr+1], addr, ctx->memidx);
            } else {
                tcg_gen_qemu_ld32u(cpu_fregs[FREG(B11_8)], addr, ctx->memidx);
            }
@@ -1062,10 +1066,10 @@ static void _decode_opc(DisasContext * ctx)
            TCGv addr = tcg_temp_new();
            tcg_gen_add_i32(addr, REG(B11_8), REG(0));
            if (ctx->fpscr & FPSCR_SZ) {
-               TCGv_i64 fp = tcg_temp_new_i64();
-               gen_load_fpr64(fp, XREG(B7_4));
-               tcg_gen_qemu_st64(fp, addr, ctx->memidx);
-               tcg_temp_free_i64(fp);
+               int fr = XREG(B7_4);
+               tcg_gen_qemu_ld32u(cpu_fregs[fr  ], addr, ctx->memidx);
+               tcg_gen_addi_i32(addr, addr, 4);
+               tcg_gen_qemu_ld32u(cpu_fregs[fr+1], addr, ctx->memidx);
            } else {
                tcg_gen_qemu_st32(cpu_fregs[FREG(B7_4)], addr, ctx->memidx);
            }