\r
static uint32_t omap3_l4ta_read(void *opaque, target_phys_addr_t addr)\r
{\r
- struct omap_target_agent_s *s = (struct omap_target_agent_s *) opaque;\r
+ struct omap_target_agent_s *s = (struct omap_target_agent_s *)opaque;\r
\r
- switch (addr)\r
- {\r
- //case 0x00: /* COMPONENT */\r
- // return s->component;\r
- case 0x20: /* AGENT_CONTROL */\r
- return s->control;\r
-\r
- case 0x24: /* AGENT_CONTROL_H */\r
- return s->control_h;\r
-\r
- case 0x28: /* AGENT_STATUS */\r
- return s->status;\r
+ switch (addr) {\r
+ case 0x00: /* COMPONENT_L */\r
+ return s->component;\r
+ case 0x04: /* COMPONENT_H */\r
+ return 0;\r
+ case 0x18: /* CORE_L */\r
+ return s->component;\r
+ case 0x1c: /* CORE_H */\r
+ return (s->component >> 16);\r
+ case 0x20: /* AGENT_CONTROL_L */\r
+ return s->control;\r
+ case 0x24: /* AGENT_CONTROL_H */\r
+ return s->control_h;\r
+ case 0x28: /* AGENT_STATUS_L */\r
+ return s->status;\r
+ case 0x2c: /* AGENT_STATUS_H */\r
+ return 0;\r
+ default:\r
+ break;\r
}\r
\r
- OMAP_BAD_REG(addr);\r
+ OMAP_BAD_REG(s->base + addr);\r
return 0;\r
}\r
\r
static void omap3_l4ta_write(void *opaque, target_phys_addr_t addr,\r
uint32_t value)\r
{\r
- struct omap_target_agent_s *s = (struct omap_target_agent_s *) opaque;\r
+ struct omap_target_agent_s *s = (struct omap_target_agent_s *)opaque;\r
\r
- switch (addr)\r
- {\r
- //case 0x00: /* COMPONENT */\r
- // OMAP_RO_REG(addr);\r
- // break;\r
- case 0x20: /* AGENT_CONTROL */\r
- s->control = value & 0x00000700;\r
- break;\r
- case 0x24: /* AGENT_CONTROL_H */\r
- s->control_h = value & 0x100;\r
- break;\r
- case 0x28: /* AGENT_STATUS */\r
- if (value & 0x100)\r
- s->status &= ~0x100; /* REQ_TIMEOUT */\r
- break;\r
- default:\r
- OMAP_BAD_REG(addr);\r
+ switch (addr) {\r
+ case 0x00: /* COMPONENT_L */\r
+ case 0x04: /* COMPONENT_H */\r
+ case 0x18: /* CORE_L */\r
+ case 0x1c: /* CORE_H */\r
+ OMAP_RO_REG(s->base + addr);\r
+ break;\r
+ case 0x20: /* AGENT_CONTROL_L */\r
+ s->control = value & 0x00000701;\r
+ break;\r
+ case 0x24: /* AGENT_CONTROL_H */\r
+ s->control_h = value & 0x100; /* TODO: shouldn't this be read-only? */\r
+ break;\r
+ case 0x28: /* AGENT_STATUS_L */\r
+ if (value & 0x100)\r
+ s->status &= ~0x100; /* REQ_TIMEOUT */\r
+ break;\r
+ case 0x2c: /* AGENT_STATUS_H */\r
+ /* no writable bits although the register is listed as RW */\r
+ break;\r
+ default:\r
+ OMAP_BAD_REG(s->base + addr);\r
+ break;\r
}\r
}\r
\r
omap3_l4ta_write,\r
};\r
\r
-\r
-\r
-static struct omap_l4_region_s omap3_l4_region[] = {\r
- [1] = {0x40800, 0x800, 32}, /* Initiator agent */\r
- [2] = {0x41000, 0x1000, 32}, /* Link agent */\r
- [0] = {0x40000, 0x800, 32}, /* Address and protection */\r
-\r
- [3] = {0x002000, 0x1000, 32 | 16 | 8}, /* System Control module */\r
- [4] = {0x003000, 0x1000, 32 | 16 | 8}, /* L4TA1 */\r
-\r
- [5] = {0x004000, 0x2000, 32}, /*CM Region A */\r
- [6] = {0x006000, 0x0800, 32}, /*CM Region B */\r
- [7] = {0x007000, 0x1000, 32 | 16 | 8}, /* L4TA2 */\r
-\r
- [8] = {0x050000, 0x0400, 32}, /*Display subsystem top */\r
- [9] = {0x050400, 0x0400, 32}, /*Display controller */\r
- [10] = {0x050800, 0x0400, 32}, /*RFBI*/\r
- [11] = {0x050c00, 0x0400, 32}, /*Video encoder */\r
- [12] = {0x051000, 0x1000, 32 | 16 | 8}, /* L4TA3 */\r
-\r
- [13] = {0x056000, 0x1000, 32}, /* SDMA */\r
- [14] = {0x057000, 0x1000, 32 | 16 | 8}, /* L4TA4 */\r
-\r
- [15] = {0x060000, 0x1000, 16 | 8}, /* I2C3 */\r
- [16] = {0x061000, 0x1000, 32 | 16 | 8}, /* L4TA4 */\r
-\r
- [17] = {0x062000, 0x1000, 32}, /* USBTLL */\r
- [18] = {0x063000, 0x1000, 32 | 16 | 8}, /* L4TA4 */\r
-\r
- [19] = {0x064000, 0x1000, 32}, /* HS USB HOST */\r
- [20] = {0x065000, 0x1000, 32 | 16 | 8}, /* L4TA4 */\r
-\r
- [21] = {0x06a000, 0x1000, 32 | 16 | 8}, /* UART1 */\r
- [22] = {0x06b000, 0x1000, 32 | 16 | 8}, /* L4TA4 */\r
-\r
- [23] = {0x06c000, 0x1000, 32 | 16 | 8}, /* UART2 */\r
- [24] = {0x06d000, 0x1000, 32 | 16 | 8}, /* L4TA4 */\r
-\r
- [25] = {0x070000, 0x1000, 16 | 8}, /* I2C1 */\r
- [26] = {0x071000, 0x1000, 32 | 16 | 8}, /* L4TA4 */\r
-\r
- [27] = {0x072000, 0x1000, 16 | 8}, /* I2C2 */\r
- [28] = {0x073000, 0x1000, 32 | 16 | 8}, /* L4TA4 */\r
-\r
- [29] = {0x074000, 0x1000, 32}, /* mcbsp1 */\r
- [30] = {0x075000, 0x1000, 32 | 16 | 8}, /* L4TA4 */\r
-\r
- [31] = {0x086000, 0x1000, 32 | 16}, /* GPTIMER10 */\r
- [32] = {0x087000, 0x1000, 32 | 16 | 8}, /* L4TA4 */\r
-\r
- [33] = {0x088000, 0x1000, 32 | 16}, /* GPTIMER11 */\r
- [34] = {0x089000, 0x1000, 32 | 16 | 8}, /* L4TA4 */\r
-\r
- [35] = {0x094000, 0x1000, 32 | 16 | 8}, /* MAILBOX */\r
- [36] = {0x095000, 0x1000, 32 | 16 | 8}, /* L4TA4 */\r
-\r
- [37] = {0x096000, 0x1000, 32}, /* mcbsp5 */\r
- [38] = {0x097000, 0x1000, 32 | 16 | 8}, /* L4TA4 */\r
-\r
- [39] = {0x098000, 0x1000, 32 | 16 | 8}, /* MCSPI1 */\r
- [40] = {0x099000, 0x1000, 32 | 16 | 8}, /* L4TA4 */\r
-\r
- [41] = {0x09a000, 0x1000, 32 | 16 | 8}, /* MCSPI2 */\r
- [42] = {0x09b000, 0x1000, 32 | 16 | 8}, /* L4TA4 */\r
-\r
- [43] = {0x09c000, 0x1000, 32}, /* MMC/SD/SDIO */\r
- [44] = {0x09d000, 0x1000, 32 | 16 | 8}, /* L4TA4 */\r
-\r
- [45] = {0x09e000, 0x1000, 32}, /* MS-PRO */\r
- [46] = {0x09f000, 0x1000, 32 | 16 | 8}, /* L4TA4 */\r
-\r
- [47] = {0x09e000, 0x1000, 32}, /* MS-PRO */\r
- [48] = {0x09f000, 0x1000, 32 | 16 | 8}, /* L4TA4 */\r
-\r
- [49] = {0x0ab000, 0x1000, 32}, /* HS USB OTG */\r
- [50] = {0x0ac000, 0x1000, 32 | 16 | 8}, /* L4TA4 */\r
-\r
- [51] = {0x0ad000, 0x1000, 32}, /* MMC/SD/SDIO3 */\r
- [52] = {0x0ae000, 0x1000, 32 | 16 | 8}, /* L4TA4 */\r
-\r
- [53] = {0x0b0000, 0x1000, 32 | 16}, /* MG */\r
- [54] = {0x0b1000, 0x1000, 32 | 16 | 8}, /* L4TA4 */\r
-\r
- [55] = {0x0b2000, 0x1000, 32}, /* HDQ/1-WIRE */\r
- [56] = {0x0b3000, 0x1000, 32 | 16 | 8}, /* L4TA4 */\r
-\r
- [57] = {0x0b4000, 0x1000, 32}, /* MMC/SD/SDIO2 */\r
- [58] = {0x0b5000, 0x1000, 32 | 16 | 8}, /* L4TA4 */\r
-\r
- [59] = {0x0b6000, 0x1000, 32}, /* icr mpu */\r
- [60] = {0x0b7000, 0x1000, 32 | 16 | 8}, /* L4TA4 */\r
-\r
- [61] = {0x0b8000, 0x1000, 32 | 16 | 8}, /* MCSPI3 */\r
- [62] = {0x0b9000, 0x1000, 32 | 16 | 8}, /* L4TA4 */\r
-\r
- [63] = {0x0ba000, 0x1000, 32 | 16 | 8}, /* MCSPI4 */\r
- [64] = {0x0bb000, 0x1000, 32 | 16 | 8}, /* L4TA4 */\r
-\r
- [65] = {0x0bc000, 0x4000, 32 | 16 | 8}, /* CAMERA ISP */\r
- [66] = {0x0c0000, 0x1000, 32 | 16 | 8}, /* L4TA4 */\r
-\r
- [67] = {0x0c7000, 0x1000, 32 | 16}, /* MODEM */\r
- [68] = {0x0c8000, 0x1000, 32 | 16 | 8}, /* L4TA4 */\r
-\r
- [69] = {0x0c9000, 0x1000, 32 | 16 | 8}, /* SR1 */\r
- [70] = {0x0ca000, 0x1000, 32 | 16 | 8}, /* L4TA4 */\r
-\r
- [71] = {0x0cb000, 0x1000, 32 | 16 | 8}, /* SR2 */\r
- [72] = {0x0cc000, 0x1000, 32 | 16 | 8}, /* L4TA4 */\r
-\r
- [73] = {0x0cd000, 0x1000, 32}, /* ICR MODEM */\r
- [74] = {0x0ce000, 0x1000, 32 | 16 | 8}, /* L4TA4 */\r
-\r
- [75] = {0x30a000, 0x1000, 32 | 16 | 8}, /* CONTRL MODULE ID */\r
- [76] = {0x30b000, 0x1000, 32 | 16 | 8}, /* L4TA4 */\r
-\r
- \r
- [77] = {0x306000, 0x2000, 32}, /* PRM REGION A */\r
- [78] = {0x308000, 0x800, 32}, /* PRM REGION B */\r
- [79] = {0x309000, 0x1000, 32 | 16 | 8}, /* L4TA4 */\r
-\r
- /*L4 WAKEUP MEMORY SPACE */\r
- [80] = {0x304000, 0x1000, 32 | 16}, /* GPTIMER12 */\r
- [81] = {0x305000, 0x1000, 32 | 16 | 8}, /* L4TA4 */\r
- \r
- [82] = {0x30a000, 0x800, 32 | 16 | 8}, /*TAP.undocument*/\r
- [83] = {0x30a800, 0x1000, 32 | 16 | 8}, /* L4TA4 */\r
-\r
-\r
- [84] = {0x310000, 0x1000, 32 | 16 | 8}, /* GPIO1 */\r
- [85] = {0x311000, 0x1000, 32 | 16 | 8}, /* L4TA4 */\r
-\r
- [86] = {0x314000, 0x1000, 32 | 16}, /* WDTIMER2 */\r
- [87] = {0x315000, 0x1000, 32 | 16 | 8}, /* L4TA4 */\r
-\r
- [88] = {0x318000, 0x1000, 32 | 16}, /* GPTIMER1 */\r
- [89] = {0x319000, 0x1000, 32 | 16 | 8}, /* L4TA4 */\r
-\r
- [90] = {0x320000, 0x1000, 32 | 16}, /* 32K Timer */\r
- [91] = {0x321000, 0x1000, 32 | 16 | 8}, /* L4TA2 */\r
-\r
- [92] = {0x328000, 0x800, 32 | 16 | 8}, /* AP */\r
- [93] = {0x328800, 0x800, 32 | 16 | 8}, /* IP */\r
- [94] = {0x329000, 0x1000, 32 | 16 | 8}, /* LA */\r
- [95] = {0x32a000, 0x800, 32 | 16 | 8}, /* LA */\r
- [96] = {0x340000, 0x1000, 32 | 16 | 8}, /* L4TA4 */\r
-\r
- /*L4 Peripheral MEMORY SPACE */\r
- [97] = {0x1000000, 0x800, 32 | 16 | 8}, /* AP */\r
- [98] = {0x1000800, 0x800, 32 | 16 | 8}, /* IP */\r
- [99] = {0x1001000, 0x1000, 32 | 16 | 8}, /* LA */\r
-\r
- [100] = {0x1020000, 0x1000, 32 | 16 | 8}, /* UART3 */\r
- [101] = {0x1021000, 0x1000, 32 | 16 | 8}, /* L4TA4 */\r
-\r
- [102] = {0x1022000, 0x1000, 32}, /* MCBSP 2 */\r
- [103] = {0x1023000, 0x1000, 32 | 16 | 8}, /* L4TA4 */\r
- \r
- [104] = {0x1024000, 0x1000, 32}, /* MCBSP 3 */\r
- [105] = {0x1025000, 0x1000, 32 | 16 | 8}, /* L4TA4 */\r
-\r
- [106] = {0x1026000, 0x1000, 32}, /* MCBSP 4 */\r
- [107] = {0x1027000, 0x1000, 32 | 16 | 8}, /* L4TA4 */\r
-\r
- [108] = {0x1028000, 0x1000, 32}, /* MCBSP 2 (sidetone) */\r
- [109] = {0x1029000, 0x1000, 32 | 16 | 8}, /* L4TA4 */\r
-\r
- [110] = {0x102a000, 0x1000, 32}, /* MCBSP 3 (sidetone) */\r
- [111] = {0x102b000, 0x1000, 32 | 16 | 8}, /* L4TA4 */\r
-\r
- [112] = {0x1030000, 0x1000, 32 | 16}, /* WDTIMER3 */\r
- [113] = {0x1031000, 0x1000, 32 | 16 | 8}, /* L4TA4 */\r
-\r
- [114] = {0x1032000, 0x1000, 32 | 16}, /* GPTIMER2 */\r
- [115] = {0x1033000, 0x1000, 32 | 16 | 8}, /* L4TA4 */\r
-\r
- [116] = {0x1034000, 0x1000, 32 | 16}, /* GPTIMER3 */\r
- [117] = {0x1035000, 0x1000, 32 | 16 | 8}, /* L4TA4 */\r
-\r
- [118] = {0x1036000, 0x1000, 32 | 16}, /* GPTIMER4 */\r
- [119] = {0x1037000, 0x1000, 32 | 16 | 8}, /* L4TA4 */\r
-\r
- [120] = {0x1038000, 0x1000, 32 | 16}, /* GPTIMER5 */\r
- [121] = {0x1039000, 0x1000, 32 | 16 | 8}, /* L4TA4 */\r
-\r
- [122] = {0x103a000, 0x1000, 32 | 16}, /* GPTIMER6 */\r
- [123] = {0x103b000, 0x1000, 32 | 16 | 8}, /* L4TA4 */\r
-\r
- [124] = {0x103c000, 0x1000, 32 | 16}, /* GPTIMER7 */\r
- [125] = {0x103d000, 0x1000, 32 | 16 | 8}, /* L4TA4 */\r
-\r
- [126] = {0x103e000, 0x1000, 32 | 16}, /* GPTIMER8 */\r
- [127] = {0x103f000, 0x1000, 32 | 16 | 8}, /* L4TA4 */\r
-\r
- [128] = {0x1040000, 0x1000, 32 | 16}, /* GPTIMER9 */\r
- [129] = {0x1041000, 0x1000, 32 | 16 | 8}, /* L4TA4 */\r
-\r
- [130] = {0x1050000, 0x1000, 32 | 16 | 8}, /* GPIO2 */\r
- [131] = {0x1051000, 0x1000, 32 | 16 | 8}, /* L4TA4 */\r
-\r
- [132] = {0x1052000, 0x1000, 32 | 16 | 8}, /* GPIO3 */\r
- [133] = {0x1053000, 0x1000, 32 | 16 | 8}, /* L4TA4 */\r
-\r
- [134] = {0x1054000, 0x1000, 32 | 16 | 8}, /* GPIO4 */\r
- [135] = {0x1055000, 0x1000, 32 | 16 | 8}, /* L4TA4 */\r
-\r
- [136] = {0x1056000, 0x1000, 32 | 16 | 8}, /* GPIO5 */\r
- [137] = {0x1057000, 0x1000, 32 | 16 | 8}, /* L4TA4 */\r
-\r
- [138] = {0x1058000, 0x1000, 32 | 16 | 8}, /* GPIO6 */\r
- [139] = {0x1059000, 0x1000, 32 | 16 | 8}, /* L4TA4 */\r
-\r
- /*L4 Emulation MEMORY SPACE */\r
- [140] = {0xc006000, 0x800, 32 | 16 | 8}, /* AP */\r
- [141] = {0xc006800, 0x800, 32 | 16 | 8}, /* IP */\r
- [142] = {0xc007000, 0x1000, 32 | 16 | 8}, /* LA */\r
- [143] = {0xc008000, 0x800, 32 | 16 | 8}, /* DAP */\r
-\r
- [144] = {0xc010000, 0x8000, 32 | 16 | 8}, /* MPU Emulation */\r
- [145] = {0xc018000, 0x1000, 32 | 16 | 8}, /* L4TA4 */\r
-\r
- [146] = {0xc019000, 0x8000, 32}, /* TPIU */\r
- [147] = {0xc01a000, 0x1000, 32 | 16 | 8}, /* L4TA4 */\r
-\r
- [148] = {0xc01b000, 0x8000, 32}, /* ETB */\r
- [149] = {0xc01c000, 0x1000, 32 | 16 | 8}, /* L4TA4 */\r
-\r
- [150] = {0xc01d000, 0x8000, 32}, /* DAOCTL */\r
- [151] = {0xc01e000, 0x1000, 32 | 16 | 8}, /* L4TA4 */\r
-\r
- [152] = {0xc706000, 0x2000, 32}, /* PR Region A */\r
- [153] = {0xc706800, 0x800, 32}, /* PR Region B */\r
- [154] = {0xc709000, 0x1000, 32 | 16 | 8}, /* L4TA4 */\r
-\r
- [155] = {0xc710000, 0x1000, 32 | 16 | 8}, /* GPIO1 */\r
- [156] = {0xc711000, 0x1000, 32 | 16 | 8}, /* L4TA4 */\r
-\r
- [157] = {0xc714000, 0x1000, 32 | 16}, /* WDTIMER 2 */\r
- [158] = {0xc715000, 0x1000, 32 | 16 | 8}, /* L4TA4 */\r
-\r
- [159] = {0xc718000, 0x1000, 32 | 16 | 8}, /* GPTIMER 1 */\r
- [160] = {0xc719000, 0x1000, 32 | 16 | 8}, /* L4TA4 */\r
-\r
- [161] = {0xc720000, 0x1000, 32 | 16}, /* 32k timer */\r
- [162] = {0xc721000, 0x1000, 32 | 16 | 8}, /* L4TA4 */\r
-\r
- [163] = {0xc728000, 0x800, 32 | 16 | 8}, /* AP */\r
- [164] = {0xc728800, 0x800, 32 | 16 | 8}, /* IP */\r
- [165] = {0xc729000, 0x1000, 32 | 16 | 8}, /* LA */\r
- [166] = {0xc72a000, 0x800, 32 | 16 | 8}, /* DAP */\r
-\r
+static struct omap_l4_region_s omap3_l4_region[158] = {\r
+ /* L4-Core */\r
+ [ 0] = {0x00002000, 0x1000, 32 | 16 | 8}, /* SCM */\r
+ [ 1] = {0x00003000, 0x1000, 32 | 16 | 8}, /* L4IC */\r
+ [ 2] = {0x00004000, 0x2000, 32 }, /* CM Region A */\r
+ [ 3] = {0x00006000, 0x0800, 32 }, /* CM Region B */\r
+ [ 4] = {0x00007000, 0x1000, 32 | 16 | 8}, /* L4IC */\r
+ [ 5] = {0x00040000, 0x0800, 32 }, /* AP */\r
+ [ 6] = {0x00040800, 0x0800, 32 }, /* IP */\r
+ [ 7] = {0x00041000, 0x1000, 32 }, /* LA */\r
+ [ 8] = {0x0004fc00, 0x0400, 32 | 16 | 8}, /* DSI */\r
+ [ 9] = {0x00050000, 0x0400, 32 | 16 | 8}, /* DISS */\r
+ [ 10] = {0x00050400, 0x0400, 32 | 16 | 8}, /* DISPC */\r
+ [ 11] = {0x00050800, 0x0400, 32 | 16 | 8}, /* RFBI */\r
+ [ 12] = {0x00050c00, 0x0400, 32 | 16 | 8}, /* VENC */\r
+ [ 13] = {0x00051000, 0x1000, 32 | 16 | 8}, /* L4IC */\r
+ [ 14] = {0x00056000, 0x1000, 32 }, /* SDMA */\r
+ [ 15] = {0x00057000, 0x1000, 32 | 16 | 8}, /* L4IC */\r
+ [ 16] = {0x00060000, 0x1000, 16 | 8}, /* I2C3 */\r
+ [ 17] = {0x00061000, 0x1000, 32 | 16 | 8}, /* L4IC */\r
+ [ 18] = {0x00062000, 0x1000, 32 }, /* USBTLL */\r
+ [ 19] = {0x00063000, 0x1000, 32 | 16 | 8}, /* L4IC */\r
+ [ 20] = {0x00064000, 0x1000, 32 }, /* HS USB HOST */\r
+ [ 21] = {0x00065000, 0x1000, 32 | 16 | 8}, /* L4IC */\r
+ [ 22] = {0x0006a000, 0x1000, 32 | 16 | 8}, /* UART1 */\r
+ [ 23] = {0x0006b000, 0x1000, 32 | 16 | 8}, /* L4IC */\r
+ [ 24] = {0x0006c000, 0x1000, 32 | 16 | 8}, /* UART2 */\r
+ [ 25] = {0x0006d000, 0x1000, 32 | 16 | 8}, /* L4IC */\r
+ [ 26] = {0x00070000, 0x1000, 16 | 8}, /* I2C1 */\r
+ [ 27] = {0x00071000, 0x1000, 32 | 16 | 8}, /* L4IC */\r
+ [ 28] = {0x00072000, 0x1000, 16 | 8}, /* I2C2 */\r
+ [ 29] = {0x00073000, 0x1000, 32 | 16 | 8}, /* L4IC */\r
+ [ 30] = {0x00074000, 0x1000, 32 }, /* McBSP1 */\r
+ [ 31] = {0x00075000, 0x1000, 32 | 16 | 8}, /* L4IC */\r
+ [ 32] = {0x00086000, 0x1000, 32 | 16 }, /* GPTIMER10 */\r
+ [ 33] = {0x00087000, 0x1000, 32 | 16 | 8}, /* L4IC */\r
+ [ 34] = {0x00088000, 0x1000, 32 | 16 }, /* GPTIMER11 */\r
+ [ 35] = {0x00089000, 0x1000, 32 | 16 | 8}, /* L4IC */\r
+ [ 36] = {0x00094000, 0x1000, 32 | 16 | 8}, /* MAILBOX */\r
+ [ 37] = {0x00095000, 0x1000, 32 | 16 | 8}, /* L4IC */\r
+ [ 38] = {0x00096000, 0x1000, 32 }, /* McBSP5 */\r
+ [ 39] = {0x00097000, 0x1000, 32 | 16 | 8}, /* L4IC */\r
+ [ 40] = {0x00098000, 0x1000, 32 | 16 | 8}, /* McSPI1 */\r
+ [ 41] = {0x00099000, 0x1000, 32 | 16 | 8}, /* L4IC */\r
+ [ 42] = {0x0009a000, 0x1000, 32 | 16 | 8}, /* McSPI2 */\r
+ [ 43] = {0x0009b000, 0x1000, 32 | 16 | 8}, /* L4IC */\r
+ [ 44] = {0x0009c000, 0x1000, 32 }, /* MMC/SD/SDIO1 */\r
+ [ 45] = {0x0009d000, 0x1000, 32 | 16 | 8}, /* L4IC */\r
+ [ 46] = {0x0009e000, 0x1000, 32 }, /* MS-PRO */\r
+ [ 47] = {0x0009f000, 0x1000, 32 | 16 | 8}, /* L4IC */\r
+ [ 48] = {0x000ab000, 0x1000, 32 }, /* HS USB OTG */\r
+ [ 49] = {0x000ac000, 0x1000, 32 | 16 | 8}, /* L4IC */\r
+ [ 50] = {0x000ad000, 0x1000, 32 }, /* MMC/SD/SDIO3 */\r
+ [ 51] = {0x000ae000, 0x1000, 32 | 16 | 8}, /* L4IC */\r
+ [ 52] = {0x000b2000, 0x1000, 32 }, /* HDQ/1-Wire */\r
+ [ 53] = {0x000b3000, 0x1000, 32 | 16 | 8}, /* L4IC */\r
+ [ 54] = {0x000b4000, 0x1000, 32 }, /* MMC/SD/SDIO2 */\r
+ [ 55] = {0x000b5000, 0x1000, 32 | 16 | 8}, /* L4IC */\r
+ [ 56] = {0x000b6000, 0x1000, 32 }, /* ICR MPU Port */\r
+ [ 57] = {0x000b7000, 0x1000, 32 | 16 | 8}, /* L4IC */\r
+ [ 58] = {0x000b8000, 0x1000, 32 | 16 | 8}, /* McSPI3 */\r
+ [ 59] = {0x000b9000, 0x1000, 32 | 16 | 8}, /* L4IC */\r
+ [ 60] = {0x000ba000, 0x1000, 32 | 16 | 8}, /* McSPI4 */\r
+ [ 61] = {0x000bb000, 0x1000, 32 | 16 | 8}, /* L4IC */\r
+ [ 62] = {0x000bc000, 0x4000, 32 | 16 | 8}, /* Camera ISP */\r
+ [ 63] = {0x000c0000, 0x1000, 32 | 16 | 8}, /* L4IC */\r
+ [ 64] = {0x000c7000, 0x1000, 32 }, /* Modem */\r
+ [ 65] = {0x000c8000, 0x1000, 32 | 16 | 8}, /* L4IC */\r
+ [ 66] = {0x000cd000, 0x1000, 32 }, /* ICR modem port */\r
+ [ 67] = {0x000ce000, 0x1000, 32 | 16 | 8}, /* L4IC */\r
+ /* L4-Wakeup interconnect region A */\r
+ [ 68] = {0x00304000, 0x1000, 32 | 16 }, /* GPTIMER12 */\r
+ [ 69] = {0x00305000, 0x1000, 32 | 16 | 8}, /* L4IC */\r
+ [ 70] = {0x00306000, 0x2000, 32 }, /* PRM region A */\r
+ [ 71] = {0x00308000, 0x0800, 32 }, /* PRM region B */\r
+ [ 72] = {0x00309000, 0x1000, 32 | 16 | 8}, /* L4IC */\r
+ /* L4-Core */\r
+ [ 73] = {0x0030a000, 0x0800, 32 | 16 | 8}, /* TAP */\r
+ [ 74] = {0x0030b000, 0x1000, 32 | 16 | 8}, /* L4IC */\r
+ /* L4-Wakeup interconnect region B */\r
+ [ 75] = {0x00310000, 0x1000, 32 | 16 | 8}, /* GPIO1 */\r
+ [ 76] = {0x00311000, 0x1000, 32 | 16 | 8}, /* L4IC */\r
+ [ 77] = {0x00314000, 0x1000, 32 | 16 }, /* WDTIMER2 */\r
+ [ 78] = {0x00315000, 0x1000, 32 | 16 | 8}, /* L4IC */\r
+ [ 79] = {0x00318000, 0x1000, 32 | 16 }, /* GPTIMER1 */\r
+ [ 80] = {0x00319000, 0x1000, 32 | 16 | 8}, /* L4IC */\r
+ [ 81] = {0x00320000, 0x1000, 32 | 16 }, /* 32K Timer */\r
+ [ 82] = {0x00321000, 0x1000, 32 | 16 | 8}, /* L4IC */\r
+ [ 83] = {0x00328000, 0x0800, 32 | 16 | 8}, /* L4-Wakeup config AP */\r
+ [ 84] = {0x00328800, 0x0800, 32 | 16 | 8}, /* L4-Wakeup config IP L4-Core */\r
+ [ 85] = {0x00329000, 0x1000, 32 | 16 | 8}, /* L4-Wakeup config LA */\r
+ [ 86] = {0x0032a000, 0x0800, 32 | 16 | 8}, /* L4-Wakeup config IP L4-Emu */\r
+ [ 87] = {0x00340000, 0x1000, 32 | 16 | 8}, /* L4IC */\r
+ /* L4-Per */\r
+ [ 88] = {0x01000000, 0x0800, 32 | 16 | 8}, /* AP */\r
+ [ 89] = {0x01000800, 0x0800, 32 | 16 | 8}, /* IP */\r
+ [ 90] = {0x01001000, 0x1000, 32 | 16 | 8}, /* LA */\r
+ [ 91] = {0x01020000, 0x1000, 32 | 16 | 8}, /* UART3 */\r
+ [ 92] = {0x01021000, 0x1000, 32 | 16 | 8}, /* L4IC */\r
+ [ 93] = {0x01022000, 0x1000, 32 }, /* McBSP2 */\r
+ [ 94] = {0x01023000, 0x1000, 32 | 16 | 8}, /* L4IC */\r
+ [ 95] = {0x01024000, 0x1000, 32 }, /* McBSP3 */\r
+ [ 96] = {0x01025000, 0x1000, 32 | 16 | 8}, /* L4IC */\r
+ [ 97] = {0x01026000, 0x1000, 32 }, /* McBSP4 */\r
+ [ 98] = {0x01027000, 0x1000, 32 | 16 | 8}, /* L4IC */\r
+ [ 99] = {0x01028000, 0x1000, 32 }, /* McBSP2 (sidetone) */\r
+ [100] = {0x01029000, 0x1000, 32 | 16 | 8}, /* L4IC */\r
+ [101] = {0x0102a000, 0x1000, 32 }, /* McBSP3 (sidetone) */\r
+ [102] = {0x0102b000, 0x1000, 32 | 16 | 8}, /* L4IC */\r
+ [103] = {0x01030000, 0x1000, 32 | 16 }, /* WDTIMER3 */\r
+ [104] = {0x01031000, 0x1000, 32 | 16 | 8}, /* L4IC */\r
+ [105] = {0x01032000, 0x1000, 32 | 16 }, /* GPTIMER2 */\r
+ [106] = {0x01033000, 0x1000, 32 | 16 | 8}, /* L4IC */\r
+ [107] = {0x01034000, 0x1000, 32 | 16 }, /* GPTIMER3 */\r
+ [108] = {0x01035000, 0x1000, 32 | 16 | 8}, /* L4IC */\r
+ [109] = {0x01036000, 0x1000, 32 | 16 }, /* GPTIMER4 */\r
+ [110] = {0x01037000, 0x1000, 32 | 16 | 8}, /* L4IC */\r
+ [111] = {0x01038000, 0x1000, 32 | 16 }, /* GPTIMER5 */\r
+ [112] = {0x01039000, 0x1000, 32 | 16 | 8}, /* L4IC */\r
+ [113] = {0x0103a000, 0x1000, 32 | 16 }, /* GPTIMER6 */\r
+ [114] = {0x0103b000, 0x1000, 32 | 16 | 8}, /* L4IC */\r
+ [115] = {0x0103c000, 0x1000, 32 | 16 }, /* GPTIMER7 */\r
+ [116] = {0x0103d000, 0x1000, 32 | 16 | 8}, /* L4IC */\r
+ [117] = {0x0103e000, 0x1000, 32 | 16 }, /* GPTIMER8 */\r
+ [118] = {0x0103f000, 0x1000, 32 | 16 | 8}, /* L4IC */\r
+ [119] = {0x01040000, 0x1000, 32 | 16 }, /* GPTIMER9 */\r
+ [120] = {0x01041000, 0x1000, 32 | 16 | 8}, /* L4IC */\r
+ [121] = {0x01050000, 0x1000, 32 | 16 | 8}, /* GPIO2 */\r
+ [122] = {0x01051000, 0x1000, 32 | 16 | 8}, /* L4IC */\r
+ [123] = {0x01052000, 0x1000, 32 | 16 | 8}, /* GPIO3 */\r
+ [124] = {0x01053000, 0x1000, 32 | 16 | 8}, /* L4IC */\r
+ [125] = {0x01054000, 0x1000, 32 | 16 | 8}, /* GPIO4 */\r
+ [126] = {0x01055000, 0x1000, 32 | 16 | 8}, /* L4IC */\r
+ [127] = {0x01056000, 0x1000, 32 | 16 | 8}, /* GPIO5 */\r
+ [128] = {0x01057000, 0x1000, 32 | 16 | 8}, /* L4IC */\r
+ [129] = {0x01058000, 0x1000, 32 | 16 | 8}, /* GPIO6 */\r
+ [130] = {0x01059000, 0x1000, 32 | 16 | 8}, /* L4IC */\r
+ /* L4-Emu */\r
+ [131] = {0x0c006000, 0x0800, 32 | 16 | 8}, /* AP */\r
+ [132] = {0x0c006800, 0x0800, 32 | 16 | 8}, /* IP L4-Core */\r
+ [133] = {0x0c007000, 0x1000, 32 | 16 | 8}, /* LA */\r
+ [134] = {0x0c008000, 0x0800, 32 | 16 | 8}, /* IP DAP */\r
+ [135] = {0x0c010000, 0x8000, 32 | 16 | 8}, /* MPU Emulation */\r
+ [136] = {0x0c018000, 0x1000, 32 | 16 | 8}, /* L4IC */\r
+ [137] = {0x0c019000, 0x1000, 32 }, /* TPIU */\r
+ [138] = {0x0c01a000, 0x1000, 32 | 16 | 8}, /* L4IC */\r
+ [139] = {0x0c01b000, 0x1000, 32 }, /* ETB */\r
+ [140] = {0x0c01c000, 0x1000, 32 | 16 | 8}, /* L4IC */\r
+ [141] = {0x0c01d000, 0x1000, 32 }, /* DAPCTL */\r
+ [142] = {0x0c01e000, 0x1000, 32 | 16 | 8}, /* L4IC */\r
+ [143] = {0x0c706000, 0x2000, 32 }, /* PRM Region A */\r
+ [144] = {0x0c706800, 0x0800, 32 }, /* PRM Region B */\r
+ [145] = {0x0c709000, 0x1000, 32 | 16 | 8}, /* L4IC */\r
+ [146] = {0x0c710000, 0x1000, 32 | 16 | 8}, /* GPIO1 */\r
+ [147] = {0x0c711000, 0x1000, 32 | 16 | 8}, /* L4IC */\r
+ [148] = {0x0c714000, 0x1000, 32 | 16 }, /* WDTIMER2 */\r
+ [149] = {0x0c715000, 0x1000, 32 | 16 | 8}, /* L4IC */\r
+ [150] = {0x0c718000, 0x1000, 32 | 16 | 8}, /* GPTIMER1 */\r
+ [151] = {0x0c719000, 0x1000, 32 | 16 | 8}, /* L4IC */\r
+ [152] = {0x0c720000, 0x1000, 32 | 16 }, /* 32k timer */\r
+ [153] = {0x0c721000, 0x1000, 32 | 16 | 8}, /* L4IC */\r
+ [154] = {0x0c728000, 0x0800, 32 | 16 | 8}, /* L4-Wakeup config AP */\r
+ [155] = {0x0c728800, 0x0800, 32 | 16 | 8}, /* L4-Wakeup config IP L4-Core */\r
+ [156] = {0x0c729000, 0x1000, 32 | 16 | 8}, /* L4-Wakeup config LA */\r
+ [157] = {0x0c72a000, 0x0800, 32 | 16 | 8}, /* L4-Wakeup config IP L4-Emu */\r
};\r
+\r
static struct omap_l4_agent_info_s omap3_l4_agent_info[] = {\r
- {0, 0, 2, 1}, /* System Control module */\r
- {1, 5, 3, 2}, /* CM */\r
- {2, 77, 3, 2}, /* PRM */\r
- {3, 86, 2, 1}, /* WDTIMER 2 */\r
- {4, 3, 2, 1}, /* SCM */\r
- {5, 88, 2, 1}, /* GP TIMER 1 */\r
- {6, 114, 2, 1}, /* GP TIMER 2 */\r
- {7, 116, 2, 1}, /* GP TIMER 3 */\r
- {8, 118, 2, 1}, /* GP TIMER 4 */\r
- {9, 120, 2, 1}, /* GP TIMER 5 */\r
- {10, 122, 2, 1}, /* GP TIMER 6 */\r
- {11, 124, 2, 1}, /* GP TIMER 7 */\r
- {12, 126, 2, 1}, /* GP TIMER 8 */\r
- {13, 128, 2, 1}, /* GP TIMER 9 */\r
- {14, 31, 2, 1}, /* GP TIMER 10 */\r
- {15, 33, 2, 1}, /* GP TIMER 11 */\r
- {16, 80, 2, 1}, /* GP TIMER 12 */\r
- {17, 90, 2, 1}, /* 32K Sync timer */\r
- {18, 21, 2, 1}, /* uart1 */\r
- {19, 23, 2, 1}, /* uart2 */\r
- {20, 100, 2, 1}, /* uart3 */\r
- {21, 8, 5, 4}, /* Display */\r
- {22, 84, 2, 1}, /* GPIO 1 */\r
- {23, 130, 2, 1}, /* GPIO 2 */\r
- {24, 132, 2, 1}, /* GPIO 3 */\r
- {25, 134, 2, 1}, /* GPIO 4 */\r
- {26, 136, 2, 1}, /* GPIO 5 */\r
- {27, 138, 2, 1}, /* GPIO 6 */\r
- {28,82, 2, 1}, /* TAP */\r
- {29,43, 2, 1}, /* MMC1 */\r
- {30,57, 2, 1}, /* MMC2 */\r
- {31,51, 2, 1}, /* MMC3 */\r
- {32,25, 2, 1}, /* I2C1 */\r
- {33,27, 2, 1}, /* I2C2 */\r
- {34,15, 2, 1}, /* I2C3 */\r
- \r
- \r
+ { 0, 0, 2, 1}, /* SCM */\r
+ { 1, 1, 3, 2}, /* CM */\r
+ { 2, 70, 3, 2}, /* PRM */\r
+ { 3, 77, 2, 1}, /* WDTIMER2 */\r
+ { 4, 79, 2, 1}, /* GPTIMER1 */\r
+ { 5, 105, 2, 1}, /* GPTIMER2 */\r
+ { 6, 107, 2, 1}, /* GPTIMER3 */\r
+ { 7, 108, 2, 1}, /* GPTIMER4 */\r
+ { 8, 111, 2, 1}, /* GPTIMER5 */\r
+ { 9, 113, 2, 1}, /* GPTIMER6 */\r
+ {10, 115, 2, 1}, /* GPTIMER7 */\r
+ {11, 116, 2, 1}, /* GPTIMER8 */\r
+ {12, 119, 2, 1}, /* GPTIMER9 */\r
+ {13, 32, 2, 1}, /* GPTIMER10 */\r
+ {14, 34, 2, 1}, /* GPTIMER11 */\r
+ {15, 68, 2, 1}, /* GPTIMER12 */\r
+ {16, 81, 2, 1}, /* 32K Sync timer */\r
+ {17, 22, 2, 1}, /* UART1 */\r
+ {18, 24, 2, 1}, /* UART2 */\r
+ {19, 91, 2, 1}, /* UART3 */\r
+ {20, 8, 6, 4}, /* DSS */\r
+ {21, 75, 2, 1}, /* GPIO1 */\r
+ {22, 121, 2, 1}, /* GPIO2 */\r
+ {23, 123, 2, 1}, /* GPIO3 */\r
+ {24, 124, 2, 1}, /* GPIO4 */\r
+ {25, 127, 2, 1}, /* GPIO5 */\r
+ {26, 129, 2, 1}, /* GPIO6 */\r
+ {27, 73, 2, 1}, /* TAP */\r
+ {28, 44, 2, 1}, /* MMC1 */\r
+ {29, 54, 2, 1}, /* MMC2 */\r
+ {30, 50, 2, 1}, /* MMC3 */\r
+ {31, 26, 2, 1}, /* I2C1 */\r
+ {32, 28, 2, 1}, /* I2C2 */\r
+ {33, 16, 2, 1}, /* I2C3 */\r
};\r
\r
static struct omap_target_agent_s *omap3_l4ta_get(struct omap_l4_s *bus, int cs)\r
struct omap_mpu_state_s *mpu;\r
\r
/*IVA2_PRM Register */\r
- uint32_t rm_rstctrl_iva2; /*0x4830 6050 */\r
- uint32_t rm_rstst_iva2; /*0x4830 6058 */\r
- uint32_t pm_wkdep_iva2; /*0x4830 60C8 */\r
- uint32_t pm_pwstctrl_iva2; /*0x4830 60E0 */\r
- uint32_t pm_pwstst_iva2; /*0x4830 60E4 */\r
- uint32_t pm_prepwstst_iva2; /*0x4830 60E8 */\r
- uint32_t pm_irqstatus_iva2; /*0x4830 60F8 */\r
- uint32_t pm_irqenable_iva2; /*0x4830 60FC */\r
+ uint32_t rm_rstctrl_iva2; /*0x4830 6050 */\r
+ uint32_t rm_rstst_iva2; /*0x4830 6058 */\r
+ uint32_t pm_wkdep_iva2; /*0x4830 60C8 */\r
+ uint32_t pm_pwstctrl_iva2; /*0x4830 60E0 */\r
+ uint32_t pm_pwstst_iva2; /*0x4830 60E4 */\r
+ uint32_t pm_prepwstst_iva2; /*0x4830 60E8 */\r
+ uint32_t prm_irqstatus_iva2; /*0x4830 60F8 */\r
+ uint32_t prm_irqenable_iva2; /*0x4830 60FC */\r
\r
/*OCP_System_Reg_PRM Registerr */\r
uint32_t prm_revision; /*0x4830 6804 */\r
\r
/*CAM_PRM Register */\r
uint32_t rm_rstst_cam; /*0x4830 6f58 */\r
- uint32_t pm_wken_cam; /*0x4830 6fc8 */\r
+ uint32_t pm_wkdep_cam; /*0x4830 6fc8 */\r
uint32_t pm_pwstctrl_cam; /*0x4830 6fe0 */\r
uint32_t pm_pwstst_cam; /*0x4830 6fe4 */\r
uint32_t pm_prepwstst_cam; /*0x4830 6fe8 */\r
\r
/*USBHOST_PRM Register */\r
uint32_t rm_rstst_usbhost; /*0x4830 7458 */\r
- uint32_t rm_wken_usbhost; /*0x4830 74a0 */\r
- uint32_t rm_mpugrpsel_usbhost; /*0x4830 74a4 */\r
- uint32_t rm_iva2grpsel_usbhost; /*0x4830 74a8 */\r
- uint32_t rm_wkst_usbhost; /*0x4830 74b0 */\r
- uint32_t rm_wkdep_usbhost; /*0x4830 74c8 */\r
- uint32_t rm_pwstctrl_usbhost; /*0x4830 74e0 */\r
- uint32_t rm_pwstst_usbhost; /*0x4830 74e4 */\r
- uint32_t rm_prepwstst_usbhost; /*0x4830 74e8 */\r
+ uint32_t pm_wken_usbhost; /*0x4830 74a0 */\r
+ uint32_t pm_mpugrpsel_usbhost; /*0x4830 74a4 */\r
+ uint32_t pm_iva2grpsel_usbhost; /*0x4830 74a8 */\r
+ uint32_t pm_wkst_usbhost; /*0x4830 74b0 */\r
+ uint32_t pm_wkdep_usbhost; /*0x4830 74c8 */\r
+ uint32_t pm_pwstctrl_usbhost; /*0x4830 74e0 */\r
+ uint32_t pm_pwstst_usbhost; /*0x4830 74e4 */\r
+ uint32_t pm_prepwstst_usbhost; /*0x4830 74e8 */\r
\r
};\r
\r
s->pm_pwstctrl_iva2 = 0xff0f07;\r
s->pm_pwstst_iva2 = 0xff7;\r
s->pm_prepwstst_iva2 = 0x0;\r
- s->pm_irqstatus_iva2 = 0x0;\r
- s->pm_irqenable_iva2 = 0x0;\r
+ s->prm_irqstatus_iva2 = 0x0;\r
+ s->prm_irqenable_iva2 = 0x0;\r
\r
s->prm_revision = 0x10;\r
s->prm_sysconfig = 0x1;\r
s->pm_prepwstst_dss = 0x0;\r
\r
s->rm_rstst_cam = 0x1;\r
- s->pm_wken_cam = 0x16;\r
+ s->pm_wkdep_cam = 0x16;\r
s->pm_pwstctrl_cam = 0x30107;\r
s->pm_pwstst_cam = 0x3;\r
s->pm_prepwstst_cam = 0x0;\r
s->pm_prepwstst_neon = 0x0;\r
\r
s->rm_rstst_usbhost = 0x1;\r
- s->rm_wken_usbhost = 0x1;\r
- s->rm_mpugrpsel_usbhost = 0x1;\r
- s->rm_iva2grpsel_usbhost = 0x1;\r
- s->rm_wkst_usbhost = 0x0;\r
- s->rm_wkdep_usbhost = 0x17;\r
- s->rm_pwstctrl_usbhost = 0x30107;\r
- s->rm_pwstst_usbhost = 0x3;\r
- s->rm_prepwstst_usbhost = 0x0;\r
+ s->pm_wken_usbhost = 0x1;\r
+ s->pm_mpugrpsel_usbhost = 0x1;\r
+ s->pm_iva2grpsel_usbhost = 0x1;\r
+ s->pm_wkst_usbhost = 0x0;\r
+ s->pm_wkdep_usbhost = 0x17;\r
+ s->pm_pwstctrl_usbhost = 0x30107;\r
+ s->pm_pwstst_usbhost = 0x3;\r
+ s->pm_prepwstst_usbhost = 0x0;\r
\r
}\r
\r
static uint32_t omap3_prm_read(void *opaque, target_phys_addr_t addr)\r
{\r
- struct omap3_prm_s *s = (struct omap3_prm_s *) opaque;\r
-\r
- switch (addr)\r
- {\r
- case 0x50:\r
- return s->rm_rstctrl_iva2;\r
- case 0x58:\r
- return s->rm_rstst_iva2;\r
- case 0xc8:\r
- return s->pm_wkdep_iva2 ;\r
- case 0xe0:\r
- return s->pm_pwstctrl_iva2;\r
- case 0xe4:\r
- return s->pm_pwstst_iva2;\r
- case 0xe8:\r
- return s->pm_prepwstst_iva2;\r
- case 0xf8:\r
- return s->pm_irqstatus_iva2;\r
- case 0xfc:\r
- return s->pm_irqenable_iva2;\r
-\r
- case 0x804:\r
- return s->prm_revision;\r
- case 0x814:\r
- return s->prm_sysconfig;\r
- case 0x818:\r
- return s->prm_irqstatus_mpu;\r
- case 0x81c:\r
- return s->prm_irqenable_mpu;\r
-\r
- case 0x958:\r
- return s->rm_rstst_mpu;\r
- case 0x9c8:\r
- return s->pm_wkdep_mpu;\r
- case 0x9d4:\r
- return s->pm_evgenctrl_mpu;\r
- case 0x9d8:\r
- return s->pm_evgenontim_mpu;\r
- case 0x9dc:\r
- return s->pm_evgenofftim_mpu;\r
- case 0x9e0:\r
- return s->pm_pwstctrl_mpu;\r
- case 0x9e4:\r
- return s->pm_pwstst_mpu;\r
- case 0x9e8:\r
- return s->pm_perpwstst_mpu;\r
-\r
- case 0xa58:\r
- return s->rm_rstst_core;\r
- case 0xaa0:\r
- return s->pm_wken1_core;\r
- case 0xaa4:\r
- return s->pm_mpugrpsel1_core;\r
- case 0xaa8:\r
- return s->pm_iva2grpsel1_core;\r
- case 0xab0:\r
- return s->pm_wkst1_core;\r
- case 0xab8:\r
- return s->pm_wkst3_core;\r
- case 0xae0:\r
- return s->pm_pwstctrl_core;\r
- case 0xae4:\r
- return s->pm_pwstst_core;\r
- case 0xae8:\r
- return s->pm_prepwstst_core;\r
-\r
- case 0xb58:\r
- return s->rm_rstst_sgx;\r
- case 0xbc8:\r
- return s->pm_wkdep_sgx;\r
- case 0xbe0:\r
- return s->pm_pwstctrl_sgx;\r
- case 0xbe4:\r
- return s->pm_pwstst_sgx;\r
- case 0xbe8:\r
- return s->pm_prepwstst_sgx;\r
+ struct omap3_prm_s *s = (struct omap3_prm_s *)opaque;\r
\r
- \r
- case 0xca0:\r
- return s->pm_wken_wkup;\r
- case 0xca4:\r
- return s->pm_mpugrpsel_wkup ;\r
- case 0xca8:\r
- return s->pm_iva2grpsel_wkup ;\r
- case 0xcb0:\r
- return s->pm_wkst_wkup ;\r
-\r
- \r
- case 0xd40:\r
- return s->prm_clksel;\r
- case 0xd70:\r
- return s->prm_clkout_ctrl;\r
-\r
- case 0xe58:\r
- return s->rm_rstst_dss;\r
- case 0xea0:\r
- return s->pm_wken_dss;\r
- case 0xec8:\r
- return s->pm_wkdep_dss;\r
- case 0xee0:\r
- return s->pm_pwstctrl_dss;\r
- case 0xee4:\r
- return s->pm_pwstst_dss;\r
- case 0xee8:\r
- return s->pm_prepwstst_dss;\r
-\r
- case 0xf58:\r
- return s->rm_rstst_cam;\r
- case 0xfc8:\r
- return s->pm_wken_cam ;\r
- case 0xfe0:\r
- return s->pm_pwstctrl_cam;\r
- case 0xfe4:\r
- return s->pm_pwstst_cam;\r
- case 0xfe8:\r
- return s->pm_prepwstst_cam;\r
-\r
- case 0x1058:\r
- return s->rm_rstst_per;\r
- case 0x10a0:\r
- return s->pm_wken_per ;\r
- case 0x10a4:\r
- return s->pm_mpugrpsel_per;\r
- case 0x10a8:\r
- return s->pm_iva2grpsel_per;\r
- case 0x10b0:\r
- return s->pm_wkst_per;\r
- case 0x10c8:\r
- return s->pm_wkdep_per;\r
- case 0x10e0:\r
- return s->pm_pwstctrl_per;\r
- case 0x10e4:\r
- return s->pm_pwstst_per;\r
- case 0x10e8:\r
- return s->pm_perpwstst_per;\r
-\r
- \r
- case 0x1220:\r
- return s->prm_vc_smps_sa;\r
- case 0x1224:\r
- return s->prm_vc_smps_vol_ra ;\r
- case 0x1228:\r
- return s->prm_vc_smps_cmd_ra ;\r
- case 0x122c:\r
- return s->prm_vc_cmd_val_0 ;\r
- case 0x1230:\r
- return s->prm_vc_cmd_val_1 ;\r
- case 0x1234:\r
- return s->prm_vc_hc_conf;\r
- case 0x1238:\r
- return s->prm_vc_i2c_cfg;\r
- case 0x123c:\r
- return s->prm_vc_bypass_val;\r
- case 0x1250:\r
- return s->prm_rstctrl;\r
- case 0x1254:\r
- return s->prm_rsttimer;\r
- case 0x1258:\r
- return s->prm_rstst;\r
- case 0x1260:\r
- return s->prm_voltctrl;\r
- case 0x1264:\r
- return s->prm_sram_pcharge; \r
- case 0x1270:\r
- return s->prm_clksrc_ctrl;\r
- case 0x1280:\r
- return s->prm_obs;\r
- case 0x1290:\r
- return s->prm_voltsetup1;\r
- case 0x1294:\r
- return s->prm_voltoffset;\r
- case 0x1298:\r
- return s->prm_clksetup;\r
- case 0x129c:\r
- return s->prm_polctrl;\r
- case 0x12a0:\r
- return s->prm_voltsetup2;\r
-\r
- case 0x1358:\r
- return s->rm_rstst_neon;\r
- case 0x13c8:\r
- return s->pm_wkdep_neon ;\r
- case 0x13e0:\r
- return s->pm_pwstctrl_neon;\r
- case 0x13e4:\r
- return s->pm_pwstst_neon;\r
- case 0x13e8:\r
- return s->pm_prepwstst_neon;\r
-\r
- case 0x1458:\r
- return s->rm_rstst_usbhost;\r
- case 0x14a0:\r
- return s->rm_wken_usbhost ;\r
- case 0x14a4:\r
- return s->rm_mpugrpsel_usbhost;\r
- case 0x14a8:\r
- return s->rm_iva2grpsel_usbhost;\r
- case 0x14b0:\r
- return s->rm_wkst_usbhost;\r
- case 0x14c8:\r
- return s->rm_wkdep_usbhost;\r
- case 0x14e0:\r
- return s->rm_pwstctrl_usbhost;\r
- case 0x14e4:\r
- return s->rm_pwstst_usbhost;\r
- case 0x14e8:\r
- return s->rm_prepwstst_usbhost;\r
-\r
- default:\r
- printf("prm READ offset %x\n",addr);\r
- exit(-1);\r
+ switch (addr) {\r
+ /* IVA2_PRM */\r
+ case 0x0050: return s->rm_rstctrl_iva2;\r
+ case 0x0058: return s->rm_rstst_iva2;\r
+ case 0x00c8: return s->pm_wkdep_iva2;\r
+ case 0x00e0: return s->pm_pwstctrl_iva2;\r
+ case 0x00e4: return s->pm_pwstst_iva2;\r
+ case 0x00e8: return s->pm_prepwstst_iva2;\r
+ case 0x00f8: return s->prm_irqstatus_iva2;\r
+ case 0x00fc: return s->prm_irqenable_iva2;\r
+ /* OCP_System_Reg_PRM */\r
+ case 0x0804: return s->prm_revision;\r
+ case 0x0814: return s->prm_sysconfig;\r
+ case 0x0818: return s->prm_irqstatus_mpu;\r
+ case 0x081c: return s->prm_irqenable_mpu;\r
+ /* MPU_PRM */\r
+ case 0x0958: return s->rm_rstst_mpu;\r
+ case 0x09c8: return s->pm_wkdep_mpu;\r
+ case 0x09d4: return s->pm_evgenctrl_mpu;\r
+ case 0x09d8: return s->pm_evgenontim_mpu;\r
+ case 0x09dc: return s->pm_evgenofftim_mpu;\r
+ case 0x09e0: return s->pm_pwstctrl_mpu;\r
+ case 0x09e4: return s->pm_pwstst_mpu;\r
+ case 0x09e8: return s->pm_perpwstst_mpu;\r
+ /* CORE_PRM */\r
+ case 0x0a58: return s->rm_rstst_core;\r
+ case 0x0aa0: return s->pm_wken1_core;\r
+ case 0x0aa4: return s->pm_mpugrpsel1_core;\r
+ case 0x0aa8: return s->pm_iva2grpsel1_core;\r
+ case 0x0ab0: return s->pm_wkst1_core;\r
+ case 0x0ab8: return s->pm_wkst3_core;\r
+ case 0x0ae0: return s->pm_pwstctrl_core;\r
+ case 0x0ae4: return s->pm_pwstst_core;\r
+ case 0x0ae8: return s->pm_prepwstst_core;\r
+ case 0x0af0: return s->pm_wken3_core;\r
+ case 0x0af4: return s->pm_iva2grpsel3_core;\r
+ case 0x0af8: return s->pm_mpugrpsel3_core;\r
+ /* SGX_PRM */\r
+ case 0x0b58: return s->rm_rstst_sgx;\r
+ case 0x0bc8: return s->pm_wkdep_sgx;\r
+ case 0x0be0: return s->pm_pwstctrl_sgx;\r
+ case 0x0be4: return s->pm_pwstst_sgx;\r
+ case 0x0be8: return s->pm_prepwstst_sgx;\r
+ /* WKUP_PRM */\r
+ case 0x0ca0: return s->pm_wken_wkup;\r
+ case 0x0ca4: return s->pm_mpugrpsel_wkup;\r
+ case 0x0ca8: return s->pm_iva2grpsel_wkup;\r
+ case 0x0cb0: return s->pm_wkst_wkup;\r
+ /* Clock_Control_Reg_PRM */\r
+ case 0x0d40: return s->prm_clksel;\r
+ case 0x0d70: return s->prm_clkout_ctrl;\r
+ /* DSS_PRM */\r
+ case 0x0e58: return s->rm_rstst_dss;\r
+ case 0x0ea0: return s->pm_wken_dss;\r
+ case 0x0ec8: return s->pm_wkdep_dss;\r
+ case 0x0ee0: return s->pm_pwstctrl_dss;\r
+ case 0x0ee4: return s->pm_pwstst_dss;\r
+ case 0x0ee8: return s->pm_prepwstst_dss;\r
+ /* CAM_PRM */\r
+ case 0x0f58: return s->rm_rstst_cam;\r
+ case 0x0fc8: return s->pm_wkdep_cam;\r
+ case 0x0fe0: return s->pm_pwstctrl_cam;\r
+ case 0x0fe4: return s->pm_pwstst_cam;\r
+ case 0x0fe8: return s->pm_prepwstst_cam;\r
+ /* PER_PRM */\r
+ case 0x1058: return s->rm_rstst_per;\r
+ case 0x10a0: return s->pm_wken_per;\r
+ case 0x10a4: return s->pm_mpugrpsel_per;\r
+ case 0x10a8: return s->pm_iva2grpsel_per;\r
+ case 0x10b0: return s->pm_wkst_per;\r
+ case 0x10c8: return s->pm_wkdep_per;\r
+ case 0x10e0: return s->pm_pwstctrl_per;\r
+ case 0x10e4: return s->pm_pwstst_per;\r
+ case 0x10e8: return s->pm_perpwstst_per;\r
+ /* EMU_PRM */\r
+ case 0x1158: return s->rm_rstst_emu;\r
+ case 0x11e4: return s->pm_pwstst_emu;\r
+ /* Global_Reg_PRM */\r
+ case 0x1220: return s->prm_vc_smps_sa;\r
+ case 0x1224: return s->prm_vc_smps_vol_ra;\r
+ case 0x1228: return s->prm_vc_smps_cmd_ra;\r
+ case 0x122c: return s->prm_vc_cmd_val_0;\r
+ case 0x1230: return s->prm_vc_cmd_val_1;\r
+ case 0x1234: return s->prm_vc_hc_conf;\r
+ case 0x1238: return s->prm_vc_i2c_cfg;\r
+ case 0x123c: return s->prm_vc_bypass_val;\r
+ case 0x1250: return s->prm_rstctrl;\r
+ case 0x1254: return s->prm_rsttimer;\r
+ case 0x1258: return s->prm_rstst;\r
+ case 0x1260: return s->prm_voltctrl;\r
+ case 0x1264: return s->prm_sram_pcharge; \r
+ case 0x1270: return s->prm_clksrc_ctrl;\r
+ case 0x1280: return s->prm_obs;\r
+ case 0x1290: return s->prm_voltsetup1;\r
+ case 0x1294: return s->prm_voltoffset;\r
+ case 0x1298: return s->prm_clksetup;\r
+ case 0x129c: return s->prm_polctrl;\r
+ case 0x12a0: return s->prm_voltsetup2;\r
+ /* NEON_PRM */\r
+ case 0x1358: return s->rm_rstst_neon;\r
+ case 0x13c8: return s->pm_wkdep_neon;\r
+ case 0x13e0: return s->pm_pwstctrl_neon;\r
+ case 0x13e4: return s->pm_pwstst_neon;\r
+ case 0x13e8: return s->pm_prepwstst_neon;\r
+ /* USBHOST_PRM */\r
+ case 0x1458: return s->rm_rstst_usbhost;\r
+ case 0x14a0: return s->pm_wken_usbhost;\r
+ case 0x14a4: return s->pm_mpugrpsel_usbhost;\r
+ case 0x14a8: return s->pm_iva2grpsel_usbhost;\r
+ case 0x14b0: return s->pm_wkst_usbhost;\r
+ case 0x14c8: return s->pm_wkdep_usbhost;\r
+ case 0x14e0: return s->pm_pwstctrl_usbhost;\r
+ case 0x14e4: return s->pm_pwstst_usbhost;\r
+ case 0x14e8: return s->pm_prepwstst_usbhost;\r
+ default:\r
+ OMAP_BAD_REG(addr);\r
+ return 0;\r
}\r
}\r
\r
omap_clk_setrate(omap_findclk(s->mpu, "omap3_sys_clk"), 1, 1);\r
else if ((value & 0xd0) == 0x80)\r
omap_clk_setrate(omap_findclk(s->mpu, "omap3_sys_clk"), 2, 1);\r
- //OMAP3_DEBUG(("omap3_sys_clk %d \n",omap_clk_getrate(omap_findclk(s->mpu, "omap3_sys_clk"))));\r
}\r
+\r
static void omap3_prm_write(void *opaque, target_phys_addr_t addr,\r
uint32_t value)\r
{\r
- struct omap3_prm_s *s = (struct omap3_prm_s *) opaque;\r
+ struct omap3_prm_s *s = (struct omap3_prm_s *)opaque;\r
\r
- switch (addr)\r
- {\r
- case 0xc8:\r
- s->pm_wkdep_iva2 = value & 0xb3;\r
- break;\r
- case 0xe0:\r
- s->pm_pwstctrl_iva2 = value & 0xff0f0f;\r
- break;\r
- case 0xe4:\r
- s->pm_pwstst_iva2 = value & 0x100ff7;\r
- break;\r
- case 0xe8:\r
- s->pm_prepwstst_iva2 = value & 0xff7;\r
- break;\r
- case 0x814:\r
- s->prm_sysconfig = value &0x1;\r
- break;\r
- case 0x818:\r
- s->prm_irqstatus_mpu = 0x0;\r
- break;\r
- case 0x81c:\r
- s->prm_irqenable_mpu = 0x3ffffff;\r
- break;\r
- case 0x9c8:\r
- s->pm_wkdep_mpu = value & 0xa5;;\r
- break;\r
- case 0x9e0:\r
- s->pm_pwstctrl_mpu = value & 0x3010f;\r
- break;\r
- case 0x9e4:\r
- s->pm_pwstst_mpu = value & 0x1000c7;\r
- break;\r
- case 0x9e8:\r
- s->pm_perpwstst_mpu = value & 0xc7;\r
- break;\r
- case 0xae0:\r
- s->pm_pwstctrl_core = value & 0xf0307;\r
- break;\r
- case 0xae4:\r
- s->pm_pwstst_core = value & 0x1000f3;\r
- break;\r
- case 0xae8:\r
- s->pm_prepwstst_core = value & 0xf7;\r
- break;\r
- case 0xbc8:\r
- s->pm_wkdep_sgx = value & 0x17;\r
- break;\r
- case 0xbe0:\r
- s->pm_pwstctrl_sgx = value & 0x30107;\r
- break;\r
- case 0xbe4:\r
- s->pm_pwstst_sgx = value & 0x100003;;\r
- break;\r
- case 0xbe8:\r
- s->pm_prepwstst_sgx = value & 0x3;\r
- break; \r
- case 0xca0:\r
- s->pm_wken_wkup = value & 0x3cb;\r
- break;\r
- case 0xca4:\r
- s->pm_mpugrpsel_wkup = value & 0x3cb;\r
- break;\r
- case 0xca8:\r
- s->pm_iva2grpsel_wkup = value & 0x3cb;\r
- break;\r
- case 0xcac:\r
- s->pm_wkst_wkup = value & 0x3cb;\r
- break;\r
- case 0xd40:\r
- s->prm_clksel = value & 0x7;\r
- break;\r
- case 0xec8:\r
- s->pm_wkdep_dss = value & 0x16;\r
- break;\r
- case 0xee0:\r
- s->pm_pwstctrl_dss = value & 0x30107;\r
- break;\r
- case 0xee4:\r
- s->pm_pwstst_dss = value & 0x100003;\r
- break;\r
- case 0xee8:\r
- s->pm_prepwstst_dss = value &0x3;\r
- break;\r
- case 0xfc8:\r
- s->pm_wken_cam = value & 0x16;\r
- break;\r
- case 0xfe0:\r
- s->pm_pwstctrl_cam = value & 0x30107;\r
- break;\r
- case 0xfe4:\r
- s->pm_pwstst_cam = value & 0x100003;\r
- break;\r
- case 0xfe8:\r
- s->pm_prepwstst_cam = value & 0x3;\r
- break;\r
- case 0x10c8:\r
- s->pm_wkdep_per = value & 0x17;\r
- break;\r
- case 0x10a0:\r
- s->pm_wken_per = value & 0x3efff;\r
- break;\r
- case 0x10e0:\r
- s->pm_pwstctrl_per = value & 0x30107;\r
- break;\r
- case 0x10e4:\r
- s->pm_pwstst_per = value & 0x100003;;\r
- break;\r
- case 0x10e8:\r
- s->pm_perpwstst_per = value & 0x3;\r
- break; \r
- case 0x1220:\r
- s->prm_vc_smps_sa = value & 0x7f007f;\r
- break;\r
- case 0x1224:\r
- s->prm_vc_smps_vol_ra = value & 0xff00ff;\r
- break;\r
- case 0x1228:\r
- s->prm_vc_smps_cmd_ra = value & 0xff00ff;\r
- break;\r
- case 0x122c:\r
- s->prm_vc_cmd_val_0 = value ;\r
- break;\r
- case 0x1230:\r
- s->prm_vc_cmd_val_1 = value ;\r
- break;\r
- case 0x1234:\r
- s->prm_vc_hc_conf = value & 0x1f001f;\r
- break;\r
- case 0x1238:\r
- s->prm_vc_i2c_cfg = value & 0x3f;\r
- break;\r
- case 0x123c:\r
- s->prm_vc_bypass_val = value;\r
- break;\r
- case 0x1250:\r
- s->prm_rstctrl = value & 0x7;\r
- /*TODO: Software reset*/\r
- break;\r
- case 0x1254:\r
- s->prm_rsttimer = value & 0x1fff;\r
- break;\r
- case 0x1258:\r
- s->prm_rstst = value & 0x7ff;\r
- break;\r
- case 0x1260:\r
- s->prm_voltctrl = value & 0x1f;\r
- break;\r
- case 0x1264:\r
- s->prm_sram_pcharge = value &0xff;\r
- break;\r
- case 0x1270:\r
- s->prm_clksrc_ctrl = value & (0xd8);\r
- omap3_prm_clksrc_ctrl_update(s, s->prm_clksrc_ctrl);\r
- break;\r
- case 0x1290:\r
- s->prm_voltsetup1 = value;\r
- break;\r
- case 0x1294:\r
- s->prm_voltoffset = value&0xffff;\r
- break;\r
- case 0x1298:\r
- s->prm_clksetup = value&0xffff;\r
- break;\r
- case 0x129c:\r
- s->prm_polctrl = value&0xf;\r
- break;\r
- case 0x12a0:\r
- s->prm_voltsetup2 = value & 0xffff;\r
- break;\r
- case 0x13c8:\r
- s->pm_wkdep_neon = value & 0x2;\r
- break;\r
- case 0x13e0:\r
- s->pm_pwstctrl_neon = value & 0x7;\r
- break;\r
- case 0x13e4:\r
- s->pm_pwstst_neon = value & 0x100003;\r
- break;\r
- case 0x13e8:\r
- s->pm_prepwstst_neon = value & 0x3;\r
- break;\r
- case 0x14a0:\r
- s->rm_wken_usbhost = value &0x1;\r
- break;\r
- case 0x14c8:\r
- s->rm_wkdep_usbhost = value & 0x17;\r
- break;\r
- case 0x14e0:\r
- s->rm_pwstctrl_usbhost = value & 0x30117;\r
- break;\r
- case 0x14e4:\r
- s->rm_pwstst_usbhost = value & 0x100002;\r
- break;\r
- case 0x14e8:\r
- s->rm_prepwstst_usbhost = value & 0x2;\r
- break;\r
-\r
- default:\r
- printf("omap3_prm_write addr %x value %x \n", addr, value);\r
- exit(-1);\r
+ switch (addr) {\r
+ /* IVA2_PRM */\r
+ case 0x0050: s->rm_rstctrl_iva2 = value & 0x7; break;\r
+ case 0x0058: s->rm_rstst_iva2 &= ~(value & 0x3f0f); break;\r
+ case 0x00c8: s->pm_wkdep_iva2 = value & 0xb3; break;\r
+ case 0x00e0: s->pm_pwstctrl_iva2 = 0xcff000 | (value & 0x300f0f); break;\r
+ case 0x00e4: OMAP_RO_REG(addr); break;\r
+ case 0x00e8: s->pm_prepwstst_iva2 = value & 0xff7;\r
+ case 0x00f8: s->prm_irqstatus_iva2 &= ~(value & 0x7); break;\r
+ case 0x00fc: s->prm_irqenable_iva2 = value & 0x7; break;\r
+ /* OCP_System_Reg_PRM */\r
+ case 0x0804: OMAP_RO_REG(addr); break;\r
+ case 0x0814: s->prm_sysconfig = value & 0x1; break;\r
+ case 0x0818: s->prm_irqstatus_mpu &= ~(value & 0x03c003fd); break;\r
+ case 0x081c: s->prm_irqenable_mpu = value & 0x03c003fd; break;\r
+ /* MPU_PRM */\r
+ case 0x0958: s->rm_rstst_mpu &= ~(value & 0x080f); break;\r
+ case 0x09c8: s->pm_wkdep_mpu = value & 0xa5; break;\r
+ case 0x09d4: s->pm_evgenctrl_mpu = value & 0x1f; break;\r
+ case 0x09d8: s->pm_evgenontim_mpu = value; break;\r
+ case 0x09dc: s->pm_evgenofftim_mpu = value; break;\r
+ case 0x09e0: s->pm_pwstctrl_mpu = value & 0x3010f; break;\r
+ case 0x09e4: OMAP_RO_REG(addr); break;\r
+ case 0x09e8: s->pm_perpwstst_mpu = value & 0xc7; break;\r
+ /* CORE_PRM */\r
+ case 0x0a58: s->rm_rstst_core &= ~(value & 0x7); break;\r
+ case 0x0aa0: s->pm_wken1_core = 0x80000008 | (value & 0x433ffe10); break;\r
+ case 0x0aa4: s->pm_mpugrpsel1_core = 0x80000008 | (value & 0x433ffe10); break;\r
+ case 0x0aa8: s->pm_iva2grpsel1_core = 0x80000008 | (value & 0x433ffe10); break;\r
+ case 0x0ab0: s->pm_wkst1_core = value & 0x433ffe10; break;\r
+ case 0x0ab8: s->pm_wkst3_core &= ~(value & 0x4); break;\r
+ case 0x0ae0: s->pm_pwstctrl_core = (value & 0x0f031f); break;\r
+ case 0x0ae4: OMAP_RO_REG(addr); break;\r
+ case 0x0ae8: s->pm_prepwstst_core = value & 0xf7; break;\r
+ case 0x0af0: s->pm_wken3_core = value & 0x4; break;\r
+ case 0x0af4: s->pm_iva2grpsel3_core = value & 0x4; break;\r
+ case 0x0af8: s->pm_mpugrpsel3_core = value & 0x4; break;\r
+ /* SGX_PRM */\r
+ case 0x0b58: s->rm_rstst_sgx &= ~(value & 0xf); break;\r
+ case 0x0bc8: s->pm_wkdep_sgx = value & 0x16; break;\r
+ case 0x0be0: s->pm_pwstctrl_sgx = 0x030104 | (value & 0x3); break;\r
+ case 0x0be4: OMAP_RO_REG(addr); break;\r
+ case 0x0be8: s->pm_prepwstst_sgx = value & 0x3; break;\r
+ /* WKUP_PRM */\r
+ case 0x0ca0: s->pm_wken_wkup = 0x2 | (value & 0x0103c9); break;\r
+ case 0x0ca4: s->pm_mpugrpsel_wkup = 0x0102 | (value & 0x02c9); break;\r
+ case 0x0ca8: s->pm_iva2grpsel_wkup = value & 0x03cb; break;\r
+ case 0x0cb0: s->pm_wkst_wkup &= ~(value & 0x0103cb); break;\r
+ /* Clock_Control_Reg_PRM */\r
+ case 0x0d40: \r
+ s->prm_clksel = value & 0x7;\r
+ fprintf(stderr, "%s PRM_CLKSEL = 0x%x\n", __FUNCTION__,\r
+ s->prm_clksel);\r
+ /* TODO: update clocks */\r
+ break;\r
+ case 0x0d70:\r
+ s->prm_clkout_ctrl = value & 0x80;\r
+ fprintf(stderr, "%s PRM_CLKOUT_CTRL = 0x%x\n", __FUNCTION__,\r
+ s->prm_clkout_ctrl);\r
+ /* TODO: check do we need to update something */\r
+ break;\r
+ /* DSS_PRM */\r
+ case 0x0e58: s->rm_rstst_dss &= ~(value & 0xf); break;\r
+ case 0x0ea0: s->pm_wken_dss = value & 1; break;\r
+ case 0x0ec8: s->pm_wkdep_dss = value & 0x16; break;\r
+ case 0x0ee0: s->pm_pwstctrl_dss = 0x030104 | (value & 3); break;\r
+ case 0x0ee4: OMAP_RO_REG(addr); break;\r
+ case 0x0ee8: s->pm_prepwstst_dss = value & 3; break;\r
+ /* CAM_PRM */\r
+ case 0x0f58: s->rm_rstst_cam &= (value & 0xf); break;\r
+ case 0x0fc8: s->pm_wkdep_cam = value & 0x16; break;\r
+ case 0x0fe0: s->pm_pwstctrl_cam = 0x030104 | (value & 3); break;\r
+ case 0x0fe4: OMAP_RO_REG(addr); break;\r
+ case 0x0fe8: s->pm_prepwstst_cam = value & 0x3; break;\r
+ /* PER_PRM */\r
+ case 0x1058: s->rm_rstst_per &= ~(value & 0xf); break;\r
+ case 0x10a0: s->pm_wken_per = value & 0x03efff; break;\r
+ case 0x10a4: s->pm_mpugrpsel_per = value & 0x03efff; break;\r
+ case 0x10a8: s->pm_iva2grpsel_per = value & 0x03efff; break;\r
+ case 0x10b0: s->pm_wkst_per &= ~(value & 0x03efff); break;\r
+ case 0x10c8: s->pm_wkdep_per = value & 0x17; break;\r
+ case 0x10e0: s->pm_pwstctrl_per = 0x030100 | (value & 7); break;\r
+ case 0x10e4: OMAP_RO_REG(addr); break;\r
+ case 0x10e8: s->pm_perpwstst_per = value & 0x7; break;\r
+ /* EMU_PRM */\r
+ case 0x1158: s->rm_rstst_emu &= ~(value & 7); break;\r
+ case 0x11e4: OMAP_RO_REG(addr); break;\r
+ /* Global_Reg_PRM */\r
+ case 0x1220: s->prm_vc_smps_sa = value & 0x7f007f; break;\r
+ case 0x1224: s->prm_vc_smps_vol_ra = value & 0xff00ff; break;\r
+ case 0x1228: s->prm_vc_smps_cmd_ra = value & 0xff00ff; break;\r
+ case 0x122c: s->prm_vc_cmd_val_0 = value; break;\r
+ case 0x1230: s->prm_vc_cmd_val_1 = value; break;\r
+ case 0x1234: s->prm_vc_hc_conf = value & 0x1f001f; break;\r
+ case 0x1238: s->prm_vc_i2c_cfg = value & 0x3f; break;\r
+ case 0x123c: s->prm_vc_bypass_val = value & 0x01ffff7f; break;\r
+ case 0x1250: s->prm_rstctrl = 0; break; /* TODO: resets */\r
+ case 0x1254: s->prm_rsttimer = value & 0x1fff; break;\r
+ case 0x1258: s->prm_rstst &= ~(value & 0x7fb); break;\r
+ case 0x1260: s->prm_voltctrl = value & 0x1f; break;\r
+ case 0x1264: s->prm_sram_pcharge = value & 0xff; break;\r
+ case 0x1270:\r
+ s->prm_clksrc_ctrl = value & (0xd8);\r
+ omap3_prm_clksrc_ctrl_update(s, s->prm_clksrc_ctrl);\r
+ /* TODO: update SYSCLKSEL bits */\r
+ break;\r
+ case 0x1280: OMAP_RO_REG(addr); break;\r
+ case 0x1290: s->prm_voltsetup1 = value; break;\r
+ case 0x1294: s->prm_voltoffset = value & 0xffff; break;\r
+ case 0x1298: s->prm_clksetup = value & 0xffff; break;\r
+ case 0x129c: s->prm_polctrl = value & 0xf; break;\r
+ case 0x12a0: s->prm_voltsetup2 = value & 0xffff; break;\r
+ /* NEON_PRM */\r
+ case 0x1358: s->rm_rstst_neon &= ~(value & 0xf); break;\r
+ case 0x13c8: s->pm_wkdep_neon = value & 0x2; break;\r
+ case 0x13e0: s->pm_pwstctrl_neon = 0x4 | (value & 3); break;\r
+ case 0x13e4: OMAP_RO_REG(addr); break;\r
+ case 0x13e8: s->pm_prepwstst_neon = value & 3; break;\r
+ /* USBHOST_PRM */\r
+ case 0x1458: s->rm_rstst_usbhost &= ~(value & 0xf); break;\r
+ case 0x14a0: s->pm_wken_usbhost = value & 1; break;\r
+ case 0x14a4: s->pm_mpugrpsel_usbhost = value & 1; break;\r
+ case 0x14a8: s->pm_iva2grpsel_usbhost = value & 1; break;\r
+ case 0x14b0: s->pm_wkst_usbhost &= ~(value & 1); break;\r
+ case 0x14c8: s->pm_wkdep_usbhost = value & 0x17; break;\r
+ case 0x14e0: s->pm_pwstctrl_usbhost = 0x030104 | (value & 0x13); break;\r
+ case 0x14e4: OMAP_RO_REG(addr); break;\r
+ case 0x14e8: s->pm_prepwstst_usbhost = value & 3; break;\r
+ default:\r
+ OMAP_BAD_REGV(addr, value);\r
+ break;\r
}\r
}\r
\r
\r
\r
\r
- s->l4 = omap_l4_init(OMAP3_L4_BASE, sizeof(omap3_l4_agent_info));\r
+ s->l4 = omap_l4_init(OMAP3_L4_BASE, sizeof(omap3_l4_agent_info) / sizeof(struct omap_l4_agent_info_s));\r
\r
cpu_irq = arm_pic_init_cpu(s->env);\r
- s->ih[0] = omap2_inth_init(s,\r
- 0x48200000, 0x1000, 3, &s->irq[0],\r
+ s->ih[0] = omap2_inth_init(s, 0x48200000, 0x1000, 3, &s->irq[0],\r
cpu_irq[ARM_PIC_CPU_IRQ],\r
- cpu_irq[ARM_PIC_CPU_FIQ], omap_findclk(s,\r
- "omap3_mpu_intc_fclk"),\r
+ cpu_irq[ARM_PIC_CPU_FIQ], \r
+ omap_findclk(s, "omap3_mpu_intc_fclk"),\r
omap_findclk(s, "omap3_mpu_intc_iclk"));\r
\r
for (i = 0; i < 4; i++)\r
omap_findclk(s, "omap3_wkup_l4_iclk"),\r
s);\r
\r
- s->omap3_scm = omap3_scm_init(omap3_l4ta_get(s->l4, 4), s);\r
+ s->omap3_scm = omap3_scm_init(omap3_l4ta_get(s->l4, 0), s);\r
\r
s->omap3_pm = omap3_pm_init(s);\r
s->omap3_sms = omap3_sms_init(s);\r
\r
- s->gptimer[0] = omap_gp_timer_init(omap3_l4ta_get(s->l4, 5),\r
+ s->gptimer[0] = omap_gp_timer_init(omap3_l4ta_get(s->l4, 4),\r
s->irq[0][OMAP_INT_35XX_GPTIMER1],\r
omap_findclk(s, "omap3_gp1_fclk"),\r
omap_findclk(s, "omap3_wkup_l4_iclk"));\r
- s->gptimer[1] = omap_gp_timer_init(omap3_l4ta_get(s->l4, 6),\r
+ s->gptimer[1] = omap_gp_timer_init(omap3_l4ta_get(s->l4, 5),\r
s->irq[0][OMAP_INT_35XX_GPTIMER2],\r
omap_findclk(s, "omap3_gp2_fclk"),\r
omap_findclk(s, "omap3_per_l4_iclk"));\r
- s->gptimer[2] = omap_gp_timer_init(omap3_l4ta_get(s->l4, 7),\r
+ s->gptimer[2] = omap_gp_timer_init(omap3_l4ta_get(s->l4, 6),\r
s->irq[0][OMAP_INT_35XX_GPTIMER3],\r
omap_findclk(s, "omap3_gp3_fclk"),\r
omap_findclk(s, "omap3_per_l4_iclk"));\r
- s->gptimer[3] = omap_gp_timer_init(omap3_l4ta_get(s->l4, 8),\r
+ s->gptimer[3] = omap_gp_timer_init(omap3_l4ta_get(s->l4, 7),\r
s->irq[0][OMAP_INT_35XX_GPTIMER4],\r
omap_findclk(s, "omap3_gp4_fclk"),\r
omap_findclk(s, "omap3_per_l4_iclk"));\r
- s->gptimer[4] = omap_gp_timer_init(omap3_l4ta_get(s->l4, 9),\r
+ s->gptimer[4] = omap_gp_timer_init(omap3_l4ta_get(s->l4, 8),\r
s->irq[0][OMAP_INT_35XX_GPTIMER5],\r
omap_findclk(s, "omap3_gp5_fclk"),\r
omap_findclk(s, "omap3_per_l4_iclk"));\r
- s->gptimer[5] = omap_gp_timer_init(omap3_l4ta_get(s->l4, 10),\r
+ s->gptimer[5] = omap_gp_timer_init(omap3_l4ta_get(s->l4, 9),\r
s->irq[0][OMAP_INT_35XX_GPTIMER6],\r
omap_findclk(s, "omap3_gp6_fclk"),\r
omap_findclk(s, "omap3_per_l4_iclk"));\r
- s->gptimer[6] = omap_gp_timer_init(omap3_l4ta_get(s->l4, 11),\r
+ s->gptimer[6] = omap_gp_timer_init(omap3_l4ta_get(s->l4, 10),\r
s->irq[0][OMAP_INT_35XX_GPTIMER7],\r
omap_findclk(s, "omap3_gp7_fclk"),\r
omap_findclk(s, "omap3_per_l4_iclk"));\r
- s->gptimer[7] = omap_gp_timer_init(omap3_l4ta_get(s->l4, 12),\r
+ s->gptimer[7] = omap_gp_timer_init(omap3_l4ta_get(s->l4, 11),\r
s->irq[0][OMAP_INT_35XX_GPTIMER8],\r
omap_findclk(s, "omap3_gp8_fclk"),\r
omap_findclk(s, "omap3_per_l4_iclk"));\r
- s->gptimer[8] = omap_gp_timer_init(omap3_l4ta_get(s->l4, 13),\r
+ s->gptimer[8] = omap_gp_timer_init(omap3_l4ta_get(s->l4, 12),\r
s->irq[0][OMAP_INT_35XX_GPTIMER9],\r
omap_findclk(s, "omap3_gp9_fclk"),\r
omap_findclk(s, "omap3_per_l4_iclk"));\r
- s->gptimer[9] = omap_gp_timer_init(omap3_l4ta_get(s->l4, 14),\r
+ s->gptimer[9] = omap_gp_timer_init(omap3_l4ta_get(s->l4, 13),\r
s->irq[0][OMAP_INT_35XX_GPTIMER10],\r
omap_findclk(s, "omap3_gp10_fclk"),\r
omap_findclk(s, "omap3_core_l4_iclk"));\r
- s->gptimer[10] = omap_gp_timer_init(omap3_l4ta_get(s->l4, 15),\r
+ s->gptimer[10] = omap_gp_timer_init(omap3_l4ta_get(s->l4, 14),\r
s->irq[0][OMAP_INT_35XX_GPTIMER11],\r
omap_findclk(s, "omap3_gp12_fclk"),\r
omap_findclk(s, "omap3_core_l4_iclk"));\r
- s->gptimer[11] = omap_gp_timer_init(omap3_l4ta_get(s->l4, 16),\r
- s->irq[0][OMAP_INT_35XX_GPTIMER12],\r
- omap_findclk(s, "omap3_gp12_fclk"),\r
- omap_findclk(s, "omap3_wkup_l4_iclk"));\r
-\r
+ s->gptimer[11] = omap_gp_timer_init(omap3_l4ta_get(s->l4, 15),\r
+ s->irq[0][OMAP_INT_35XX_GPTIMER12],\r
+ omap_findclk(s, "omap3_gp12_fclk"),\r
+ omap_findclk(s, "omap3_wkup_l4_iclk"));\r
\r
\r
- omap_synctimer_init(omap3_l4ta_get(s->l4, 17), s,\r
+ omap_synctimer_init(omap3_l4ta_get(s->l4, 16), s,\r
omap_findclk(s, "omap3_sys_32k"), NULL);\r
\r
s->sdrc = omap_sdrc_init(0x6d000000);\r
s->gpmc = omap_gpmc_init(s, 0x6e000000, s->irq[0][OMAP_INT_35XX_GPMC_IRQ]);\r
\r
\r
- s->uart[0] = omap2_uart_init(omap3_l4ta_get(s->l4, 18),\r
+ s->uart[0] = omap2_uart_init(omap3_l4ta_get(s->l4, 17),\r
s->irq[0][OMAP_INT_35XX_UART1_IRQ],\r
omap_findclk(s, "omap3_uart1_fclk"),\r
omap_findclk(s, "omap3_uart1_iclk"),\r
s->drq[OMAP35XX_DMA_UART1_TX],\r
s->drq[OMAP35XX_DMA_UART1_RX], serial_hds[0]);\r
- s->uart[1] = omap2_uart_init(omap3_l4ta_get(s->l4, 19),\r
+ s->uart[1] = omap2_uart_init(omap3_l4ta_get(s->l4, 18),\r
s->irq[0][OMAP_INT_35XX_UART2_IRQ],\r
omap_findclk(s, "omap3_uart2_fclk"),\r
omap_findclk(s, "omap3_uart2_iclk"),\r
s->drq[OMAP35XX_DMA_UART2_TX],\r
s->drq[OMAP35XX_DMA_UART2_RX],\r
serial_hds[0] ? serial_hds[1] : 0);\r
- s->uart[2] = omap2_uart_init(omap3_l4ta_get(s->l4, 20),\r
+ s->uart[2] = omap2_uart_init(omap3_l4ta_get(s->l4, 19),\r
s->irq[0][OMAP_INT_35XX_UART3_IRQ],\r
omap_findclk(s, "omap3_uart2_fclk"),\r
omap_findclk(s, "omap3_uart3_iclk"),\r
/*attach serial[0] to uart 2 for beagle board */\r
omap_uart_attach(s->uart[2], serial_hds[0]);\r
\r
- s->dss = omap_dss_init(omap3_l4ta_get(s->l4, 21), 0x68005400, ds,\r
+ s->dss = omap_dss_init(omap3_l4ta_get(s->l4, 20), 0x68005400, ds,\r
s->irq[0][OMAP_INT_35XX_DSS_IRQ], s->drq[OMAP24XX_DMA_DSS],\r
NULL,NULL,NULL,NULL,NULL);\r
\r
\r
s->gpif = omap3_gpif_init();\r
/*gpio 1*/\r
- omap3_gpio_init(s, s->gpif ,omap3_l4ta_get(s->l4, 22),\r
+ omap3_gpio_init(s, s->gpif ,omap3_l4ta_get(s->l4, 21),\r
&s->irq[0][OMAP_INT_35XX_GPIO_BANK1], \r
NULL,NULL,0);\r
/*gpio 2*/\r
- omap3_gpio_init(s, s->gpif ,omap3_l4ta_get(s->l4, 23),\r
+ omap3_gpio_init(s, s->gpif ,omap3_l4ta_get(s->l4, 22),\r
&s->irq[0][OMAP_INT_35XX_GPIO_BANK2], \r
NULL,NULL,1);\r
/*gpio 3*/\r
- omap3_gpio_init(s, s->gpif ,omap3_l4ta_get(s->l4, 24),\r
+ omap3_gpio_init(s, s->gpif ,omap3_l4ta_get(s->l4, 23),\r
&s->irq[0][OMAP_INT_35XX_GPIO_BANK3], \r
NULL,NULL,2);\r
/*gpio 4*/\r
- omap3_gpio_init(s, s->gpif ,omap3_l4ta_get(s->l4, 25),\r
+ omap3_gpio_init(s, s->gpif ,omap3_l4ta_get(s->l4, 24),\r
&s->irq[0][OMAP_INT_35XX_GPIO_BANK4], \r
NULL,NULL,3);\r
\r
/*gpio 5*/\r
- omap3_gpio_init(s, s->gpif ,omap3_l4ta_get(s->l4, 26),\r
+ omap3_gpio_init(s, s->gpif ,omap3_l4ta_get(s->l4, 25),\r
&s->irq[0][OMAP_INT_35XX_GPIO_BANK5], \r
NULL,NULL,4);\r
/*gpio 6*/\r
- omap3_gpio_init(s, s->gpif ,omap3_l4ta_get(s->l4, 27),\r
+ omap3_gpio_init(s, s->gpif ,omap3_l4ta_get(s->l4, 26),\r
&s->irq[0][OMAP_INT_35XX_GPIO_BANK6], \r
NULL,NULL,5);\r
\r
- omap_tap_init(omap3_l4ta_get(s->l4, 28), s);\r
+ omap_tap_init(omap3_l4ta_get(s->l4, 27), s);\r
\r
- s->omap3_mmc = omap3_mmc_init(omap3_l4ta_get(s->l4, 29), drives_table[sdindex].bdrv,\r
+ s->omap3_mmc = omap3_mmc_init(omap3_l4ta_get(s->l4, 28), drives_table[sdindex].bdrv,\r
s->irq[0][OMAP_INT_35XX_MMC1_IRQ],\r
&s->drq[OMAP35XX_DMA_MMC1_TX],\r
omap_findclk(s, "omap3_mmc1_fclk"), omap_findclk(s, "omap3_mmc1_iclk"));\r
\r
- s->i2c[0] = omap3_i2c_init(omap3_l4ta_get(s->l4, 32),\r
+ s->i2c[0] = omap3_i2c_init(omap3_l4ta_get(s->l4, 31),\r
s->irq[0][OMAP_INT_35XX_I2C1_IRQ],\r
&s->drq[OMAP35XX_DMA_I2C1_TX],\r
omap_findclk(s, "omap3_i2c1_fclk"),\r
omap_findclk(s, "omap3_i2c1_iclk"),\r
8);\r
- s->i2c[1] = omap3_i2c_init(omap3_l4ta_get(s->l4, 33),\r
+ s->i2c[1] = omap3_i2c_init(omap3_l4ta_get(s->l4, 32),\r
s->irq[0][OMAP_INT_35XX_I2C2_IRQ],\r
&s->drq[OMAP35XX_DMA_I2C2_TX],\r
omap_findclk(s, "omap3_i2c2_fclk"),\r
omap_findclk(s, "omap3_i2c2_iclk"),\r
8);\r
- s->i2c[2] = omap3_i2c_init(omap3_l4ta_get(s->l4, 34),\r
+ s->i2c[2] = omap3_i2c_init(omap3_l4ta_get(s->l4, 33),\r
s->irq[0][OMAP_INT_35XX_I2C3_IRQ],\r
&s->drq[OMAP35XX_DMA_I2C3_TX],\r
omap_findclk(s, "omap3_i2c3_fclk"),\r
projects / qemu / commitdiff