{
ESPState *s = opaque;
- esp_lower_irq(s);
-
memset(s->rregs, 0, ESP_REGS);
memset(s->wregs, 0, ESP_REGS);
s->rregs[ESP_TCHI] = TCHI_FAS100A; // Indicate fas100a
s->regs[IOMMU_AFSR] = IOMMU_AFSR_RESV;
s->regs[IOMMU_AER] = IOMMU_AER_EN_P0_ARB | IOMMU_AER_EN_P1_ARB;
s->regs[IOMMU_MASK_ID] = IOMMU_TS_MASK;
- qemu_irq_lower(s->irq);
}
void *iommu_init(target_phys_addr_t addr, uint32_t version, qemu_irq irq)
#define SBI_SIZE (SBI_NREGS * 4)
-static void sbi_check_interrupts(void *opaque)
-{
-}
-
static void sbi_set_irq(void *opaque, int irq, int level)
{
}
for (i = 0; i < MAX_CPUS; i++) {
qemu_get_be32s(f, &s->intreg_pending[i]);
}
- sbi_check_interrupts(s);
return 0;
}
for (i = 0; i < MAX_CPUS; i++) {
s->intreg_pending[i] = 0;
}
- sbi_check_interrupts(s);
}
void *sbi_init(target_phys_addr_t addr, qemu_irq **irq, qemu_irq **cpu_irq,
ptimer_run(s->timer, 0);
}
s->running = 1;
- qemu_irq_lower(s->irq);
}
static SLAVIO_TIMERState *slavio_timer_init(target_phys_addr_t addr,
qemu_get_8s(f, &s->reg);
qemu_get_8s(f, &s->pending);
- sun4c_check_interrupts(s);
return 0;
}
s->reg = 1;
s->pending = 0;
- sun4c_check_interrupts(s);
}
void *sun4c_intctl_init(target_phys_addr_t addr, qemu_irq **irq,