sparc merge (Blue Swirl)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1578 c046a42c-6fe2-441c-8c8c-71466251a162

diff --git a/hw/iommu.c b/hw/iommu.c
index d0b16ea..6defe61 100644 (file)
--- a/hw/iommu.c
+++ b/hw/iommu.c
@@ -33,9 +33,11 @@ do { printf("IOMMU: " fmt , ##args); } while (0)
 #define DPRINTF(fmt, args...)
 #endif
 
-#define IOMMU_NREGS (3*4096)
+#define IOMMU_NREGS (3*4096/4)
+#define IOMMU_CTRL          (0x0000 >> 2)
 #define IOMMU_CTRL_IMPL     0xf0000000 /* Implementation */
 #define IOMMU_CTRL_VERS     0x0f000000 /* Version */
+#define IOMMU_VERSION       0x04000000
 #define IOMMU_CTRL_RNGE     0x0000001c /* Mapping RANGE */
 #define IOMMU_RNGE_16MB     0x00000000 /* 0xff000000 -> 0xffffffff */
 #define IOMMU_RNGE_32MB     0x00000004 /* 0xfe000000 -> 0xffffffff */
@@ -46,6 +48,32 @@ do { printf("IOMMU: " fmt , ##args); } while (0)
 #define IOMMU_RNGE_1GB      0x00000018 /* 0xc0000000 -> 0xffffffff */
 #define IOMMU_RNGE_2GB      0x0000001c /* 0x80000000 -> 0xffffffff */
 #define IOMMU_CTRL_ENAB     0x00000001 /* IOMMU Enable */
+#define IOMMU_CTRL_MASK     0x0000001d
+
+#define IOMMU_BASE          (0x0004 >> 2)
+#define IOMMU_BASE_MASK     0x07fffc00
+
+#define IOMMU_TLBFLUSH      (0x0014 >> 2)
+#define IOMMU_TLBFLUSH_MASK 0xffffffff
+
+#define IOMMU_PGFLUSH       (0x0018 >> 2)
+#define IOMMU_PGFLUSH_MASK  0xffffffff
+
+#define IOMMU_SBCFG0        (0x1010 >> 2) /* SBUS configration per-slot */
+#define IOMMU_SBCFG1        (0x1014 >> 2) /* SBUS configration per-slot */
+#define IOMMU_SBCFG2        (0x1018 >> 2) /* SBUS configration per-slot */
+#define IOMMU_SBCFG3        (0x101c >> 2) /* SBUS configration per-slot */
+#define IOMMU_SBCFG_SAB30   0x00010000 /* Phys-address bit 30 when bypass enabled */
+#define IOMMU_SBCFG_BA16    0x00000004 /* Slave supports 16 byte bursts */
+#define IOMMU_SBCFG_BA8     0x00000002 /* Slave supports 8 byte bursts */
+#define IOMMU_SBCFG_BYPASS  0x00000001 /* Bypass IOMMU, treat all addresses
+                                                 produced by this device as pure
+                                          physical. */
+#define IOMMU_SBCFG_MASK    0x00010003
+
+#define IOMMU_ARBEN         (0x2000 >> 2) /* SBUS arbitration enable */
+#define IOMMU_ARBEN_MASK    0x001f0000
+#define IOMMU_MID           0x00000008
 
 /* The format of an iopte in the page tables */
 #define IOPTE_PAGE          0x07ffff00 /* Physical page number (PA[30:12]) */
@@ -87,7 +115,7 @@ static void iommu_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val
     saddr = (addr - s->addr) >> 2;
     DPRINTF("write reg[%d] = %x\n", saddr, val);
     switch (saddr) {
-    case 0:
+    case IOMMU_CTRL:
        switch (val & IOMMU_CTRL_RNGE) {
        case IOMMU_RNGE_16MB:
            s->iostart = 0xff000000;
@@ -116,7 +144,30 @@ static void iommu_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val
            break;
        }
        DPRINTF("iostart = %x\n", s->iostart);
-       /* Fall through */
+       s->regs[saddr] = ((val & IOMMU_CTRL_MASK) | IOMMU_VERSION);
+       break;
+    case IOMMU_BASE:
+       s->regs[saddr] = val & IOMMU_BASE_MASK;
+       break;
+    case IOMMU_TLBFLUSH:
+       DPRINTF("tlb flush %x\n", val);
+       s->regs[saddr] = val & IOMMU_TLBFLUSH_MASK;
+       break;
+    case IOMMU_PGFLUSH:
+       DPRINTF("page flush %x\n", val);
+       s->regs[saddr] = val & IOMMU_PGFLUSH_MASK;
+       break;
+    case IOMMU_SBCFG0:
+    case IOMMU_SBCFG1:
+    case IOMMU_SBCFG2:
+    case IOMMU_SBCFG3:
+       s->regs[saddr] = val & IOMMU_SBCFG_MASK;
+       break;
+    case IOMMU_ARBEN:
+        // XXX implement SBus probing: fault when reading unmapped
+        // addresses, fault cause and address stored to MMU/IOMMU
+       s->regs[saddr] = (val & IOMMU_ARBEN_MASK) | IOMMU_MID;
+       break;
     default:
        s->regs[saddr] = val;
        break;
@@ -184,6 +235,7 @@ static void iommu_reset(void *opaque)
 
     memset(s->regs, 0, IOMMU_NREGS * 4);
     s->iostart = 0;
+    s->regs[0] = IOMMU_VERSION;
 }
 
 void *iommu_init(uint32_t addr)

diff --git a/hw/slavio_misc.c b/hw/slavio_misc.c
index 597a0cb..1b681be 100644 (file)
--- a/hw/slavio_misc.c
+++ b/hw/slavio_misc.c
@@ -44,7 +44,7 @@ typedef struct MiscState {
     int irq;
     uint8_t config;
     uint8_t aux1, aux2;
-    uint8_t diag, mctrl;
+    uint8_t diag, mctrl, sysctrl;
 } MiscState;
 
 #define MISC_MAXADDR 1
@@ -64,7 +64,7 @@ static void slavio_misc_reset(void *opaque)
 {
     MiscState *s = opaque;
 
-    // Diagnostic register not cleared in reset
+    // Diagnostic and system control registers not cleared in reset
     s->config = s->aux1 = s->aux2 = s->mctrl = 0;
 }
 
@@ -116,8 +116,10 @@ static void slavio_misc_mem_writeb(void *opaque, target_phys_addr_t addr, uint32
        break;
     case 0x1f00000:
        MISC_DPRINTF("Write system control %2.2x\n", val & 0xff);
-       if (val & 1)
+       if (val & 1) {
+           s->sysctrl = 0x2;
            qemu_system_reset_request();
+       }
        break;
     case 0xa000000:
        MISC_DPRINTF("Write power management %2.2x\n", val & 0xff);
@@ -158,6 +160,7 @@ static uint32_t slavio_misc_mem_readb(void *opaque, target_phys_addr_t addr)
        break;
     case 0x1f00000:
        MISC_DPRINTF("Read system control %2.2x\n", ret);
+       ret = s->sysctrl;
        break;
     case 0xa000000:
        MISC_DPRINTF("Read power management %2.2x\n", ret);
@@ -188,6 +191,7 @@ static void slavio_misc_save(QEMUFile *f, void *opaque)
     qemu_put_8s(f, &s->aux2);
     qemu_put_8s(f, &s->diag);
     qemu_put_8s(f, &s->mctrl);
+    qemu_put_8s(f, &s->sysctrl);
 }
 
 static int slavio_misc_load(QEMUFile *f, void *opaque, int version_id)
@@ -203,6 +207,7 @@ static int slavio_misc_load(QEMUFile *f, void *opaque, int version_id)
     qemu_get_8s(f, &s->aux2);
     qemu_get_8s(f, &s->diag);
     qemu_get_8s(f, &s->mctrl);
+    qemu_get_8s(f, &s->sysctrl);
     return 0;
 }