#define BIOS_FILENAME "mipsel_bios.bin"
#endif
-#ifdef MIPS_HAS_MIPS64
+#ifdef TARGET_MIPS64
#define INITRD_LOAD_ADDR (int64_t)0x80800000
#else
#define INITRD_LOAD_ADDR (int32_t)0x80800000
/* init CPUs */
if (cpu_model == NULL) {
-#ifdef MIPS_HAS_MIPS64
+#ifdef TARGET_MIPS64
cpu_model = "R4000";
#else
cpu_model = "4KEc";
#define BIOS_FILENAME "mipsel_bios.bin"
#endif
-#ifdef MIPS_HAS_MIPS64
+#ifdef TARGET_MIPS64
#define INITRD_LOAD_ADDR (int64_t)(int32_t)0x80800000
#else
#define INITRD_LOAD_ADDR (int32_t)0x80800000
/* init CPUs */
if (cpu_model == NULL) {
-#ifdef MIPS_HAS_MIPS64
+#ifdef TARGET_MIPS64
cpu_model = "R4000";
#else
cpu_model = "4KEc";
{
}
-#ifdef MIPS_HAS_MIPS64
+#ifdef TARGET_MIPS64
#if TARGET_LONG_BITS > HOST_LONG_BITS
void do_dsll (void);
void do_dsll32 (void);
void do_ddiv (void);
void do_ddivu (void);
#endif
-#ifdef MIPS_HAS_MIPS64
+#ifdef TARGET_MIPS64
void do_dmult (void);
void do_dmultu (void);
#endif
void do_lwr_raw (uint32_t);
uint32_t do_swl_raw (uint32_t);
uint32_t do_swr_raw (uint32_t);
-#ifdef MIPS_HAS_MIPS64
+#ifdef TARGET_MIPS64
void do_ldl_raw (uint64_t);
void do_ldr_raw (uint64_t);
uint64_t do_sdl_raw (uint64_t);
uint32_t do_swl_kernel (uint32_t);
uint32_t do_swr_user (uint32_t);
uint32_t do_swr_kernel (uint32_t);
-#ifdef MIPS_HAS_MIPS64
+#ifdef TARGET_MIPS64
void do_ldl_user (uint64_t);
void do_ldl_kernel (uint64_t);
void do_ldr_user (uint64_t);
/* If we want to use host float regs... */
//#define USE_HOST_FLOAT_REGS
-/* 32 bits target */
-#undef MIPS_HAS_MIPS64
-//#define MIPS_HAS_MIPS64 1
/* real pages are variable size... */
#define TARGET_PAGE_BITS 12
/* Uses MIPS R4Kc TLB model */
#define MIPS_TLB_NB 16
#define MIPS_TLB_MAX 128
-#ifdef MIPS_HAS_MIPS64
+#ifdef TARGET_MIPS64
#define TARGET_LONG_BITS 64
#else
#define TARGET_LONG_BITS 32
RETURN();
}
-#ifdef MIPS_HAS_MIPS64
+#ifdef TARGET_MIPS64
/* Arithmetic */
void op_dadd (void)
{
RETURN();
}
#endif
-#endif /* MIPS_HAS_MIPS64 */
+#endif /* TARGET_MIPS64 */
/* Logical */
void op_and (void)
RETURN();
}
-#ifdef MIPS_HAS_MIPS64
+#ifdef TARGET_MIPS64
#if TARGET_LONG_BITS > HOST_LONG_BITS
/* Those might call libgcc functions. */
}
#endif /* TARGET_LONG_BITS > HOST_LONG_BITS */
-#ifdef MIPS_HAS_MIPS64
+#ifdef TARGET_MIPS64
void op_dmult (void)
{
CALL_FROM_TB0(do_dmult);
RETURN();
}
-#ifdef MIPS_HAS_MIPS64
+#ifdef TARGET_MIPS64
void op_dext(void)
{
unsigned int pos = PARAM1;
#undef MEMSUFFIX
#endif
-#ifdef MIPS_HAS_MIPS64
+#ifdef TARGET_MIPS64
#if TARGET_LONG_BITS > HOST_LONG_BITS
/* Those might call libgcc functions. */
void do_dsll (void)
T0 = T1;
}
#endif /* TARGET_LONG_BITS > HOST_LONG_BITS */
-#endif /* MIPS_HAS_MIPS64 */
+#endif /* TARGET_MIPS64 */
/* 64 bits arithmetic for 32 bits hosts */
#if TARGET_LONG_BITS > HOST_LONG_BITS
}
#endif
-#ifdef MIPS_HAS_MIPS64
+#ifdef TARGET_MIPS64
void do_dmult (void)
{
/* XXX */
return tmp;
}
-#ifdef MIPS_HAS_MIPS64
+#ifdef TARGET_MIPS64
# ifdef TARGET_WORDS_BIGENDIAN
#define GET_LMASK64(v) ((v) & 4)
return tmp;
}
-#endif /* MIPS_HAS_MIPS64 */
+#endif /* TARGET_MIPS64 */
RETURN();
}
-#ifdef MIPS_HAS_MIPS64
+#ifdef TARGET_MIPS64
void glue(op_ld, MEMSUFFIX) (void)
{
T0 = glue(ldq, MEMSUFFIX)(T0);
}
RETURN();
}
-#endif /* MIPS_HAS_MIPS64 */
+#endif /* TARGET_MIPS64 */
void glue(op_lwc1, MEMSUFFIX) (void)
{
}
#endif
-#ifdef MIPS_HAS_MIPS64
+#ifdef TARGET_MIPS64
OP_LD_TABLE(d);
OP_LD_TABLE(dl);
OP_LD_TABLE(dr);
* memory access
*/
switch (opc) {
-#ifdef MIPS_HAS_MIPS64
+#ifdef TARGET_MIPS64
case OPC_LD:
op_ldst(ld);
GEN_STORE_TN_REG(rt, T0);
gen_op_add();
opn = "addiu";
break;
-#ifdef MIPS_HAS_MIPS64
+#ifdef TARGET_MIPS64
case OPC_DADDI:
save_cpu_state(ctx, 1);
gen_op_daddo();
opn = "srl";
}
break;
-#ifdef MIPS_HAS_MIPS64
+#ifdef TARGET_MIPS64
case OPC_DSLL:
gen_op_dsll();
opn = "dsll";
gen_op_sub();
opn = "subu";
break;
-#ifdef MIPS_HAS_MIPS64
+#ifdef TARGET_MIPS64
case OPC_DADD:
save_cpu_state(ctx, 1);
gen_op_daddo();
opn = "srlv";
}
break;
-#ifdef MIPS_HAS_MIPS64
+#ifdef TARGET_MIPS64
case OPC_DSLLV:
gen_op_dsllv();
opn = "dsllv";
gen_op_multu();
opn = "multu";
break;
-#ifdef MIPS_HAS_MIPS64
+#ifdef TARGET_MIPS64
case OPC_DDIV:
gen_op_ddiv();
opn = "ddiv";
gen_op_clz();
opn = "clz";
break;
-#ifdef MIPS_HAS_MIPS64
+#ifdef TARGET_MIPS64
case OPC_DCLO:
gen_op_dclo();
opn = "dclo";
/* MIPS16 extension to MIPS32 */
/* SmartMIPS extension to MIPS32 */
-#ifdef MIPS_HAS_MIPS64
+#ifdef TARGET_MIPS64
/* Coprocessor 3 (FPU) */
/* MDMX extension to MIPS64 */
}
break;
-#ifdef MIPS_HAS_MIPS64
+#ifdef TARGET_MIPS64
/* MIPS64 specific opcodes */
case OPC_DSLL:
case OPC_DSRL ... OPC_DSRA:
}
/* Treat as a noop */
break;
-#ifdef MIPS_HAS_MIPS64
+#ifdef TARGET_MIPS64
case OPC_DCLZ ... OPC_DCLO:
gen_cl(ctx, op1, rd, rs);
break;
}
GEN_STORE_TN_REG(rt, T0);
break;
-#ifdef MIPS_HAS_MIPS64
+#ifdef TARGET_MIPS64
case OPC_DEXTM ... OPC_DEXT:
case OPC_DINSM ... OPC_DINS:
gen_bitops(ctx, op1, rt, rs, sa, rd);
switch (op1) {
case OPC_MFC0:
case OPC_MTC0:
-#ifdef MIPS_HAS_MIPS64
+#ifdef TARGET_MIPS64
case OPC_DMFC0:
case OPC_DMTC0:
#endif
case OPC_CFC1:
case OPC_MTC1:
case OPC_CTC1:
-#ifdef MIPS_HAS_MIPS64
+#ifdef TARGET_MIPS64
case OPC_DMFC1:
case OPC_DMTC1:
#endif
}
break;
-#ifdef MIPS_HAS_MIPS64
+#ifdef TARGET_MIPS64
/* MIPS64 opcodes */
case OPC_LWU:
case OPC_LDL ... OPC_LDR:
}
}
-#if defined(MIPS_HAS_MIPS64) && defined(MIPS_DEBUG_SIGN_EXTENSIONS)
+#if defined(TARGET_MIPS64) && defined(MIPS_DEBUG_SIGN_EXTENSIONS)
/* Debug help: The architecture requires 32bit code to maintain proper
sign-extened values on 64bit machines. */
env->CP0_Config0, env->CP0_Config1, env->CP0_LLAddr);
if (c0_status & (1 << CP0St_CU1))
fpu_dump_state(env, f, cpu_fprintf, flags);
-#if defined(MIPS_HAS_MIPS64) && defined(MIPS_DEBUG_SIGN_EXTENSIONS)
+#if defined(TARGET_MIPS64) && defined(MIPS_DEBUG_SIGN_EXTENSIONS)
cpu_mips_check_sign_extensions(env, f, cpu_fprintf, flags);
#endif
}
/* MIPS CPU definitions */
static mips_def_t mips_defs[] =
{
-#ifndef MIPS_HAS_MIPS64
+#ifndef TARGET_MIPS64
{
.name = "4Kc",
.CP0_PRid = 0x00018000,