#define INTCTLM_MASK 0x1f
#define MASTER_IRQ_MASK ~0x0fa2007f
#define MASTER_DISABLE 0x80000000
-#define CPU_IRQ_MASK 0xfffe0000
+#define CPU_SOFTIRQ_MASK 0xfffe0000
+#define CPU_HARDIRQ_MASK 0x0000fffe
#define CPU_IRQ_INT15_IN 0x0004000
#define CPU_IRQ_INT15_MASK 0x80000000
case 1: // clear pending softints
if (val & CPU_IRQ_INT15_IN)
val |= CPU_IRQ_INT15_MASK;
- val &= CPU_IRQ_MASK;
+ val &= CPU_SOFTIRQ_MASK;
s->intreg_pending[cpu] &= ~val;
slavio_check_interrupts(s);
DPRINTF("Cleared cpu %d irq mask %x, curmask %x\n", cpu, val, s->intreg_pending[cpu]);
break;
case 2: // set softint
- val &= CPU_IRQ_MASK;
+ val &= CPU_SOFTIRQ_MASK;
s->intreg_pending[cpu] |= val;
slavio_check_interrupts(s);
DPRINTF("Set cpu %d irq mask %x, curmask %x\n", cpu, val, s->intreg_pending[cpu]);
if (pending & (1 << j))
pil_pending |= 1 << s->intbit_to_level[j];
}
+ pil_pending |= s->intreg_pending[i] & CPU_HARDIRQ_MASK;
}
- pil_pending |= (s->intreg_pending[i] & CPU_IRQ_MASK) >> 16;
+ pil_pending |= (s->intreg_pending[i] & CPU_SOFTIRQ_MASK) >> 16;
for (j = 0; j < MAX_PILS; j++) {
if (pil_pending & (1 << j)) {
*irq = qemu_allocate_irqs(slavio_set_irq, s, 32);
*cpu_irq = qemu_allocate_irqs(slavio_set_timer_irq_cpu, s, MAX_CPUS);
- s->cputimer_bit = 1 << s->intbit_to_level[cputimer];
+ s->cputimer_bit = 1 << cputimer;
slavio_intctl_reset(s);
return s;
}
uint32_t ecc_version;
target_phys_addr_t sun4c_intctl_base, sun4c_counter_base;
long vram_size, nvram_size;
- // IRQ numbers are not PIL ones, but master interrupt controller register
- // bit numbers
+ // IRQ numbers are not PIL ones, but master interrupt controller
+ // register bit numbers except for clock_irq, which indexes cpu
+ // interrupt controller register
int intctl_g_intr, esp_irq, le_irq, clock_irq, clock1_irq;
int ser_irq, ms_kb_irq, fd_irq, me_irq, cs_irq;
int machine_id; // For NVRAM
.nvram_size = 0x2000,
.esp_irq = 18,
.le_irq = 16,
- .clock_irq = 7,
+ .clock_irq = 14,
.clock1_irq = 19,
.ms_kb_irq = 14,
.ser_irq = 15,
.nvram_size = 0x2000,
.esp_irq = 18,
.le_irq = 16,
- .clock_irq = 7,
+ .clock_irq = 14,
.clock1_irq = 19,
.ms_kb_irq = 14,
.ser_irq = 15,
.nvram_size = 0x2000,
.esp_irq = 18,
.le_irq = 16,
- .clock_irq = 7,
+ .clock_irq = 14,
.clock1_irq = 19,
.ms_kb_irq = 14,
.ser_irq = 15,
.nvram_size = 0x2000,
.esp_irq = 18,
.le_irq = 16,
- .clock_irq = 7,
+ .clock_irq = 14,
.clock1_irq = 19,
.ms_kb_irq = 14,
.ser_irq = 15,