/* general purpose registers */
ppc_gpr_t gpr[32];
-#if TARGET_GPR_BITS < 64
+#if !defined(TARGET_PPC64)
/* Storage for GPR MSB, used by the SPE extension */
ppc_gpr_t gprh[32];
#endif
#endif
/* General purpose registers containing vector operands moves */
-#if TARGET_GPR_BITS < 64
+#if !defined(TARGET_PPC64)
void OPPROTO glue(op_load_gpr64_T0_gpr, REG) (void)
{
T0_64 = (uint64_t)env->gpr[REG] | ((uint64_t)env->gprh[REG] << 32);
RETURN();
}
#endif
-#endif /* TARGET_GPR_BITS < 64 */
+#endif /* !defined(TARGET_PPC64) */
/* Altivec registers moves */
void OPPROTO glue(op_load_avr_A0_avr, REG) (void)
/*** SPE extension ***/
/* Register moves */
-#if TARGET_GPR_BITS < 64
+#if !defined(TARGET_PPC64)
GEN32(gen_op_load_gpr64_T0, gen_op_load_gpr64_T0_gpr);
GEN32(gen_op_load_gpr64_T1, gen_op_load_gpr64_T1_gpr);
GEN32(gen_op_store_T2_gpr64, gen_op_store_T2_gpr64_gpr);
#endif
-#else /* TARGET_GPR_BITS < 64 */
+#else /* !defined(TARGET_PPC64) */
/* No specific load/store functions: GPRs are already 64 bits */
#define gen_op_load_gpr64_T0 gen_op_load_gpr_T0
#define gen_op_store_T2_gpr64 gen_op_store_T2_gpr
#endif
-#endif /* TARGET_GPR_BITS < 64 */
+#endif /* !defined(TARGET_PPC64) */
#define GEN_SPE(name0, name1, opc2, opc3, inval, type) \
GEN_HANDLER(name0##_##name1, 0x04, opc2, opc3, inval, type) \