Add support for OMAP3 SYS_CLK input selection reconfiguration support. In real life we would also need to support sys_boot pin 6 to choose between oscillator bypass mode (xtalin is square wave) or PRCM internal oscillator (xtalin). Current code is fixed to use the bypass mode with a default setting of 26MHz input. Also, added SYS_CLKOUT1 clock which was missing.
/*
* Beagle board emulation. http://beagleboard.org/
*
- * Copyright (C) 2008 yajin(yajin@vm-kernel.org)
+ * Original code Copyright (C) 2008 yajin(yajin@vm-kernel.org)
+ * Rewrite Copyright (C) 2009 Nokia Corporation
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
#include "sysemu.h"
#include "omap.h"
#include "arm-misc.h"
-#include "irq.h"
-#include "console.h"
#include "boards.h"
#include "i2c.h"
#include "devices.h"
#include "flash.h"
-#include "hw.h"
-#include "block.h"
#define BEAGLE_NAND_CS 0
#define BEAGLE_NAND_PAGESIZE 0x800
+#define BEAGLE_SDRAM_SIZE (128 * 1024 * 1024) /* 128MB */
/* Beagle board support */
struct beagle_s {
struct twl4030_s *twl4030;
};
-static struct arm_boot_info beagle_binfo = {
- .ram_size = 0x08000000,
-};
-
static void beagle_nand_pread(struct nand_flash_s *nand,
uint64_t addr,
uint8_t *data,
const char *initrd_filename, const char *cpu_model)
{
struct beagle_s *s = (struct beagle_s *) qemu_mallocz(sizeof(*s));
- int sdram_size = beagle_binfo.ram_size;
int sdindex = drive_get_index(IF_SD, 0, 0);
if (sdindex == -1) {
- fprintf(stderr, "qemu: missing SecureDigital device\n");
+ fprintf(stderr, "%s: missing SecureDigital device\n", __FUNCTION__);
exit(1);
}
-
- if (ram_size < sdram_size + OMAP3530_SRAM_SIZE) {
- fprintf(stderr, "This architecture uses %i bytes of memory\n",
- sdram_size + OMAP3530_SRAM_SIZE);
+ if (ram_size < (beagle_machine.ram_require & ~RAMSIZE_FIXED)) {
+ fprintf(stderr, "%s: This architecture uses %lu bytes of memory\n",
+ __FUNCTION__, (beagle_machine.ram_require & ~RAMSIZE_FIXED));
exit(1);
}
- s->cpu = omap3530_mpu_init(sdram_size, NULL);
+ s->cpu = omap3530_mpu_init(BEAGLE_SDRAM_SIZE, NULL);
if (serial_hds[0])
omap_uart_attach(s->cpu->uart[2], serial_hds[0]);
omap3_mmc_attach(s->cpu->omap3_mmc[0], drives_table[sdindex].bdrv);
s->i2c = omap_i2c_bus(s->cpu->i2c[0]);
- s->twl4030 = twl4030_init(s->i2c, s->cpu->irq[0][OMAP_INT_35XX_SYS_NIRQ]);
+ s->twl4030 = twl4030_init(s->i2c, s->cpu->irq[0][OMAP_INT_3XXX_SYS_NIRQ]);
s->lcd_panel = omap3_lcd_panel_init();
omap3_lcd_panel_attach(s->cpu->dss, 0, s->lcd_panel);
-
+
if (!omap3_mmc_boot(s->cpu)
&& !omap3_nand_boot(s->cpu, s->nand, beagle_nand_pread)) {
fprintf(stderr, "%s: boot from MMC and NAND failed\n",
}
QEMUMachine beagle_machine = {
- .name = "beagle",
- .desc = "Beagle board (OMAP3530)",
- .init = beagle_init,
- .ram_require = (0x08000000 + OMAP3530_SRAM_SIZE) | RAMSIZE_FIXED,
+ .name = "beagle",
+ .desc = "Beagle board (OMAP3530)",
+ .init = beagle_init,
+ .ram_require = (BEAGLE_SDRAM_SIZE
+ + OMAP3XXX_SRAM_SIZE
+ + OMAP3XXX_BOOTROM_SIZE) | RAMSIZE_FIXED,
};
# define OMAP3_Q3_BASE 0xc0000000
# define OMAP_MPUI_BASE 0xe1000000
-# define OMAP730_SRAM_SIZE 0x00032000
-# define OMAP15XX_SRAM_SIZE 0x00030000
-# define OMAP16XX_SRAM_SIZE 0x00004000
-# define OMAP1611_SRAM_SIZE 0x0003e800
-# define OMAP242X_SRAM_SIZE 0x000a0000
-# define OMAP243X_SRAM_SIZE 0x00010000
-# define OMAP3530_SRAM_SIZE 0x00010000
-# define OMAP_CS0_SIZE 0x04000000
-# define OMAP_CS1_SIZE 0x04000000
-# define OMAP_CS2_SIZE 0x04000000
-# define OMAP_CS3_SIZE 0x04000000
+# define OMAP730_SRAM_SIZE 0x00032000
+# define OMAP15XX_SRAM_SIZE 0x00030000
+# define OMAP16XX_SRAM_SIZE 0x00004000
+# define OMAP1611_SRAM_SIZE 0x0003e800
+# define OMAP242X_SRAM_SIZE 0x000a0000
+# define OMAP243X_SRAM_SIZE 0x00010000
+# define OMAP3XXX_SRAM_SIZE 0x00010000
+# define OMAP3XXX_BOOTROM_SIZE 0x0001C000
+# define OMAP_CS0_SIZE 0x04000000
+# define OMAP_CS1_SIZE 0x04000000
+# define OMAP_CS2_SIZE 0x04000000
+# define OMAP_CS3_SIZE 0x04000000
/* omap_clk.c */
struct omap_mpu_state_s;
# define OMAP_INT_34XX_GPTIMER12 95
/*
- * OMAP-35XX common IRQ numbers
+ * OMAP-3XXX common IRQ numbers
*/
-#define OMAP_INT_35XX_EMUINT 0 /* MPU emulation */
-#define OMAP_INT_35XX_COMMTX 1 /* MPU emulation */
-#define OMAP_INT_35XX_COMMRX 2 /* MPU emulation */
-#define OMAP_INT_35XX_BENCH 3 /* MPU emulation */
-#define OMAP_INT_35XX_MCBSP2_ST_IRQ 4 /* Sidetone MCBSP2 overflow */
-#define OMAP_INT_35XX_MCBSP3_ST_IRQ 5 /* Sidetone MCBSP3 overflow */
+#define OMAP_INT_3XXX_EMUINT 0 /* MPU emulation */
+#define OMAP_INT_3XXX_COMMTX 1 /* MPU emulation */
+#define OMAP_INT_3XXX_COMMRX 2 /* MPU emulation */
+#define OMAP_INT_3XXX_BENCH 3 /* MPU emulation */
+#define OMAP_INT_3XXX_MCBSP2_ST_IRQ 4 /* Sidetone MCBSP2 overflow */
+#define OMAP_INT_3XXX_MCBSP3_ST_IRQ 5 /* Sidetone MCBSP3 overflow */
/* IRQ6 is reserved */
-#define OMAP_INT_35XX_SYS_NIRQ 7 /* External source (active low) */
+#define OMAP_INT_3XXX_SYS_NIRQ 7 /* External source (active low) */
/* IRQ8 is reserved */
-#define OMAP_INT_35XX_SMX_DBG_IRQ 9 /* L3 interconnect error for debug */
-#define OMAP_INT_35XX_SMX_APP_IRQ 10 /* L3 interconnect error for application */
-#define OMAP_INT_35XX_PRCM_MPU_IRQ 11 /* PRCM module IRQ */
-#define OMAP_INT_35XX_SDMA_IRQ0 12 /* System DMA request 0 */
-#define OMAP_INT_35XX_SDMA_IRQ1 13 /* System DMA request 1 */
-#define OMAP_INT_35XX_SDMA_IRQ2 14 /* System DMA request 2 */
-#define OMAP_INT_35XX_SDMA_IRQ3 15 /* System DMA request 3 */
-#define OMAP_INT_35XX_MCBSP1_IRQ 16 /* MCBSP module 1 IRQ */
-#define OMAP_INT_35XX_MCBSP2_IRQ 17 /* MCBSP module 2 IRQ */
+#define OMAP_INT_3XXX_SMX_DBG_IRQ 9 /* L3 interconnect error for debug */
+#define OMAP_INT_3XXX_SMX_APP_IRQ 10 /* L3 interconnect error for application */
+#define OMAP_INT_3XXX_PRCM_MPU_IRQ 11 /* PRCM module IRQ */
+#define OMAP_INT_3XXX_SDMA_IRQ0 12 /* System DMA request 0 */
+#define OMAP_INT_3XXX_SDMA_IRQ1 13 /* System DMA request 1 */
+#define OMAP_INT_3XXX_SDMA_IRQ2 14 /* System DMA request 2 */
+#define OMAP_INT_3XXX_SDMA_IRQ3 15 /* System DMA request 3 */
+#define OMAP_INT_3XXX_MCBSP1_IRQ 16 /* MCBSP module 1 IRQ */
+#define OMAP_INT_3XXX_MCBSP2_IRQ 17 /* MCBSP module 2 IRQ */
/* IRQ18 is reserved */
/* IRQ19 is reserved */
-#define OMAP_INT_35XX_GPMC_IRQ 20 /* General-purpose memory controller module */
-#define OMAP_INT_35XX_SGX_IRQ 21 /* 2D/3D graphics module */
-#define OMAP_INT_35XX_MCBSP3_IRQ 22 /* MCBSP module 3 */
-#define OMAP_INT_35XX_MCBSP4_IRQ 23 /* MCBSP module 4 */
-#define OMAP_INT_35XX_CAM_IRQ0 24 /* Camera interface request 0 */
-#define OMAP_INT_35XX_DSS_IRQ 25 /* Display subsystem module */
-#define OMAP_INT_35XX_MAIL_U0_MPU 26 /* Mailbox user 0 request */
-#define OMAP_INT_35XX_MCBSP5_IRQ 27 /* MCBSP module 5 */
-#define OMAP_INT_35XX_IVA2_MMU_IRQ 28 /* IVA2 MMU */
-#define OMAP_INT_35XX_GPIO1_MPU_IRQ 29 /* GPIO module 1 */
-#define OMAP_INT_35XX_GPIO2_MPU_IRQ 30 /* GPIO module 2 */
-#define OMAP_INT_35XX_GPIO3_MPU_IRQ 31 /* GPIO module 3 */
-#define OMAP_INT_35XX_GPIO4_MPU_IRQ 32 /* GPIO module 4 */
-#define OMAP_INT_35XX_GPIO5_MPU_IRQ 33 /* GPIO module 5 */
-#define OMAP_INT_35XX_GPIO6_MPU_IRQ 34 /* GPIO module 6 */
+#define OMAP_INT_3XXX_GPMC_IRQ 20 /* General-purpose memory controller module */
+#define OMAP_INT_3XXX_SGX_IRQ 21 /* 2D/3D graphics module */
+#define OMAP_INT_3XXX_MCBSP3_IRQ 22 /* MCBSP module 3 */
+#define OMAP_INT_3XXX_MCBSP4_IRQ 23 /* MCBSP module 4 */
+#define OMAP_INT_3XXX_CAM_IRQ0 24 /* Camera interface request 0 */
+#define OMAP_INT_3XXX_DSS_IRQ 25 /* Display subsystem module */
+#define OMAP_INT_3XXX_MAIL_U0_MPU 26 /* Mailbox user 0 request */
+#define OMAP_INT_3XXX_MCBSP5_IRQ 27 /* MCBSP module 5 */
+#define OMAP_INT_3XXX_IVA2_MMU_IRQ 28 /* IVA2 MMU */
+#define OMAP_INT_3XXX_GPIO1_MPU_IRQ 29 /* GPIO module 1 */
+#define OMAP_INT_3XXX_GPIO2_MPU_IRQ 30 /* GPIO module 2 */
+#define OMAP_INT_3XXX_GPIO3_MPU_IRQ 31 /* GPIO module 3 */
+#define OMAP_INT_3XXX_GPIO4_MPU_IRQ 32 /* GPIO module 4 */
+#define OMAP_INT_3XXX_GPIO5_MPU_IRQ 33 /* GPIO module 5 */
+#define OMAP_INT_3XXX_GPIO6_MPU_IRQ 34 /* GPIO module 6 */
/* IRQ35 is reserved */
-#define OMAP_INT_35XX_WDT3_IRQ 36 /* Watchdog timer module 3 overflow */
-#define OMAP_INT_35XX_GPT1_IRQ 37 /* General-purpose timer module 1 */
-#define OMAP_INT_35XX_GPT2_IRQ 38 /* General-purpose timer module 2 */
-#define OMAP_INT_35XX_GPT3_IRQ 39 /* General-purpose timer module 3 */
-#define OMAP_INT_35XX_GPT4_IRQ 40 /* General-purpose timer module 4 */
-#define OMAP_INT_35XX_GPT5_IRQ 41 /* General-purpose timer module 5 */
-#define OMAP_INT_35XX_GPT6_IRQ 42 /* General-purpose timer module 6 */
-#define OMAP_INT_35XX_GPT7_IRQ 43 /* General-purpose timer module 7 */
-#define OMAP_INT_35XX_GPT8_IRQ 44 /* General-purpose timer module 8 */
-#define OMAP_INT_35XX_GPT9_IRQ 45 /* General-purpose timer module 9 */
-#define OMAP_INT_35XX_GPT10_IRQ 46 /* General-purpose timer module 10 */
-#define OMAP_INT_35XX_GPT11_IRQ 47 /* General-purpose timer module 11 */
-#define OMAP_INT_35XX_SPI4_IRQ 48 /* MCSPI module 4 */
+#define OMAP_INT_3XXX_WDT3_IRQ 36 /* Watchdog timer module 3 overflow */
+#define OMAP_INT_3XXX_GPT1_IRQ 37 /* General-purpose timer module 1 */
+#define OMAP_INT_3XXX_GPT2_IRQ 38 /* General-purpose timer module 2 */
+#define OMAP_INT_3XXX_GPT3_IRQ 39 /* General-purpose timer module 3 */
+#define OMAP_INT_3XXX_GPT4_IRQ 40 /* General-purpose timer module 4 */
+#define OMAP_INT_3XXX_GPT5_IRQ 41 /* General-purpose timer module 5 */
+#define OMAP_INT_3XXX_GPT6_IRQ 42 /* General-purpose timer module 6 */
+#define OMAP_INT_3XXX_GPT7_IRQ 43 /* General-purpose timer module 7 */
+#define OMAP_INT_3XXX_GPT8_IRQ 44 /* General-purpose timer module 8 */
+#define OMAP_INT_3XXX_GPT9_IRQ 45 /* General-purpose timer module 9 */
+#define OMAP_INT_3XXX_GPT10_IRQ 46 /* General-purpose timer module 10 */
+#define OMAP_INT_3XXX_GPT11_IRQ 47 /* General-purpose timer module 11 */
+#define OMAP_INT_3XXX_SPI4_IRQ 48 /* MCSPI module 4 */
/* IRQ49 is reserved */
/* IRQ50 is reserved */
/* IRQ51 is reserved */
/* IRQ52 is reserved */
-#define OMAP_INT_35XX_MG_IRQ 53
-#define OMAP_INT_35XX_MCBSP4_IRQ_TX 54 /* MCBSP module 4 transmit */
-#define OMAP_INT_35XX_MCBSP4_IRQ_RX 55 /* MCBSP module 4 receive */
-#define OMAP_INT_35XX_I2C1_IRQ 56 /* I2C module 1 */
-#define OMAP_INT_35XX_I2C2_IRQ 57 /* I2C module 2 */
-#define OMAP_INT_35XX_HDQ_IRQ 58 /* HDQ/1-Wire */
-#define OMAP_INT_35XX_MCBSP1_IRQ_TX 59 /* MCBSP module 1 transmit */
-#define OMAP_INT_35XX_MCBSP1_IRQ_RX 60 /* MCBSP module 1 receive */
-#define OMAP_INT_35XX_I2C3_IRQ 61 /* I2C module 3 */
-#define OMAP_INT_35XX_MCBSP2_IRQ_TX 62 /* MCBSP module 2 transmit */
-#define OMAP_INT_35XX_MCBSP2_IRQ_RX 63 /* MCBSP module 2 receive */
+#define OMAP_INT_3XXX_MG_IRQ 53
+#define OMAP_INT_3XXX_MCBSP4_IRQ_TX 54 /* MCBSP module 4 transmit */
+#define OMAP_INT_3XXX_MCBSP4_IRQ_RX 55 /* MCBSP module 4 receive */
+#define OMAP_INT_3XXX_I2C1_IRQ 56 /* I2C module 1 */
+#define OMAP_INT_3XXX_I2C2_IRQ 57 /* I2C module 2 */
+#define OMAP_INT_3XXX_HDQ_IRQ 58 /* HDQ/1-Wire */
+#define OMAP_INT_3XXX_MCBSP1_IRQ_TX 59 /* MCBSP module 1 transmit */
+#define OMAP_INT_3XXX_MCBSP1_IRQ_RX 60 /* MCBSP module 1 receive */
+#define OMAP_INT_3XXX_I2C3_IRQ 61 /* I2C module 3 */
+#define OMAP_INT_3XXX_MCBSP2_IRQ_TX 62 /* MCBSP module 2 transmit */
+#define OMAP_INT_3XXX_MCBSP2_IRQ_RX 63 /* MCBSP module 2 receive */
/* IRQ64 is reserved */
-#define OMAP_INT_35XX_MCSPI1_IRQ 65 /* MCSPI module 1 */
-#define OMAP_INT_35XX_MCSPI2_IRQ 66 /* MCSPI module 2 */
+#define OMAP_INT_3XXX_MCSPI1_IRQ 65 /* MCSPI module 1 */
+#define OMAP_INT_3XXX_MCSPI2_IRQ 66 /* MCSPI module 2 */
/* IRQ67 is reserved */
/* IRQ68 is reserved */
/* IRQ69 is reserved */
/* IRQ70 is reserved */
/* IRQ71 is reserved */
-#define OMAP_INT_35XX_UART1_IRQ 72 /* UART module 1 */
-#define OMAP_INT_35XX_UART2_IRQ 73 /* UART module 2 */
-#define OMAP_INT_35XX_UART3_IRQ 74 /* UART module 3 (also infrared)*/
-#define OMAP_INT_35XX_PBIAS_IRQ 75 /* Merged interrupt for PBIASlite1 and 2 */
-#define OMAP_INT_35XX_OHCI_IRQ 76 /* OHCI controller HSUSB MP Host interrupt */
-#define OMAP_INT_35XX_EHCI_IRQ 77 /* EHCI controller HSUSB MP Host interrupt */
-#define OMAP_INT_35XX_TLL_IRQ 78 /* HSUSB MP TLL interrupt */
+#define OMAP_INT_3XXX_UART1_IRQ 72 /* UART module 1 */
+#define OMAP_INT_3XXX_UART2_IRQ 73 /* UART module 2 */
+#define OMAP_INT_3XXX_UART3_IRQ 74 /* UART module 3 (also infrared)*/
+#define OMAP_INT_3XXX_PBIAS_IRQ 75 /* Merged interrupt for PBIASlite1 and 2 */
+#define OMAP_INT_3XXX_OHCI_IRQ 76 /* OHCI controller HSUSB MP Host interrupt */
+#define OMAP_INT_3XXX_EHCI_IRQ 77 /* EHCI controller HSUSB MP Host interrupt */
+#define OMAP_INT_3XXX_TLL_IRQ 78 /* HSUSB MP TLL interrupt */
/* IRQ79 is reserved */
/* IRQ80 is reserved */
-#define OMAP_INT_35XX_MCBSP5_IRQ_TX 81 /* MCBSP module 5 transmit */
-#define OMAP_INT_35XX_MCBSP5_IRQ_RX 82 /* MCBSP module 5 receive */
-#define OMAP_INT_35XX_MMC1_IRQ 83 /* MMC/SD module 1 */
-#define OMAP_INT_35XX_MS_IRQ 84
+#define OMAP_INT_3XXX_MCBSP5_IRQ_TX 81 /* MCBSP module 5 transmit */
+#define OMAP_INT_3XXX_MCBSP5_IRQ_RX 82 /* MCBSP module 5 receive */
+#define OMAP_INT_3XXX_MMC1_IRQ 83 /* MMC/SD module 1 */
+#define OMAP_INT_3XXX_MS_IRQ 84
/* IRQ85 is reserved */
-#define OMAP_INT_35XX_MMC2_IRQ 86 /* MMC/SD module 2 */
-#define OMAP_INT_35XX_MPU_ICR_IRQ 87 /* MPU ICR */
-#define OMAP_INT_35XX_D2DFRINT 88 /* 3G coprocessor */
-#define OMAP_INT_35XX_MCBSP3_IRQ_TX 89 /* MCBSP module 3 transmit */
-#define OMAP_INT_35XX_MCBSP3_IRQ_RX 90 /* MCBSP module 3 receive */
-#define OMAP_INT_35XX_MCSPI3_IRQ 91 /* MCSPI module 3 */
-#define OMAP_INT_35XX_HSUSB_MC 92 /* High-Speed USB OTG controller */
-#define OMAP_INT_35XX_HSUSB_DMA 93 /* High-Speed USB OTG DMA controller */
-#define OMAP_INT_35XX_MMC3_IRQ 94 /* MMC/SD module 3 */
-#define OMAP_INT_35XX_GPT12_IRQ 95 /* General-purpose timer module 12 */
+#define OMAP_INT_3XXX_MMC2_IRQ 86 /* MMC/SD module 2 */
+#define OMAP_INT_3XXX_MPU_ICR_IRQ 87 /* MPU ICR */
+#define OMAP_INT_3XXX_D2DFRINT 88 /* 3G coprocessor */
+#define OMAP_INT_3XXX_MCBSP3_IRQ_TX 89 /* MCBSP module 3 transmit */
+#define OMAP_INT_3XXX_MCBSP3_IRQ_RX 90 /* MCBSP module 3 receive */
+#define OMAP_INT_3XXX_MCSPI3_IRQ 91 /* MCSPI module 3 */
+#define OMAP_INT_3XXX_HSUSB_MC 92 /* High-Speed USB OTG controller */
+#define OMAP_INT_3XXX_HSUSB_DMA 93 /* High-Speed USB OTG DMA controller */
+#define OMAP_INT_3XXX_MMC3_IRQ 94 /* MMC/SD module 3 */
+#define OMAP_INT_3XXX_GPT12_IRQ 95 /* General-purpose timer module 12 */
/* omap_dma.c */
enum omap_dma_model {
* number plus one! Zero is a reserved value (defined as
* NO_DEVICE here). Other missing values are reserved.
*/
-#define OMAP35XX_DMA_NO_DEVICE 0
-
-#define OMAP35XX_DMA_EXT_DMAREQ0 2
-#define OMAP35XX_DMA_EXT_DMAREQ1 3
-#define OMAP35XX_DMA_GPMC 4
-
-#define OMAP35XX_DMA_DSS_LINETRIGGER 6
-#define OMAP35XX_DMA_EXT_DMAREQ2 7
-
-#define OMAP35XX_DMA_SPI3_TX0 15
-#define OMAP35XX_DMA_SPI3_RX0 16
-#define OMAP35XX_DMA_MCBSP3_TX 17
-#define OMAP35XX_DMA_MCBSP3_RX 18
-#define OMAP35XX_DMA_MCBSP4_TX 19
-#define OMAP35XX_DMA_MCBSP4_RX 20
-#define OMAP35XX_DMA_MCBSP5_TX 21
-#define OMAP35XX_DMA_MCBSP5_RX 22
-#define OMAP35XX_DMA_SPI3_TX1 23
-#define OMAP35XX_DMA_SPI3_RX1 24
-#define OMAP35XX_DMA_I2C3_TX 25
-#define OMAP35XX_DMA_I2C3_RX 26
-#define OMAP35XX_DMA_I2C1_TX 27
-#define OMAP35XX_DMA_I2C1_RX 28
-#define OMAP35XX_DMA_I2C2_TX 29
-#define OMAP35XX_DMA_I2C2_RX 30
-#define OMAP35XX_DMA_MCBSP1_TX 31
-#define OMAP35XX_DMA_MCBSP1_RX 32
-#define OMAP35XX_DMA_MCBSP2_TX 33
-#define OMAP35XX_DMA_MCBSP2_RX 34
-#define OMAP35XX_DMA_SPI1_TX0 35
-#define OMAP35XX_DMA_SPI1_RX0 36
-#define OMAP35XX_DMA_SPI1_TX1 37
-#define OMAP35XX_DMA_SPI1_RX1 38
-#define OMAP35XX_DMA_SPI1_TX2 39
-#define OMAP35XX_DMA_SPI1_RX2 40
-#define OMAP35XX_DMA_SPI1_TX3 41
-#define OMAP35XX_DMA_SPI1_RX4 42
-#define OMAP35XX_DMA_SPI2_TX0 43
-#define OMAP35XX_DMA_SPI2_RX0 44
-#define OMAP35XX_DMA_SPI2_TX1 45
-#define OMAP35XX_DMA_SPI2_RX1 46
-#define OMAP35XX_DMA_MMC2_TX 47
-#define OMAP35XX_DMA_MMC2_RX 48
-#define OMAP35XX_DMA_UART1_TX 49
-#define OMAP35XX_DMA_UART1_RX 50
-#define OMAP35XX_DMA_UART2_TX 51
-#define OMAP35XX_DMA_UART2_RX 52
-#define OMAP35XX_DMA_UART3_TX 53
-#define OMAP35XX_DMA_UART3_RX 54
-
-#define OMAP35XX_DMA_MMC1_TX 61
-#define OMAP35XX_DMA_MMC1_RX 62
-#define OMAP35XX_DMA_MS 63
-#define OMAP35XX_DMA_EXT_DMAREQ3 64
-
-#define OMAP35XX_DMA_SPI4_TX0 70
-#define OMAP35XX_DMA_SPI4_RX0 71
-#define OMAP35XX_DMA_DSS0 72
-#define OMAP35XX_DMA_DSS1 73
-#define OMAP35XX_DMA_DSS2 74
-#define OMAP35XX_DMA_DSS3 75
-
-#define OMAP35XX_DMA_MMC3_TX 77
-#define OMAP35XX_DMA_MMC3_RX 78
+#define OMAP3XXX_DMA_NO_DEVICE 0
+
+#define OMAP3XXX_DMA_EXT_DMAREQ0 2
+#define OMAP3XXX_DMA_EXT_DMAREQ1 3
+#define OMAP3XXX_DMA_GPMC 4
+
+#define OMAP3XXX_DMA_DSS_LINETRIGGER 6
+#define OMAP3XXX_DMA_EXT_DMAREQ2 7
+
+#define OMAP3XXX_DMA_SPI3_TX0 15
+#define OMAP3XXX_DMA_SPI3_RX0 16
+#define OMAP3XXX_DMA_MCBSP3_TX 17
+#define OMAP3XXX_DMA_MCBSP3_RX 18
+#define OMAP3XXX_DMA_MCBSP4_TX 19
+#define OMAP3XXX_DMA_MCBSP4_RX 20
+#define OMAP3XXX_DMA_MCBSP5_TX 21
+#define OMAP3XXX_DMA_MCBSP5_RX 22
+#define OMAP3XXX_DMA_SPI3_TX1 23
+#define OMAP3XXX_DMA_SPI3_RX1 24
+#define OMAP3XXX_DMA_I2C3_TX 25
+#define OMAP3XXX_DMA_I2C3_RX 26
+#define OMAP3XXX_DMA_I2C1_TX 27
+#define OMAP3XXX_DMA_I2C1_RX 28
+#define OMAP3XXX_DMA_I2C2_TX 29
+#define OMAP3XXX_DMA_I2C2_RX 30
+#define OMAP3XXX_DMA_MCBSP1_TX 31
+#define OMAP3XXX_DMA_MCBSP1_RX 32
+#define OMAP3XXX_DMA_MCBSP2_TX 33
+#define OMAP3XXX_DMA_MCBSP2_RX 34
+#define OMAP3XXX_DMA_SPI1_TX0 35
+#define OMAP3XXX_DMA_SPI1_RX0 36
+#define OMAP3XXX_DMA_SPI1_TX1 37
+#define OMAP3XXX_DMA_SPI1_RX1 38
+#define OMAP3XXX_DMA_SPI1_TX2 39
+#define OMAP3XXX_DMA_SPI1_RX2 40
+#define OMAP3XXX_DMA_SPI1_TX3 41
+#define OMAP3XXX_DMA_SPI1_RX4 42
+#define OMAP3XXX_DMA_SPI2_TX0 43
+#define OMAP3XXX_DMA_SPI2_RX0 44
+#define OMAP3XXX_DMA_SPI2_TX1 45
+#define OMAP3XXX_DMA_SPI2_RX1 46
+#define OMAP3XXX_DMA_MMC2_TX 47
+#define OMAP3XXX_DMA_MMC2_RX 48
+#define OMAP3XXX_DMA_UART1_TX 49
+#define OMAP3XXX_DMA_UART1_RX 50
+#define OMAP3XXX_DMA_UART2_TX 51
+#define OMAP3XXX_DMA_UART2_RX 52
+#define OMAP3XXX_DMA_UART3_TX 53
+#define OMAP3XXX_DMA_UART3_RX 54
+
+#define OMAP3XXX_DMA_MMC1_TX 61
+#define OMAP3XXX_DMA_MMC1_RX 62
+#define OMAP3XXX_DMA_MS 63
+#define OMAP3XXX_DMA_EXT_DMAREQ3 64
+
+#define OMAP3XXX_DMA_SPI4_TX0 70
+#define OMAP3XXX_DMA_SPI4_RX0 71
+#define OMAP3XXX_DMA_DSS0 72
+#define OMAP3XXX_DMA_DSS1 73
+#define OMAP3XXX_DMA_DSS2 74
+#define OMAP3XXX_DMA_DSS3 75
+
+#define OMAP3XXX_DMA_MMC3_TX 77
+#define OMAP3XXX_DMA_MMC3_RX 78
/* omap[123].c */
uint32_t core_pm_iva2grpsel3;
uint32_t core_pm_mpugrpsel3;
- uint32_t prm_revision;
- uint32_t prm_sysconfig;
- uint32_t prm_irqstatus_mpu;
- uint32_t prm_irqenable_mpu;
-
- uint32_t prm_clksel;
- uint32_t prm_clkout_ctrl;
-
- uint32_t prm_vc_smps_sa;
- uint32_t prm_vc_smps_vol_ra;
- uint32_t prm_vc_smps_cmd_ra;
- uint32_t prm_vc_cmd_val_0;
- uint32_t prm_vc_cmd_val_1;
- uint32_t prm_vc_hc_conf;
- uint32_t prm_vc_i2c_cfg;
- uint32_t prm_vc_bypass_val;
- uint32_t prm_rstctrl;
- uint32_t prm_rsttimer;
- uint32_t prm_rstst;
- uint32_t prm_voltctrl;
- uint32_t prm_sram_pcharge;
- uint32_t prm_clksrc_ctrl;
- uint32_t prm_obs;
- uint32_t prm_voltsetup1;
- uint32_t prm_voltoffset;
- uint32_t prm_clksetup;
- uint32_t prm_polctrl;
- uint32_t prm_voltsetup2;
+ struct {
+ uint32_t prm_revision;
+ uint32_t prm_sysconfig;
+ uint32_t prm_irqstatus_mpu;
+ uint32_t prm_irqenable_mpu;
+ } ocp;
+
+ struct {
+ uint32_t prm_clksel;
+ uint32_t prm_clkout_ctrl;
+ } ccr; /* clock_control_reg */
+
+ struct {
+ uint32_t prm_vc_smps_sa;
+ uint32_t prm_vc_smps_vol_ra;
+ uint32_t prm_vc_smps_cmd_ra;
+ uint32_t prm_vc_cmd_val_0;
+ uint32_t prm_vc_cmd_val_1;
+ uint32_t prm_vc_hc_conf;
+ uint32_t prm_vc_i2c_cfg;
+ uint32_t prm_vc_bypass_val;
+ uint32_t prm_rstctrl;
+ uint32_t prm_rsttimer;
+ uint32_t prm_rstst;
+ uint32_t prm_voltctrl;
+ uint32_t prm_sram_pcharge;
+ uint32_t prm_clksrc_ctrl;
+ uint32_t prm_obs;
+ uint32_t prm_voltsetup1;
+ uint32_t prm_voltoffset;
+ uint32_t prm_clksetup;
+ uint32_t prm_polctrl;
+ uint32_t prm_voltsetup2;
+ } gr; /* global_reg */
};
static void omap3_prm_int_update(struct omap3_prm_s *s)
{
- qemu_set_irq(s->mpu_irq, s->prm_irqstatus_mpu & s->prm_irqenable_mpu);
+ qemu_set_irq(s->mpu_irq, s->ocp.prm_irqstatus_mpu & s->ocp.prm_irqenable_mpu);
qemu_set_irq(s->iva_irq, s->iva2_prm_irqstatus & s->iva2_prm_irqenable);
}
s->iva2_prm_irqstatus = 0x0;
s->iva2_prm_irqenable = 0x0;
- s->prm_revision = 0x10;
- s->prm_sysconfig = 0x1;
- s->prm_irqstatus_mpu = 0x0;
- s->prm_irqenable_mpu = 0x0;
+ s->ocp.prm_revision = 0x10;
+ s->ocp.prm_sysconfig = 0x1;
+ s->ocp.prm_irqstatus_mpu = 0x0;
+ s->ocp.prm_irqenable_mpu = 0x0;
s->mpu.rm_rstst = 0x1;
s->mpu.pm_wkdep = 0xa5;
s->wkup.pm_wkst = 0x0;
s->wkup.pm_pwstst = 0x3; /* TODO: check on real hardware */
- s->prm_clksel = 0x4;
- s->prm_clkout_ctrl = 0x80;
+ s->ccr.prm_clksel = 0x3; /* TRM says 0x4, but on HW this is 0x3 */
+ s->ccr.prm_clkout_ctrl = 0x80;
s->dss.rm_rstst = 0x1;
s->dss.pm_wken = 0x1;
s->emu.rm_rstst = 0x1;
s->emu.pm_pwstst = 0x13;
- s->prm_vc_smps_sa = 0x0;
- s->prm_vc_smps_vol_ra = 0x0;
- s->prm_vc_smps_cmd_ra = 0x0;
- s->prm_vc_cmd_val_0 = 0x0;
- s->prm_vc_cmd_val_1 = 0x0;
- s->prm_vc_hc_conf = 0x0;
- s->prm_vc_i2c_cfg = 0x18;
- s->prm_vc_bypass_val = 0x0;
- s->prm_rstctrl = 0x0;
- s->prm_rsttimer = 0x1006;
- s->prm_rstst = 0x1;
- s->prm_voltctrl = 0x0;
- s->prm_sram_pcharge = 0x50;
- s->prm_clksrc_ctrl = 0x43;
- s->prm_obs = 0x0;
- s->prm_voltsetup1 = 0x0;
- s->prm_voltoffset = 0x0;
- s->prm_clksetup = 0x0;
- s->prm_polctrl = 0xa;
- s->prm_voltsetup2 = 0x0;
+ s->gr.prm_vc_smps_sa = 0x0;
+ s->gr.prm_vc_smps_vol_ra = 0x0;
+ s->gr.prm_vc_smps_cmd_ra = 0x0;
+ s->gr.prm_vc_cmd_val_0 = 0x0;
+ s->gr.prm_vc_cmd_val_1 = 0x0;
+ s->gr.prm_vc_hc_conf = 0x0;
+ s->gr.prm_vc_i2c_cfg = 0x18;
+ s->gr.prm_vc_bypass_val = 0x0;
+ s->gr.prm_rstctrl = 0x0;
+ s->gr.prm_rsttimer = 0x1006;
+ s->gr.prm_rstst = 0x1;
+ s->gr.prm_voltctrl = 0x0;
+ s->gr.prm_sram_pcharge = 0x50;
+ s->gr.prm_clksrc_ctrl = 0x43;
+ s->gr.prm_obs = 0x0;
+ s->gr.prm_voltsetup1 = 0x0;
+ s->gr.prm_voltoffset = 0x0;
+ s->gr.prm_clksetup = 0x0;
+ s->gr.prm_polctrl = 0xa;
+ s->gr.prm_voltsetup2 = 0x0;
s->neon.rm_rstst = 0x1;
s->neon.pm_wkdep = 0x2;
switch (addr) {
case 0x00f8: return s->iva2_prm_irqstatus;
case 0x00fc: return s->iva2_prm_irqenable;
- case 0x0804: return s->prm_revision;
- case 0x0814: return s->prm_sysconfig;
- case 0x0818: return s->prm_irqstatus_mpu;
- case 0x081c: return s->prm_irqenable_mpu;
+ case 0x0804: return s->ocp.prm_revision;
+ case 0x0814: return s->ocp.prm_sysconfig;
+ case 0x0818: return s->ocp.prm_irqstatus_mpu;
+ case 0x081c: return s->ocp.prm_irqenable_mpu;
case 0x09d4: return s->mpu_pm_evgenctrl;
case 0x09d8: return s->mpu_pm_evgenontim;
case 0x09dc: return s->mpu_pm_evgenofftim;
case 0x0af0: return s->core_pm_wken3;
case 0x0af4: return s->core_pm_iva2grpsel3;
case 0x0af8: return s->core_pm_mpugrpsel3;
- case 0x0d40: return s->prm_clksel;
- case 0x0d70: return s->prm_clkout_ctrl;
+ case 0x0d40: return s->ccr.prm_clksel;
+ case 0x0d70: return s->ccr.prm_clkout_ctrl;
case 0x0de4: return 0x3; /* TODO: check on real hardware */
- case 0x1220: return s->prm_vc_smps_sa;
- case 0x1224: return s->prm_vc_smps_vol_ra;
- case 0x1228: return s->prm_vc_smps_cmd_ra;
- case 0x122c: return s->prm_vc_cmd_val_0;
- case 0x1230: return s->prm_vc_cmd_val_1;
- case 0x1234: return s->prm_vc_hc_conf;
- case 0x1238: return s->prm_vc_i2c_cfg;
- case 0x123c: return s->prm_vc_bypass_val;
- case 0x1250: return s->prm_rstctrl;
- case 0x1254: return s->prm_rsttimer;
- case 0x1258: return s->prm_rstst;
- case 0x1260: return s->prm_voltctrl;
- case 0x1264: return s->prm_sram_pcharge;
- case 0x1270: return s->prm_clksrc_ctrl;
- case 0x1280: return s->prm_obs;
- case 0x1290: return s->prm_voltsetup1;
- case 0x1294: return s->prm_voltoffset;
- case 0x1298: return s->prm_clksetup;
- case 0x129c: return s->prm_polctrl;
- case 0x12a0: return s->prm_voltsetup2;
+ case 0x1220: return s->gr.prm_vc_smps_sa;
+ case 0x1224: return s->gr.prm_vc_smps_vol_ra;
+ case 0x1228: return s->gr.prm_vc_smps_cmd_ra;
+ case 0x122c: return s->gr.prm_vc_cmd_val_0;
+ case 0x1230: return s->gr.prm_vc_cmd_val_1;
+ case 0x1234: return s->gr.prm_vc_hc_conf;
+ case 0x1238: return s->gr.prm_vc_i2c_cfg;
+ case 0x123c: return s->gr.prm_vc_bypass_val;
+ case 0x1250: return s->gr.prm_rstctrl;
+ case 0x1254: return s->gr.prm_rsttimer;
+ case 0x1258: return s->gr.prm_rstst;
+ case 0x1260: return s->gr.prm_voltctrl;
+ case 0x1264: return s->gr.prm_sram_pcharge;
+ case 0x1270: return s->gr.prm_clksrc_ctrl;
+ case 0x1280: return s->gr.prm_obs;
+ case 0x1290: return s->gr.prm_voltsetup1;
+ case 0x1294: return s->gr.prm_voltoffset;
+ case 0x1298: return s->gr.prm_clksetup;
+ case 0x129c: return s->gr.prm_polctrl;
+ case 0x12a0: return s->gr.prm_voltsetup2;
default: break;
}
omap_clk_setrate(omap_findclk(s->omap, "omap3_sys_clk"), 2, 1);
}
+static void omap3_prm_clksel_update(struct omap3_prm_s *s)
+{
+ omap_clk newparent = 0;
+
+ switch (s->ccr.prm_clksel & 7) {
+ case 0: newparent = omap_findclk(s->omap, "omap3_osc_sys_clk12"); break;
+ case 1: newparent = omap_findclk(s->omap, "omap3_osc_sys_clk13"); break;
+ case 2: newparent = omap_findclk(s->omap, "omap3_osc_sys_clk192"); break;
+ case 3: newparent = omap_findclk(s->omap, "omap3_osc_sys_clk26"); break;
+ case 4: newparent = omap_findclk(s->omap, "omap3_osc_sys_clk384"); break;
+ case 5: newparent = omap_findclk(s->omap, "omap3_osc_sys_clk168"); break;
+ default:
+ fprintf(stderr, "%s: invalid sys_clk input selection (%d) - ignored\n",
+ __FUNCTION__, s->ccr.prm_clksel & 7);
+ break;
+ }
+ if (newparent) {
+ omap_clk_reparent(omap_findclk(s->omap, "omap3_sys_clk"), newparent);
+ omap_clk_reparent(omap_findclk(s->omap, "omap3_sys_clkout1"), newparent);
+ }
+}
+
static void omap3_prm_write(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
break;
/* OCP_System_Reg_PRM */
case 0x0804: OMAP_RO_REG(addr); break;
- case 0x0814: s->prm_sysconfig = value & 0x1; break;
+ case 0x0814: s->ocp.prm_sysconfig = value & 0x1; break;
case 0x0818:
- s->prm_irqstatus_mpu &= ~(value & 0x03c003fd);
+ s->ocp.prm_irqstatus_mpu &= ~(value & 0x03c003fd);
omap3_prm_int_update(s);
break;
case 0x081c:
- s->prm_irqenable_mpu = value & 0x03c003fd;
+ s->ocp.prm_irqenable_mpu = value & 0x03c003fd;
omap3_prm_int_update(s);
break;
/* MPU_PRM */
case 0x0cb0: s->wkup.pm_wkst &= ~(value & 0x0103cb); break;
/* Clock_Control_Reg_PRM */
case 0x0d40:
- s->prm_clksel = value & 0x7;
- fprintf(stderr, "%s PRM_CLKSEL = 0x%x\n", __FUNCTION__,
- s->prm_clksel);
- /* TODO: update clocks */
+ s->ccr.prm_clksel = value & 0x7;
+ omap3_prm_clksel_update(s);
break;
case 0x0d70:
- s->prm_clkout_ctrl = value & 0x80;
- fprintf(stderr, "%s PRM_CLKOUT_CTRL = 0x%x\n", __FUNCTION__,
- s->prm_clkout_ctrl);
- /* TODO: update clocks */
+ s->ccr.prm_clkout_ctrl = value & 0x80;
+ omap_clk_onoff(omap_findclk(s->omap, "omap3_sys_clkout1"),
+ s->ccr.prm_clkout_ctrl & 0x80);
break;
/* DSS_PRM */
case 0x0e58: s->dss.rm_rstst &= ~(value & 0xf); break;
case 0x1158: s->emu.rm_rstst &= ~(value & 7); break;
case 0x11e4: OMAP_RO_REG(addr); break;
/* Global_Reg_PRM */
- case 0x1220: s->prm_vc_smps_sa = value & 0x7f007f; break;
- case 0x1224: s->prm_vc_smps_vol_ra = value & 0xff00ff; break;
- case 0x1228: s->prm_vc_smps_cmd_ra = value & 0xff00ff; break;
- case 0x122c: s->prm_vc_cmd_val_0 = value; break;
- case 0x1230: s->prm_vc_cmd_val_1 = value; break;
- case 0x1234: s->prm_vc_hc_conf = value & 0x1f001f; break;
- case 0x1238: s->prm_vc_i2c_cfg = value & 0x3f; break;
- case 0x123c: s->prm_vc_bypass_val = value & 0x01ffff7f; break;
- case 0x1250: s->prm_rstctrl = 0; break; /* TODO: resets */
- case 0x1254: s->prm_rsttimer = value & 0x1fff; break;
- case 0x1258: s->prm_rstst &= ~(value & 0x7fb); break;
- case 0x1260: s->prm_voltctrl = value & 0x1f; break;
- case 0x1264: s->prm_sram_pcharge = value & 0xff; break;
+ case 0x1220: s->gr.prm_vc_smps_sa = value & 0x7f007f; break;
+ case 0x1224: s->gr.prm_vc_smps_vol_ra = value & 0xff00ff; break;
+ case 0x1228: s->gr.prm_vc_smps_cmd_ra = value & 0xff00ff; break;
+ case 0x122c: s->gr.prm_vc_cmd_val_0 = value; break;
+ case 0x1230: s->gr.prm_vc_cmd_val_1 = value; break;
+ case 0x1234: s->gr.prm_vc_hc_conf = value & 0x1f001f; break;
+ case 0x1238: s->gr.prm_vc_i2c_cfg = value & 0x3f; break;
+ case 0x123c: s->gr.prm_vc_bypass_val = value & 0x01ffff7f; break;
+ case 0x1250: s->gr.prm_rstctrl = 0; break; /* TODO: resets */
+ case 0x1254: s->gr.prm_rsttimer = value & 0x1fff; break;
+ case 0x1258: s->gr.prm_rstst &= ~(value & 0x7fb); break;
+ case 0x1260: s->gr.prm_voltctrl = value & 0x1f; break;
+ case 0x1264: s->gr.prm_sram_pcharge = value & 0xff; break;
case 0x1270:
- s->prm_clksrc_ctrl = value & (0xd8);
- omap3_prm_clksrc_ctrl_update(s, s->prm_clksrc_ctrl);
- /* TODO: update SYSCLKSEL bits */
+ s->gr.prm_clksrc_ctrl = value & 0xd8; /* set osc bypass mode */
+ omap3_prm_clksrc_ctrl_update(s, s->gr.prm_clksrc_ctrl);
break;
case 0x1280: OMAP_RO_REG(addr); break;
- case 0x1290: s->prm_voltsetup1 = value; break;
- case 0x1294: s->prm_voltoffset = value & 0xffff; break;
- case 0x1298: s->prm_clksetup = value & 0xffff; break;
- case 0x129c: s->prm_polctrl = value & 0xf; break;
- case 0x12a0: s->prm_voltsetup2 = value & 0xffff; break;
+ case 0x1290: s->gr.prm_voltsetup1 = value; break;
+ case 0x1294: s->gr.prm_voltoffset = value & 0xffff; break;
+ case 0x1298: s->gr.prm_clksetup = value & 0xffff; break;
+ case 0x129c: s->gr.prm_polctrl = value & 0xf; break;
+ case 0x12a0: s->gr.prm_voltsetup2 = value & 0xffff; break;
/* NEON_PRM */
case 0x1358: s->neon.rm_rstst &= ~(value & 0xf); break;
case 0x13c8: s->neon.pm_wkdep = value & 0x2; break;
return s;
}
+#define OMAP3_BOOT_ROM_SIZE 0x1c000 /* 80 + 32 KB */
+static const uint8_t omap3_boot_rom[] = {
+ 0x0e, 0xf0, 0xb0, 0xe1, /* movs pc, lr */
+ 0x0e, 0xf0, 0xb0, 0xe1, /* movs pc, lr */
+ 0x0e, 0xf0, 0xb0, 0xe1, /* movs pc, lr */
+ 0x04, 0xf0, 0x5e, 0xe2, /* subs pc, lr, #4 */
+ 0x08, 0xf0, 0x5e, 0xe2, /* subs pc, lr, #8 */
+ 0x0e, 0xf0, 0xb0, 0xe1, /* movs pc, lr */
+ 0x04, 0xf0, 0x5e, 0xe2, /* subs pc, lr, #4 */
+ 0x04, 0xf0, 0x5e, 0xe2, /* subs pc, lr, #4 */
+};
+
static const struct dma_irq_map omap3_dma_irq_map[] = {
- {0, OMAP_INT_35XX_SDMA_IRQ0},
- {0, OMAP_INT_35XX_SDMA_IRQ1},
- {0, OMAP_INT_35XX_SDMA_IRQ2},
- {0, OMAP_INT_35XX_SDMA_IRQ3},
+ {0, OMAP_INT_3XXX_SDMA_IRQ0},
+ {0, OMAP_INT_3XXX_SDMA_IRQ1},
+ {0, OMAP_INT_3XXX_SDMA_IRQ2},
+ {0, OMAP_INT_3XXX_SDMA_IRQ3},
};
static int omap3_validate_addr(struct omap_mpu_state_s *s,
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *)
qemu_mallocz(sizeof(struct omap_mpu_state_s));
- ram_addr_t sram_base, q2_base;
+ ram_addr_t sram_base, q2_base, bootrom_base;
qemu_irq *cpu_irq;
qemu_irq dma_irqs[4];
int i;
exit(1);
}
s->sdram_size = sdram_size;
- s->sram_size = OMAP3530_SRAM_SIZE;
+ s->sram_size = OMAP3XXX_SRAM_SIZE;
/* Clocks */
omap_clk_init(s);
q2_base = qemu_ram_alloc(s->sdram_size);
cpu_register_physical_memory(OMAP3_Q2_BASE, s->sdram_size,
- (q2_base | IO_MEM_RAM));
+ q2_base | IO_MEM_RAM);
sram_base = qemu_ram_alloc(s->sram_size);
cpu_register_physical_memory(OMAP3_SRAM_BASE, s->sram_size,
- (sram_base | IO_MEM_RAM));
+ sram_base | IO_MEM_RAM);
+ bootrom_base = qemu_ram_alloc(OMAP3XXX_BOOTROM_SIZE);
+ cpu_register_physical_memory(OMAP3_Q1_BASE, OMAP3_BOOT_ROM_SIZE,
+ bootrom_base | IO_MEM_ROM);
+ cpu_register_physical_memory(0, OMAP3_BOOT_ROM_SIZE,
+ bootrom_base | IO_MEM_ROM);
+ cpu_physical_memory_write_rom(OMAP3_Q1_BASE, omap3_boot_rom,
+ sizeof(omap3_boot_rom));
s->l4 = omap_l4_init(OMAP3_L4_BASE,
sizeof(omap3_l4_agent_info)
s->omap3_cm = omap3_cm_init(omap3_l4ta_init(s->l4, L4A_CM), NULL, NULL, NULL, s);
s->omap3_prm = omap3_prm_init(omap3_l4ta_init(s->l4, L4A_PRM),
- s->irq[0][OMAP_INT_35XX_PRCM_MPU_IRQ],
+ s->irq[0][OMAP_INT_3XXX_PRCM_MPU_IRQ],
NULL, s);
s->omap3_mpu_wdt = omap3_mpu_wdt_init(omap3_l4ta_init(s->l4, L4A_WDTIMER2),
s->omap3_sms = omap3_sms_init(s);
s->gptimer[0] = omap_gp_timer_init(omap3_l4ta_init(s->l4, L4A_GPTIMER1),
- s->irq[0][OMAP_INT_35XX_GPT1_IRQ],
+ s->irq[0][OMAP_INT_3XXX_GPT1_IRQ],
omap_findclk(s, "omap3_gp1_fclk"),
omap_findclk(s, "omap3_wkup_l4_iclk"));
s->gptimer[1] = omap_gp_timer_init(omap3_l4ta_init(s->l4, L4A_GPTIMER2),
- s->irq[0][OMAP_INT_35XX_GPT2_IRQ],
+ s->irq[0][OMAP_INT_3XXX_GPT2_IRQ],
omap_findclk(s, "omap3_gp2_fclk"),
omap_findclk(s, "omap3_per_l4_iclk"));
s->gptimer[2] = omap_gp_timer_init(omap3_l4ta_init(s->l4, L4A_GPTIMER3),
- s->irq[0][OMAP_INT_35XX_GPT3_IRQ],
+ s->irq[0][OMAP_INT_3XXX_GPT3_IRQ],
omap_findclk(s, "omap3_gp3_fclk"),
omap_findclk(s, "omap3_per_l4_iclk"));
s->gptimer[3] = omap_gp_timer_init(omap3_l4ta_init(s->l4, L4A_GPTIMER4),
- s->irq[0][OMAP_INT_35XX_GPT4_IRQ],
+ s->irq[0][OMAP_INT_3XXX_GPT4_IRQ],
omap_findclk(s, "omap3_gp4_fclk"),
omap_findclk(s, "omap3_per_l4_iclk"));
s->gptimer[4] = omap_gp_timer_init(omap3_l4ta_init(s->l4, L4A_GPTIMER5),
- s->irq[0][OMAP_INT_35XX_GPT5_IRQ],
+ s->irq[0][OMAP_INT_3XXX_GPT5_IRQ],
omap_findclk(s, "omap3_gp5_fclk"),
omap_findclk(s, "omap3_per_l4_iclk"));
s->gptimer[5] = omap_gp_timer_init(omap3_l4ta_init(s->l4, L4A_GPTIMER6),
- s->irq[0][OMAP_INT_35XX_GPT6_IRQ],
+ s->irq[0][OMAP_INT_3XXX_GPT6_IRQ],
omap_findclk(s, "omap3_gp6_fclk"),
omap_findclk(s, "omap3_per_l4_iclk"));
s->gptimer[6] = omap_gp_timer_init(omap3_l4ta_init(s->l4, L4A_GPTIMER7),
- s->irq[0][OMAP_INT_35XX_GPT7_IRQ],
+ s->irq[0][OMAP_INT_3XXX_GPT7_IRQ],
omap_findclk(s, "omap3_gp7_fclk"),
omap_findclk(s, "omap3_per_l4_iclk"));
s->gptimer[7] = omap_gp_timer_init(omap3_l4ta_init(s->l4, L4A_GPTIMER8),
- s->irq[0][OMAP_INT_35XX_GPT8_IRQ],
+ s->irq[0][OMAP_INT_3XXX_GPT8_IRQ],
omap_findclk(s, "omap3_gp8_fclk"),
omap_findclk(s, "omap3_per_l4_iclk"));
s->gptimer[8] = omap_gp_timer_init(omap3_l4ta_init(s->l4, L4A_GPTIMER9),
- s->irq[0][OMAP_INT_35XX_GPT9_IRQ],
+ s->irq[0][OMAP_INT_3XXX_GPT9_IRQ],
omap_findclk(s, "omap3_gp9_fclk"),
omap_findclk(s, "omap3_per_l4_iclk"));
s->gptimer[9] = omap_gp_timer_init(omap3_l4ta_init(s->l4, L4A_GPTIMER10),
- s->irq[0][OMAP_INT_35XX_GPT10_IRQ],
+ s->irq[0][OMAP_INT_3XXX_GPT10_IRQ],
omap_findclk(s, "omap3_gp10_fclk"),
omap_findclk(s, "omap3_core_l4_iclk"));
s->gptimer[10] = omap_gp_timer_init(omap3_l4ta_init(s->l4, L4A_GPTIMER11),
- s->irq[0][OMAP_INT_35XX_GPT11_IRQ],
+ s->irq[0][OMAP_INT_3XXX_GPT11_IRQ],
omap_findclk(s, "omap3_gp12_fclk"),
omap_findclk(s, "omap3_core_l4_iclk"));
s->gptimer[11] = omap_gp_timer_init(omap3_l4ta_init(s->l4, L4A_GPTIMER12),
- s->irq[0][OMAP_INT_35XX_GPT12_IRQ],
+ s->irq[0][OMAP_INT_3XXX_GPT12_IRQ],
omap_findclk(s, "omap3_gp12_fclk"),
omap_findclk(s, "omap3_wkup_l4_iclk"));
s->sdrc = omap_sdrc_init(0x6d000000);
- s->gpmc = omap_gpmc_init(s, 0x6e000000, s->irq[0][OMAP_INT_35XX_GPMC_IRQ]);
+ s->gpmc = omap_gpmc_init(s, 0x6e000000, s->irq[0][OMAP_INT_3XXX_GPMC_IRQ]);
s->uart[0] = omap2_uart_init(omap3_l4ta_init(s->l4, L4A_UART1),
- s->irq[0][OMAP_INT_35XX_UART1_IRQ],
+ s->irq[0][OMAP_INT_3XXX_UART1_IRQ],
omap_findclk(s, "omap3_uart1_fclk"),
omap_findclk(s, "omap3_uart1_iclk"),
- s->drq[OMAP35XX_DMA_UART1_TX],
- s->drq[OMAP35XX_DMA_UART1_RX], 0);
+ s->drq[OMAP3XXX_DMA_UART1_TX],
+ s->drq[OMAP3XXX_DMA_UART1_RX], 0);
s->uart[1] = omap2_uart_init(omap3_l4ta_init(s->l4, L4A_UART2),
- s->irq[0][OMAP_INT_35XX_UART2_IRQ],
+ s->irq[0][OMAP_INT_3XXX_UART2_IRQ],
omap_findclk(s, "omap3_uart2_fclk"),
omap_findclk(s, "omap3_uart2_iclk"),
- s->drq[OMAP35XX_DMA_UART2_TX],
- s->drq[OMAP35XX_DMA_UART2_RX], 0);
+ s->drq[OMAP3XXX_DMA_UART2_TX],
+ s->drq[OMAP3XXX_DMA_UART2_RX], 0);
s->uart[2] = omap2_uart_init(omap3_l4ta_init(s->l4, L4A_UART3),
- s->irq[0][OMAP_INT_35XX_UART3_IRQ],
+ s->irq[0][OMAP_INT_3XXX_UART3_IRQ],
omap_findclk(s, "omap3_uart2_fclk"),
omap_findclk(s, "omap3_uart3_iclk"),
- s->drq[OMAP35XX_DMA_UART3_TX],
- s->drq[OMAP35XX_DMA_UART3_RX], 0);
+ s->drq[OMAP3XXX_DMA_UART3_TX],
+ s->drq[OMAP3XXX_DMA_UART3_RX], 0);
s->dss = omap_dss_init(s, omap3_l4ta_init(s->l4, L4A_DSS),
- s->irq[0][OMAP_INT_35XX_DSS_IRQ], s->drq[OMAP24XX_DMA_DSS],
+ s->irq[0][OMAP_INT_3XXX_DSS_IRQ], s->drq[OMAP24XX_DMA_DSS],
NULL,NULL,NULL,NULL,NULL);
s->gpif = omap3_gpif_init();
omap3_gpio_init(s, s->gpif ,omap3_l4ta_init(s->l4, L4A_GPIO1),
- &s->irq[0][OMAP_INT_35XX_GPIO1_MPU_IRQ],
+ &s->irq[0][OMAP_INT_3XXX_GPIO1_MPU_IRQ],
NULL,NULL,0);
omap3_gpio_init(s, s->gpif ,omap3_l4ta_init(s->l4, L4A_GPIO2),
- &s->irq[0][OMAP_INT_35XX_GPIO2_MPU_IRQ],
+ &s->irq[0][OMAP_INT_3XXX_GPIO2_MPU_IRQ],
NULL,NULL,1);
omap3_gpio_init(s, s->gpif ,omap3_l4ta_init(s->l4, L4A_GPIO3),
- &s->irq[0][OMAP_INT_35XX_GPIO3_MPU_IRQ],
+ &s->irq[0][OMAP_INT_3XXX_GPIO3_MPU_IRQ],
NULL,NULL,2);
omap3_gpio_init(s, s->gpif ,omap3_l4ta_init(s->l4, L4A_GPIO4),
- &s->irq[0][OMAP_INT_35XX_GPIO4_MPU_IRQ],
+ &s->irq[0][OMAP_INT_3XXX_GPIO4_MPU_IRQ],
NULL,NULL,3);
omap3_gpio_init(s, s->gpif ,omap3_l4ta_init(s->l4, L4A_GPIO5),
- &s->irq[0][OMAP_INT_35XX_GPIO5_MPU_IRQ],
+ &s->irq[0][OMAP_INT_3XXX_GPIO5_MPU_IRQ],
NULL,NULL,4);
omap3_gpio_init(s, s->gpif ,omap3_l4ta_init(s->l4, L4A_GPIO6),
- &s->irq[0][OMAP_INT_35XX_GPIO6_MPU_IRQ],
+ &s->irq[0][OMAP_INT_3XXX_GPIO6_MPU_IRQ],
NULL,NULL,5);
omap_tap_init(omap3_l4ta_init(s->l4, L4A_TAP), s);
s->omap3_mmc[0] = omap3_mmc_init(omap3_l4ta_init(s->l4, L4A_MMC1),
- s->irq[0][OMAP_INT_35XX_MMC1_IRQ],
- &s->drq[OMAP35XX_DMA_MMC1_TX],
+ s->irq[0][OMAP_INT_3XXX_MMC1_IRQ],
+ &s->drq[OMAP3XXX_DMA_MMC1_TX],
omap_findclk(s, "omap3_mmc1_fclk"),
omap_findclk(s, "omap3_mmc1_iclk"));
s->omap3_mmc[1] = omap3_mmc_init(omap3_l4ta_init(s->l4, L4A_MMC2),
- s->irq[0][OMAP_INT_35XX_MMC2_IRQ],
- &s->drq[OMAP35XX_DMA_MMC2_TX],
+ s->irq[0][OMAP_INT_3XXX_MMC2_IRQ],
+ &s->drq[OMAP3XXX_DMA_MMC2_TX],
omap_findclk(s, "omap3_mmc2_fclk"),
omap_findclk(s, "omap3_mmc2_iclk"));
s->omap3_mmc[2] = omap3_mmc_init(omap3_l4ta_init(s->l4, L4A_MMC3),
- s->irq[0][OMAP_INT_35XX_MMC3_IRQ],
- &s->drq[OMAP35XX_DMA_MMC3_TX],
+ s->irq[0][OMAP_INT_3XXX_MMC3_IRQ],
+ &s->drq[OMAP3XXX_DMA_MMC3_TX],
omap_findclk(s, "omap3_mmc3_fclk"),
omap_findclk(s, "omap3_mmc3_iclk"));
s->i2c[0] = omap3_i2c_init(omap3_l4ta_init(s->l4, L4A_I2C1),
- s->irq[0][OMAP_INT_35XX_I2C1_IRQ],
- &s->drq[OMAP35XX_DMA_I2C1_TX],
+ s->irq[0][OMAP_INT_3XXX_I2C1_IRQ],
+ &s->drq[OMAP3XXX_DMA_I2C1_TX],
omap_findclk(s, "omap3_i2c1_fclk"),
omap_findclk(s, "omap3_i2c1_iclk"),
8);
s->i2c[1] = omap3_i2c_init(omap3_l4ta_init(s->l4, L4A_I2C2),
- s->irq[0][OMAP_INT_35XX_I2C2_IRQ],
- &s->drq[OMAP35XX_DMA_I2C2_TX],
+ s->irq[0][OMAP_INT_3XXX_I2C2_IRQ],
+ &s->drq[OMAP3XXX_DMA_I2C2_TX],
omap_findclk(s, "omap3_i2c2_fclk"),
omap_findclk(s, "omap3_i2c2_iclk"),
8);
s->i2c[2] = omap3_i2c_init(omap3_l4ta_init(s->l4, L4A_I2C3),
- s->irq[0][OMAP_INT_35XX_I2C3_IRQ],
- &s->drq[OMAP35XX_DMA_I2C3_TX],
+ s->irq[0][OMAP_INT_3XXX_I2C3_IRQ],
+ &s->drq[OMAP3XXX_DMA_I2C3_TX],
omap_findclk(s, "omap3_i2c3_fclk"),
omap_findclk(s, "omap3_i2c3_iclk"),
64);
s->omap3_usb = omap3_hsusb_init(omap3_l4ta_init(s->l4, L4A_USBHS_OTG),
omap3_l4ta_init(s->l4, L4A_USBHS_HOST),
omap3_l4ta_init(s->l4, L4A_USBHS_TLL),
- s->irq[0][OMAP_INT_35XX_HSUSB_MC],
- s->irq[0][OMAP_INT_35XX_HSUSB_DMA],
- s->irq[0][OMAP_INT_35XX_OHCI_IRQ],
- s->irq[0][OMAP_INT_35XX_EHCI_IRQ],
- s->irq[0][OMAP_INT_35XX_TLL_IRQ]);
+ s->irq[0][OMAP_INT_3XXX_HSUSB_MC],
+ s->irq[0][OMAP_INT_3XXX_HSUSB_DMA],
+ s->irq[0][OMAP_INT_3XXX_OHCI_IRQ],
+ s->irq[0][OMAP_INT_3XXX_EHCI_IRQ],
+ s->irq[0][OMAP_INT_3XXX_TLL_IRQ]);
return s;
}
#define CLOCK_IN_OMAP242X (1 << 14)
#define CLOCK_IN_OMAP243X (1 << 15)
#define CLOCK_IN_OMAP343X (1 << 16)
-#define CLOCK_IN_OMAP353X (1 << 17)
+#define CLOCK_IN_OMAP3XXX (1 << 17)
uint32_t flags;
int id;
.parent = &core_l4_iclk,
};
-/*OMAP3 Clocks*/
+/* OMAP3 Clocks */
static struct clk omap3_sys_32k = {
.name = "omap3_sys_32k",
.rate = 32768,
- .flags = CLOCK_IN_OMAP353X | ALWAYS_ENABLED,
+ .flags = CLOCK_IN_OMAP3XXX | ALWAYS_ENABLED,
};
-static struct clk omap3_sys_xtalin = {
- .name = "omap3_sys_xtalin",
+static struct clk omap3_osc_sys_clk12 = {
+ .name = "omap3_osc_sys_clk12",
+ .rate = 12000000,
+ .flags = CLOCK_IN_OMAP3XXX | ALWAYS_ENABLED,
+};
+
+static struct clk omap3_osc_sys_clk13 = {
+ .name = "omap3_osc_sys_clk13",
+ .rate = 13000000,
+ .flags = CLOCK_IN_OMAP3XXX | ALWAYS_ENABLED,
+};
+
+static struct clk omap3_osc_sys_clk168 = {
+ .name = "omap3_osc_sys_clk168",
+ .rate = 16800000,
+ .flags = CLOCK_IN_OMAP3XXX | ALWAYS_ENABLED,
+};
+
+static struct clk omap3_osc_sys_clk192 = {
+ .name = "omap3_osc_sys_clk192",
+ .rate = 19200000,
+ .flags = CLOCK_IN_OMAP3XXX | ALWAYS_ENABLED,
+};
+
+static struct clk omap3_osc_sys_clk26 = {
+ .name = "omap3_osc_sys_clk26",
.rate = 26000000,
- .flags = CLOCK_IN_OMAP353X | ALWAYS_ENABLED,
+ .flags = CLOCK_IN_OMAP3XXX | ALWAYS_ENABLED,
+};
+
+static struct clk omap3_osc_sys_clk384 = {
+ .name = "omap3_osc_sys_clk384",
+ .rate = 38400000,
+ .flags = CLOCK_IN_OMAP3XXX | ALWAYS_ENABLED,
};
/*Is the altclk is enabled in beagle board?*/
static struct clk omap3_sys_altclk = {
.name = "omap3_sys_altclk",
.rate = 13000000,
- .flags = CLOCK_IN_OMAP353X ,
+ .flags = CLOCK_IN_OMAP3XXX ,
};
/*PRM*/
static struct clk omap3_sys_clk = {
.name = "omap3_sys_clk",
- .flags = CLOCK_IN_OMAP353X | ALWAYS_ENABLED,
- .parent = &omap3_sys_xtalin,
+ .flags = CLOCK_IN_OMAP3XXX | ALWAYS_ENABLED,
+ .parent = &omap3_osc_sys_clk26,
};
static struct clk omap3_32k_fclk = {
.name = "omap3_32k_fclk",
.rate = 32768,
- .flags = CLOCK_IN_OMAP353X | ALWAYS_ENABLED,
+ .flags = CLOCK_IN_OMAP3XXX | ALWAYS_ENABLED,
.parent = &omap3_sys_32k,
};
*/
static struct clk omap3_core_clk = {
.name = "omap3_core_clk",
- .flags = CLOCK_IN_OMAP353X | ALWAYS_ENABLED,
+ .flags = CLOCK_IN_OMAP3XXX | ALWAYS_ENABLED,
.parent = &omap3_sys_clk,
};
static struct clk omap3_core2_clk = {
.name = "omap3_core2_clk",
- .flags = CLOCK_IN_OMAP353X ,
+ .flags = CLOCK_IN_OMAP3XXX ,
.parent = &omap3_sys_clk,
};
static struct clk omap3_emu_core_alwon_clk = {
.name = "omap3_emu_core_alwon_clk",
- .flags = CLOCK_IN_OMAP353X ,
+ .flags = CLOCK_IN_OMAP3XXX ,
.parent = &omap3_sys_clk,
};
*/
static struct clk omap3_mpu_clk = {
.name = "omap3_mpu_clk",
- .flags = CLOCK_IN_OMAP353X ,
+ .flags = CLOCK_IN_OMAP3XXX ,
.parent = &omap3_core_clk, /*between sys_clk and core_clk*/
};
/*DPLL2: it is for iva2*/
static struct clk omap3_iva2_clk = {
.name = "omap3_iva2_clk",
- .flags = CLOCK_IN_OMAP353X ,
+ .flags = CLOCK_IN_OMAP3XXX ,
.parent = &omap3_core_clk, /*between sys_clk and core_clk*/
};
*/
static struct clk omap3_96m_fclk = {
.name = "omap3_96m_fclk",
- .flags = CLOCK_IN_OMAP353X ,
+ .flags = CLOCK_IN_OMAP3XXX ,
.parent = &omap3_sys_clk,
};
static struct clk omap3_54m_fclk = {
.name = "omap3_54m_fclk",
- .flags = CLOCK_IN_OMAP353X ,
+ .flags = CLOCK_IN_OMAP3XXX ,
.parent = &omap3_sys_clk,
};
static struct clk omap3_dss1_alwon_fclk = {
.name = "omap3_dss1_alwon_fclk",
- .flags = CLOCK_IN_OMAP353X ,
+ .flags = CLOCK_IN_OMAP3XXX ,
.parent = &omap3_sys_clk,
};
static struct clk omap3_cam_mclk = {
.name = "omap3_cam_mclk",
- .flags = CLOCK_IN_OMAP353X ,
+ .flags = CLOCK_IN_OMAP3XXX ,
.parent = &omap3_sys_clk,
};
static struct clk omap3_per_alwon_clk = {
.name = "omap3_per_alwon_clk",
- .flags = CLOCK_IN_OMAP353X ,
+ .flags = CLOCK_IN_OMAP3XXX ,
.parent = &omap3_sys_clk,
};
*/
static struct clk omap3_120m_fclk = {
.name = "omap3_120m_fclk",
- .flags = CLOCK_IN_OMAP353X ,
+ .flags = CLOCK_IN_OMAP3XXX ,
.parent = &omap3_sys_clk,
};
/*CM*/
static struct clk omap3_48m_fclk = {
.name = "omap3_48m_fclk",
- .flags = CLOCK_IN_OMAP353X ,
+ .flags = CLOCK_IN_OMAP3XXX ,
.parent = &omap3_96m_fclk, /*omap3_96m_fclk and omap3_sys_altclk*/
};
static struct clk omap3_12m_fclk = {
.name = "omap3_12m_fclk",
- .flags = CLOCK_IN_OMAP353X ,
+ .flags = CLOCK_IN_OMAP3XXX ,
.parent = &omap3_48m_fclk, /*omap3_48m_fclk and omap3_sys_altclk*/
};
*/
static struct clk omap3_l3x2_iclk = {
.name = "omap3_l3x2_iclk",
- .flags = CLOCK_IN_OMAP353X | ALWAYS_ENABLED,
+ .flags = CLOCK_IN_OMAP3XXX | ALWAYS_ENABLED,
.parent = &omap3_core_clk,
};
static struct clk omap3_l3_iclk = {
.name = "omap3_l3_iclk",
- .flags = CLOCK_IN_OMAP353X | ALWAYS_ENABLED,
+ .flags = CLOCK_IN_OMAP3XXX | ALWAYS_ENABLED,
.parent = &omap3_core_clk,
};
static struct clk omap3_l4_iclk = {
.name = "omap3_l4_iclk",
- .flags = CLOCK_IN_OMAP353X | ALWAYS_ENABLED,
+ .flags = CLOCK_IN_OMAP3XXX | ALWAYS_ENABLED,
.parent = &omap3_l3_iclk,
};
static struct clk omap3_rm_iclk = {
.name = "omap3_rm_iclk",
- .flags = CLOCK_IN_OMAP353X | ALWAYS_ENABLED,
+ .flags = CLOCK_IN_OMAP3XXX | ALWAYS_ENABLED,
.parent = &omap3_l4_iclk,
};
*/
static struct clk omap3_gp10_fclk = {
.name = "omap3_gp10_fclk",
- .flags = CLOCK_IN_OMAP353X,
+ .flags = CLOCK_IN_OMAP3XXX,
.parent = &omap3_32k_fclk, /*omap3_32k_fclk and omap3_sys_clk*/
};
static struct clk omap3_gp11_fclk = {
.name = "omap3_gp11_fclk",
- .flags = CLOCK_IN_OMAP353X,
+ .flags = CLOCK_IN_OMAP3XXX,
.parent = &omap3_32k_fclk, /*omap3_32k_fclk and omap3_sys_clk*/
};
static struct clk omap3_core_32k_fclk = {
.name = "omap3_core_32k_fclk",
- .flags = CLOCK_IN_OMAP353X,
+ .flags = CLOCK_IN_OMAP3XXX,
.parent = &omap3_32k_fclk,
};
static struct clk omap3_cpefuse_fclk = {
.name = "omap3_cpefuse_fclk",
- .flags = CLOCK_IN_OMAP353X,
+ .flags = CLOCK_IN_OMAP3XXX,
.parent = &omap3_sys_clk,
};
static struct clk omap3_core_120m_fclk = {
.name = "omap3_core_120m_fclk",
- .flags = CLOCK_IN_OMAP353X,
+ .flags = CLOCK_IN_OMAP3XXX,
.parent = &omap3_120m_fclk,
};
static struct clk omap3_core_96m_fclk = {
.name = "omap3_core_96m_fclk",
- .flags = CLOCK_IN_OMAP353X,
+ .flags = CLOCK_IN_OMAP3XXX,
.parent = &omap3_96m_fclk,
};
static struct clk omap3_core_48m_fclk = {
.name = "omap3_core_48m_fclk",
- .flags = CLOCK_IN_OMAP353X,
+ .flags = CLOCK_IN_OMAP3XXX,
.parent = &omap3_48m_fclk,
};
static struct clk omap3_core_12m_fclk = {
.name = "omap3_core_12m_fclk",
- .flags = CLOCK_IN_OMAP353X,
+ .flags = CLOCK_IN_OMAP3XXX,
.parent = &omap3_12m_fclk,
};
static struct clk omap3_core_l3_iclk = {
.name = "omap3_core_l3_iclk",
- .flags = CLOCK_IN_OMAP353X | ALWAYS_ENABLED,
+ .flags = CLOCK_IN_OMAP3XXX | ALWAYS_ENABLED,
.parent = &omap3_l3_iclk,
};
static struct clk omap3_core_l4_iclk = {
.name = "omap3_core_l4_iclk",
- .flags = CLOCK_IN_OMAP353X | ALWAYS_ENABLED,
+ .flags = CLOCK_IN_OMAP3XXX | ALWAYS_ENABLED,
.parent = &omap3_l4_iclk,
};
/*WKUP Power Domain*/
static struct clk omap3_wkup_32k_fclk = {
.name = "omap3_wkup_32k_fclk",
- .flags = CLOCK_IN_OMAP353X ,
+ .flags = CLOCK_IN_OMAP3XXX ,
.parent = &omap3_32k_fclk,
};
static struct clk omap3_wkup_l4_iclk = {
.name = "omap3_wkup_l4_iclk",
- .flags = CLOCK_IN_OMAP353X,
+ .flags = CLOCK_IN_OMAP3XXX,
.enabled = 1,
.parent = &omap3_sys_clk,
};
static struct clk omap3_gp1_fclk = {
.name = "omap3_gp1_fclk",
- .flags = CLOCK_IN_OMAP353X ,
+ .flags = CLOCK_IN_OMAP3XXX ,
.parent = &omap3_32k_fclk, /*omap3_32k_fclk and omap3_sys_clk*/
};
static struct clk omap3_gp12_fclk = {
.name = "omap3_gp12_fclk",
- .flags = CLOCK_IN_OMAP353X ,
+ .flags = CLOCK_IN_OMAP3XXX ,
.parent = &omap3_32k_fclk, /*SECURE_32K_FCLK -> 32-kHz oscillator */
};
/*gp2-gp9 timer*/
static struct clk omap3_gp2_fclk = {
.name = "omap3_gp2_fclk",
- .flags = CLOCK_IN_OMAP353X ,
+ .flags = CLOCK_IN_OMAP3XXX ,
.parent = &omap3_32k_fclk, /*omap3_32k_fclk and omap3_sys_clk*/
};
static struct clk omap3_gp3_fclk = {
.name = "omap3_gp3_fclk",
- .flags = CLOCK_IN_OMAP353X ,
+ .flags = CLOCK_IN_OMAP3XXX ,
.parent = &omap3_32k_fclk, /*omap3_32k_fclk and omap3_sys_clk*/
};
static struct clk omap3_gp4_fclk = {
.name = "omap3_gp4_fclk",
- .flags = CLOCK_IN_OMAP353X ,
+ .flags = CLOCK_IN_OMAP3XXX ,
.parent = &omap3_32k_fclk, /*omap3_32k_fclk and omap3_sys_clk*/
};
static struct clk omap3_gp5_fclk = {
.name = "omap3_gp5_fclk",
- .flags = CLOCK_IN_OMAP353X ,
+ .flags = CLOCK_IN_OMAP3XXX ,
.parent = &omap3_32k_fclk, /*omap3_32k_fclk and omap3_sys_clk*/
};
static struct clk omap3_gp6_fclk = {
.name = "omap3_gp6_fclk",
- .flags = CLOCK_IN_OMAP353X ,
+ .flags = CLOCK_IN_OMAP3XXX ,
.parent = &omap3_32k_fclk, /*omap3_32k_fclk and omap3_sys_clk*/
};
static struct clk omap3_gp7_fclk = {
.name = "omap3_gp7_fclk",
- .flags = CLOCK_IN_OMAP353X ,
+ .flags = CLOCK_IN_OMAP3XXX ,
.parent = &omap3_32k_fclk, /*omap3_32k_fclk and omap3_sys_clk*/
};
static struct clk omap3_gp8_fclk = {
.name = "omap3_gp8_fclk",
- .flags = CLOCK_IN_OMAP353X ,
+ .flags = CLOCK_IN_OMAP3XXX ,
.parent = &omap3_32k_fclk, /*omap3_32k_fclk and omap3_sys_clk*/
};
static struct clk omap3_gp9_fclk = {
.name = "omap3_gp9_fclk",
- .flags = CLOCK_IN_OMAP353X ,
+ .flags = CLOCK_IN_OMAP3XXX ,
.parent = &omap3_32k_fclk, /*omap3_32k_fclk and omap3_sys_clk*/
};
static struct clk omap3_per_96m_fclk = {
.name = "omap3_per_96m_fclk",
- .flags = CLOCK_IN_OMAP353X ,
+ .flags = CLOCK_IN_OMAP3XXX ,
.parent = &omap3_96m_fclk,
};
static struct clk omap3_per_48m_fclk = {
.name = "omap3_per_48m_fclk",
- .flags = CLOCK_IN_OMAP353X ,
+ .flags = CLOCK_IN_OMAP3XXX ,
.parent = &omap3_48m_fclk,
};
static struct clk omap3_per_l4_iclk = {
.name = "omap3_per_l4_iclk",
- .flags = CLOCK_IN_OMAP353X,
+ .flags = CLOCK_IN_OMAP3XXX,
.enabled = 1,
.parent = &omap3_l4_iclk,
};
/*UART Clocks*/
static struct clk omap3_uart1_fclk = {
.name = "omap3_uart1_fclk",
- .flags = CLOCK_IN_OMAP353X ,
+ .flags = CLOCK_IN_OMAP3XXX ,
.parent = &omap3_core_48m_fclk,
};
static struct clk omap3_uart1_iclk = {
.name = "omap3_uart1_iclk",
- .flags = CLOCK_IN_OMAP353X ,
+ .flags = CLOCK_IN_OMAP3XXX ,
.parent = &omap3_core_l4_iclk,
};
static struct clk omap3_uart2_fclk = {
.name = "omap3_uart2_fclk",
- .flags = CLOCK_IN_OMAP353X ,
+ .flags = CLOCK_IN_OMAP3XXX ,
.parent = &omap3_core_48m_fclk,
};
static struct clk omap3_uart2_iclk = {
.name = "omap3_uart2_iclk",
- .flags = CLOCK_IN_OMAP353X ,
+ .flags = CLOCK_IN_OMAP3XXX ,
.parent = &omap3_core_l4_iclk,
};
static struct clk omap3_uart3_fclk = {
.name = "omap3_uart3_fclk",
- .flags = CLOCK_IN_OMAP353X ,
+ .flags = CLOCK_IN_OMAP3XXX ,
.parent = &omap3_per_48m_fclk,
};
static struct clk omap3_uart3_iclk = {
.name = "omap3_uart3_iclk",
- .flags = CLOCK_IN_OMAP353X ,
+ .flags = CLOCK_IN_OMAP3XXX ,
.parent = &omap3_core_l4_iclk,
};
/*INTC Clock*/
static struct clk omap3_mpu_intc_fclk = {
.name = "omap3_mpu_intc_fclk",
- .flags = CLOCK_IN_OMAP353X ,
+ .flags = CLOCK_IN_OMAP3XXX ,
.divisor = 2,
.parent = &omap3_mpu_clk,
};
static struct clk omap3_mpu_intc_iclk = {
.name = "omap3_mpu_intc_iclk",
- .flags = CLOCK_IN_OMAP353X ,
+ .flags = CLOCK_IN_OMAP3XXX ,
.divisor = 2,
.parent = &omap3_mpu_clk,
};
/*SDMA clock*/
static struct clk omap3_sdma_fclk = {
.name = "omap3_sdma_fclk",
- .flags = CLOCK_IN_OMAP353X ,
+ .flags = CLOCK_IN_OMAP3XXX ,
.parent = &omap3_core_l3_iclk,
};
static struct clk omap3_sdma_iclk = {
.name = "omap3_sdma_iclk",
- .flags = CLOCK_IN_OMAP353X ,
+ .flags = CLOCK_IN_OMAP3XXX ,
.parent = &omap3_core_l4_iclk,
};
/*CLKOUT*/
+static struct clk omap3_sys_clkout1 = {
+ .name = "omap3_sys_clkout1",
+ .flags = CLOCK_IN_OMAP3XXX,
+ .parent = &omap3_osc_sys_clk26, /* same parent as as SYS_CLK */
+};
+
static struct clk omap3_sys_clkout2 = {
.name = "omap3_sys_clkout2",
- .flags = CLOCK_IN_OMAP353X ,
+ .flags = CLOCK_IN_OMAP3XXX ,
.parent = &omap3_core_clk, /*CORE_CLK CM_SYS_CLK CM_96M_FCLK 54 MHz clock*/
};
/*MMC Clock*/
static struct clk omap3_mmc1_fclk = {
.name = "omap3_mmc1_fclk",
- .flags = CLOCK_IN_OMAP353X ,
+ .flags = CLOCK_IN_OMAP3XXX ,
.parent = &omap3_per_96m_fclk,
};
static struct clk omap3_mmc1_iclk = {
.name = "omap3_mmc1_iclk",
- .flags = CLOCK_IN_OMAP353X ,
+ .flags = CLOCK_IN_OMAP3XXX ,
.parent = &omap3_per_l4_iclk,
};
static struct clk omap3_mmc2_fclk = {
.name = "omap3_mmc2_fclk",
- .flags = CLOCK_IN_OMAP353X ,
+ .flags = CLOCK_IN_OMAP3XXX ,
.parent = &omap3_per_96m_fclk,
};
static struct clk omap3_mmc2_iclk = {
.name = "omap3_mmc2_iclk",
- .flags = CLOCK_IN_OMAP353X ,
+ .flags = CLOCK_IN_OMAP3XXX ,
.parent = &omap3_per_l4_iclk,
};
static struct clk omap3_mmc3_fclk = {
.name = "omap3_mmc3_fclk",
- .flags = CLOCK_IN_OMAP353X ,
+ .flags = CLOCK_IN_OMAP3XXX ,
.parent = &omap3_per_96m_fclk,
};
static struct clk omap3_mmc3_iclk = {
.name = "omap3_mmc3_iclk",
- .flags = CLOCK_IN_OMAP353X ,
+ .flags = CLOCK_IN_OMAP3XXX ,
.parent = &omap3_per_l4_iclk,
};
/*I2C Clocls*/
static struct clk omap3_i2c1_fclk = {
.name = "omap3_i2c1_fclk",
- .flags = CLOCK_IN_OMAP353X ,
+ .flags = CLOCK_IN_OMAP3XXX ,
.parent = &omap3_per_96m_fclk,
};
static struct clk omap3_i2c1_iclk = {
.name = "omap3_i2c1_iclk",
- .flags = CLOCK_IN_OMAP353X ,
+ .flags = CLOCK_IN_OMAP3XXX ,
.parent = &omap3_core_l4_iclk,
};
static struct clk omap3_i2c2_fclk = {
.name = "omap3_i2c2_fclk",
- .flags = CLOCK_IN_OMAP353X ,
+ .flags = CLOCK_IN_OMAP3XXX ,
.parent = &omap3_per_96m_fclk,
};
static struct clk omap3_i2c2_iclk = {
.name = "omap3_i2c2_iclk",
- .flags = CLOCK_IN_OMAP353X ,
+ .flags = CLOCK_IN_OMAP3XXX ,
.parent = &omap3_core_l4_iclk,
};
static struct clk omap3_i2c3_fclk = {
.name = "omap3_i2c3_fclk",
- .flags = CLOCK_IN_OMAP353X ,
+ .flags = CLOCK_IN_OMAP3XXX ,
.parent = &omap3_per_96m_fclk,
};
static struct clk omap3_i2c3_iclk = {
.name = "omap3_i2c3_iclk",
- .flags = CLOCK_IN_OMAP353X ,
+ .flags = CLOCK_IN_OMAP3XXX ,
.parent = &omap3_core_l4_iclk,
};
/* OMAP 3*/
&omap3_sys_32k,
- &omap3_sys_xtalin,
+ &omap3_osc_sys_clk12,
+ &omap3_osc_sys_clk13,
+ &omap3_osc_sys_clk168,
+ &omap3_osc_sys_clk192,
+ &omap3_osc_sys_clk26,
+ &omap3_osc_sys_clk384,
&omap3_sys_altclk,
&omap3_sys_clk,
&omap3_32k_fclk,
&omap3_mpu_intc_iclk,
&omap3_sdma_fclk,
&omap3_sdma_iclk,
+ &omap3_sys_clkout1,
&omap3_sys_clkout2,
&omap3_mmc1_fclk,
&omap3_mmc1_iclk,
else if (cpu_is_omap3430(mpu))
flag = CLOCK_IN_OMAP243X;
else if (cpu_is_omap3530(mpu))
- flag = CLOCK_IN_OMAP353X;
+ flag = CLOCK_IN_OMAP3XXX;
else
return;
projects / qemu / commitdiff