}
enter_debug_mode:
env->hflags |= MIPS_HFLAG_DM;
+ env->hflags |= MIPS_HFLAG_64;
env->hflags &= ~MIPS_HFLAG_UM;
/* EJTAG probe trap enable is not implemented... */
if (!(env->CP0_Status & (1 << CP0St_EXL)))
env->CP0_ErrorEPC = env->PC;
}
env->CP0_Status |= (1 << CP0St_ERL) | (1 << CP0St_BEV);
+ env->hflags |= MIPS_HFLAG_64;
env->hflags &= ~MIPS_HFLAG_UM;
if (!(env->CP0_Status & (1 << CP0St_EXL)))
env->CP0_Cause &= ~(1 << CP0Ca_BD);
env->CP0_Cause &= ~(1 << CP0Ca_BD);
}
env->CP0_Status |= (1 << CP0St_EXL);
+ env->hflags |= MIPS_HFLAG_64;
env->hflags &= ~MIPS_HFLAG_UM;
}
env->hflags &= ~MIPS_HFLAG_BMASK;
!(env->hflags & MIPS_HFLAG_DM) &&
(val & (1 << CP0St_UM)))
env->hflags |= MIPS_HFLAG_UM;
+#ifdef TARGET_MIPS64
+ if ((env->hflags & MIPS_HFLAG_UM) &&
+ !(val & (1 << CP0St_PX)) &&
+ !(val & (1 << CP0St_UX)))
+ env->hflags &= ~MIPS_HFLAG_64;
+#endif
env->CP0_Status = (env->CP0_Status & ~mask) | val;
if (loglevel & CPU_LOG_EXEC)
CALL_FROM_TB2(do_mtc0_status_debug, old, val);
!(env->hflags & MIPS_HFLAG_DM) &&
(env->CP0_Status & (1 << CP0St_UM)))
env->hflags |= MIPS_HFLAG_UM;
+#ifdef TARGET_MIPS64
+ if ((env->hflags & MIPS_HFLAG_UM) &&
+ !(env->CP0_Status & (1 << CP0St_PX)) &&
+ !(env->CP0_Status & (1 << CP0St_UX)))
+ env->hflags &= ~MIPS_HFLAG_64;
+#endif
if (loglevel & CPU_LOG_EXEC)
CALL_FROM_TB0(debug_post_eret);
env->CP0_LLAddr = 1;
!(env->hflags & MIPS_HFLAG_DM) &&
(env->CP0_Status & (1 << CP0St_UM)))
env->hflags |= MIPS_HFLAG_UM;
+#ifdef TARGET_MIPS64
+ if ((env->hflags & MIPS_HFLAG_UM) &&
+ !(env->CP0_Status & (1 << CP0St_PX)) &&
+ !(env->CP0_Status & (1 << CP0St_UX)))
+ env->hflags &= ~MIPS_HFLAG_64;
+#endif
if (loglevel & CPU_LOG_EXEC)
CALL_FROM_TB0(debug_post_eret);
env->CP0_LLAddr = 1;
OP_ST_TABLE(dr);
OP_LD_TABLE(ld);
OP_ST_TABLE(cd);
+OP_LD_TABLE(wu);
#endif
OP_LD_TABLE(w);
-OP_LD_TABLE(wu);
OP_LD_TABLE(wl);
OP_LD_TABLE(wr);
OP_ST_TABLE(w);
*/
switch (opc) {
#ifdef TARGET_MIPS64
+ case OPC_LWU:
+ op_ldst(lwu);
+ GEN_STORE_TN_REG(rt, T0);
+ opn = "lwu";
+ break;
case OPC_LD:
op_ldst(ld);
GEN_STORE_TN_REG(rt, T0);
GEN_STORE_TN_REG(rt, T0);
opn = "lw";
break;
- case OPC_LWU:
- op_ldst(lwu);
- GEN_STORE_TN_REG(rt, T0);
- opn = "lwu";
- break;
case OPC_SW:
GEN_LOAD_REG_TN(T1, rt);
op_ldst(sw);
case OPC_DSRL ... OPC_DSRA:
case OPC_DSLL32:
case OPC_DSRL32 ... OPC_DSRA32:
+ if (!(ctx->hflags & MIPS_HFLAG_64))
+ generate_exception(ctx, EXCP_RI);
gen_arith_imm(ctx, op1, rd, rt, sa);
break;
case OPC_DSLLV:
case OPC_DSRLV ... OPC_DSRAV:
case OPC_DADD ... OPC_DSUBU:
+ if (!(ctx->hflags & MIPS_HFLAG_64))
+ generate_exception(ctx, EXCP_RI);
gen_arith(ctx, op1, rd, rs, rt);
break;
case OPC_DMULT ... OPC_DDIVU:
+ if (!(ctx->hflags & MIPS_HFLAG_64))
+ generate_exception(ctx, EXCP_RI);
gen_muldiv(ctx, op1, rs, rt);
break;
#endif
break;
#ifdef TARGET_MIPS64
case OPC_DCLZ ... OPC_DCLO:
+ if (!(ctx->hflags & MIPS_HFLAG_64))
+ generate_exception(ctx, EXCP_RI);
gen_cl(ctx, op1, rd, rs);
break;
#endif
#ifdef TARGET_MIPS64
case OPC_DEXTM ... OPC_DEXT:
case OPC_DINSM ... OPC_DINS:
+ if (!(ctx->hflags & MIPS_HFLAG_64))
+ generate_exception(ctx, EXCP_RI);
gen_bitops(ctx, op1, rt, rs, sa, rd);
break;
case OPC_DBSHFL:
+ if (!(ctx->hflags & MIPS_HFLAG_64))
+ generate_exception(ctx, EXCP_RI);
op2 = MASK_DBSHFL(ctx->opcode);
switch (op2) {
case OPC_DSBH:
case OPC_LD:
case OPC_SCD:
case OPC_SD:
+ if (!(ctx->hflags & MIPS_HFLAG_64))
+ generate_exception(ctx, EXCP_RI);
gen_ldst(ctx, op, rt, rs, imm);
break;
case OPC_DADDI ... OPC_DADDIU:
+ if (!(ctx->hflags & MIPS_HFLAG_64))
+ generate_exception(ctx, EXCP_RI);
gen_arith_imm(ctx, op, rt, rs, imm);
break;
#endif
/* If the exception was raised from a delay slot,
* come back to the jump. */
env->CP0_ErrorEPC = env->PC - 4;
- env->hflags &= ~MIPS_HFLAG_BMASK;
} else {
env->CP0_ErrorEPC = env->PC;
}
+#ifdef TARGET_MIPS64
+ env->hflags = MIPS_HFLAG_64;
+#else
env->hflags = 0;
+#endif
env->PC = (int32_t)0xBFC00000;
env->CP0_Wired = 0;
/* SMP not implemented */