microblaze: Trap on divizions by zero.

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>

diff --git a/target-microblaze/op_helper.c b/target-microblaze/op_helper.c
index f86b1c7..134d243 100644 (file)
--- a/target-microblaze/op_helper.c
+++ b/target-microblaze/op_helper.c
@@ -167,7 +167,12 @@ static inline int div_prepare(uint32_t a, uint32_t b)
 {
     if (b == 0) {
         env->sregs[SR_MSR] |= MSR_DZ;
-        /* FIXME: Raise the div by zero exception.  */
+
+        if ((env->sregs[SR_MSR] & MSR_EE)
+            && !(env->pvr.regs[2] & PVR2_DIV_ZERO_EXC_MASK)) {
+            env->sregs[SR_ESR] = ESR_EC_DIVZERO;
+            helper_raise_exception(EXCP_HW_EXCP);
+        }
         return 0;
     }
     env->sregs[SR_MSR] &= ~MSR_DZ;

diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c
index acf3f8d..4fbe86a 100644 (file)
--- a/target-microblaze/translate.c
+++ b/target-microblaze/translate.c
@@ -616,7 +616,6 @@ static void dec_div(DisasContext *dc)
         t_gen_raise_exception(dc, EXCP_HW_EXCP);
     }
 
-    /* FIXME: support div by zero exceptions.  */
     if (u)
         gen_helper_divu(cpu_R[dc->rd], *(dec_alu_op_b(dc)), cpu_R[dc->ra]);
     else