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Fix CLO calculation for MIPS64. And a small code cleanup.
author
ths
<ths@c046a42c-6fe2-441c-8c8c-71466251a162>
Tue, 23 Oct 2007 23:22:03 +0000
(23:22 +0000)
committer
ths
<ths@c046a42c-6fe2-441c-8c8c-71466251a162>
Tue, 23 Oct 2007 23:22:03 +0000
(23:22 +0000)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3428
c046a42c
-6fe2-441c-8c8c-
71466251a162
target-mips/op.c
patch
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diff --git
a/target-mips/op.c
b/target-mips/op.c
index
3aefec2
..
ca367d7
100644
(file)
--- a/
target-mips/op.c
+++ b/
target-mips/op.c
@@
-543,9
+543,9
@@
void op_clo (void)
T0 = 32;
} else {
for (n = 0; n < 32; n++) {
- if (!(T0 & (1 << 31)))
+ if (!(((int32_t)T0) & (1 << 31)))
break;
- T0 = T0 << 1;
+ T0 <<= 1;
}
T0 = n;
}
@@
-562,7
+562,7
@@
void op_clz (void)
for (n = 0; n < 32; n++) {
if (T0 & (1 << 31))
break;
- T0 = T0 << 1;
+ T0 <<= 1;
}
T0 = n;
}
@@
-747,7
+747,7
@@
void op_dclo (void)
for (n = 0; n < 64; n++) {
if (!(T0 & (1ULL << 63)))
break;
- T0 = T0 << 1;
+ T0 <<= 1;
}
T0 = n;
}
@@
-764,7
+764,7
@@
void op_dclz (void)
for (n = 0; n < 64; n++) {
if (T0 & (1ULL << 63))
break;
- T0 = T0 << 1;
+ T0 <<= 1;
}
T0 = n;
}