alpha: fix lit sign

according to the alpha arch reference, the literal field of an operate
instruction is unsigned:

If bit <12> of the instruction is 1, an 8-bit zero-extended literal
constant is formed by bits
<20:13> of the instruction. The l teral is interpreted as a positive
integer bet ween 0 and 255
and is zero-extended to 64 bits.

This patch fixes the mis-interpretation of the literal field.

(Tristan Gingold)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5211 c046a42c-6fe2-441c-8c8c-71466251a162

diff --git a/target-alpha/translate.c b/target-alpha/translate.c
index 847646f..e6dc473 100644 (file)
--- a/target-alpha/translate.c
+++ b/target-alpha/translate.c
@@ -351,7 +351,7 @@ static always_inline void gen_fbcond (DisasContext *ctx,
 
 static always_inline void gen_arith2 (DisasContext *ctx,
                                       void (*gen_arith_op)(void),
-                                      int rb, int rc, int islit, int8_t lit)
+                                      int rb, int rc, int islit, uint8_t lit)
 {
     if (islit)
         tcg_gen_movi_i64(cpu_T[0], lit);
@@ -367,7 +367,7 @@ static always_inline void gen_arith2 (DisasContext *ctx,
 static always_inline void gen_arith3 (DisasContext *ctx,
                                       void (*gen_arith_op)(void),
                                       int ra, int rb, int rc,
-                                      int islit, int8_t lit)
+                                      int islit, uint8_t lit)
 {
     if (ra != 31)
         tcg_gen_mov_i64(cpu_T[0], cpu_ir[ra]);
@@ -387,7 +387,7 @@ static always_inline void gen_arith3 (DisasContext *ctx,
 static always_inline void gen_cmov (DisasContext *ctx,
                                     void (*gen_test_op)(void),
                                     int ra, int rb, int rc,
-                                    int islit, int8_t lit)
+                                    int islit, uint8_t lit)
 {
     if (ra != 31)
         tcg_gen_mov_i64(cpu_T[0], cpu_ir[ra]);