Fix configuration 2 register (esp_2_cfg2.diff):

According to http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR53C9X.txt,
"Any bit pattern written to this register may be read back and should be identical"

Signed-off-by: Herve Poussineau <hpoussin@reactos.org>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5812 c046a42c-6fe2-441c-8c8c-71466251a162

diff --git a/hw/esp.c b/hw/esp.c
index 292875b..33f4432 100644 (file)
--- a/hw/esp.c
+++ b/hw/esp.c
@@ -144,8 +144,6 @@ struct ESPState {
 
 #define CFG1_RESREPT 0x40
 
-#define CFG2_MASK 0x15
-
 #define TCHI_FAS100A 0x4
 
 static void esp_raise_irq(ESPState *s)
@@ -552,10 +550,7 @@ static void esp_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
         break;
     case ESP_WCCF ... ESP_WTEST:
         break;
-    case ESP_CFG2:
-        s->rregs[saddr] = val & CFG2_MASK;
-        break;
-    case ESP_CFG3 ... ESP_RES4:
+    case ESP_CFG2 ... ESP_RES4:
         s->rregs[saddr] = val;
         break;
     default: