#include "cpu-defs.h"
-#define EXCP_UDEF 1 /* undefined instruction */
-#define EXCP_SWI 2 /* software interrupt */
+#define EXCP_UDEF 1 /* undefined instruction */
+#define EXCP_SWI 2 /* software interrupt */
+#define EXCP_PREFETCH_ABORT 3
+#define EXCP_DATA_ABORT 4
typedef struct CPUARMState {
uint32_t regs[16];
int thumb; /* 0 = arm mode, 1 = thumb mode */
+ /* coprocessor 15 (MMU) status */
+ uint32_t cp15_6;
+
/* exception/interrupt handling */
jmp_buf jmp_env;
int exception_index;
static inline void regs_to_env(void)
{
}
+
+int cpu_arm_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
+ int is_user, int is_softmmu);
gen_op_movl_T0_psr();
gen_movl_reg_T0(s, rd);
}
+ break;
case 0x1:
if (op1 == 1) {
/* branch/exchange thumb (bx). */
{
return addr;
}
+
+#if defined(CONFIG_USER_ONLY)
+
+int cpu_arm_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
+ int is_user, int is_softmmu)
+{
+ env->cp15_6 = address;
+ if (rw == 2) {
+ env->exception_index = EXCP_PREFETCH_ABORT;
+ } else {
+ env->exception_index = EXCP_DATA_ABORT;
+ }
+ return 1;
+}
+
+#else
+
+#error not implemented
+
+#endif