Convert ldfsr and stfsr to TCG
authorblueswir1 <blueswir1@c046a42c-6fe2-441c-8c8c-71466251a162>
Sat, 15 Mar 2008 18:11:06 +0000 (18:11 +0000)
committerblueswir1 <blueswir1@c046a42c-6fe2-441c-8c8c-71466251a162>
Sat, 15 Mar 2008 18:11:06 +0000 (18:11 +0000)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4067 c046a42c-6fe2-441c-8c8c-71466251a162

target-sparc/helper.h
target-sparc/op.c
target-sparc/op_helper.c
target-sparc/translate.c

index 88b56e2..365f482 100644 (file)
@@ -34,6 +34,7 @@ uint64_t TCG_HELPER_PROTO helper_ld_asi(target_ulong addr, int asi,
 void TCG_HELPER_PROTO helper_st_asi(target_ulong addr, uint64_t val, int asi,
                                     int size);
 void TCG_HELPER_PROTO helper_ldfsr(void);
+void TCG_HELPER_PROTO helper_stfsr(void);
 void TCG_HELPER_PROTO helper_check_ieee_exceptions(void);
 void TCG_HELPER_PROTO helper_clear_float_exceptions(void);
 void TCG_HELPER_PROTO helper_fabss(void);
index 79b669b..921699e 100644 (file)
@@ -285,16 +285,6 @@ void OPPROTO op_sdiv_T1_T0(void)
 #endif
 #endif
 
-void OPPROTO op_ldfsr(void)
-{
-    PUT_FSR32(env, *((uint32_t *) &FT0));
-}
-
-void OPPROTO op_stfsr(void)
-{
-    *((uint32_t *) &FT0) = GET_FSR32(env);
-}
-
 #ifndef TARGET_SPARC64
 /* XXX: use another pointer for %iN registers to avoid slow wrapping
    handling ? */
index 76af753..1172b5a 100644 (file)
@@ -1590,6 +1590,8 @@ uint64_t helper_pack64(target_ulong high, target_ulong low)
 void helper_ldfsr(void)
 {
     int rnd_mode;
+
+    PUT_FSR32(env, *((uint32_t *) &FT0));
     switch (env->fsr & FSR_RD_MASK) {
     case FSR_RD_NEAREST:
         rnd_mode = float_round_nearest_even;
@@ -1608,7 +1610,12 @@ void helper_ldfsr(void)
     set_float_rounding_mode(rnd_mode, &env->fp_status);
 }
 
-void helper_debug()
+void helper_stfsr(void)
+{
+    *((uint32_t *) &FT0) = GET_FSR32(env);
+}
+
+void helper_debug(void)
 {
     env->exception_index = EXCP_DEBUG;
     cpu_loop_exit();
index 05f23de..10a3a28 100644 (file)
@@ -4259,7 +4259,6 @@ static void disas_sparc_insn(DisasContext * dc)
                 case 0x21:      /* load fsr */
                     gen_op_check_align_T0_3();
                     gen_op_ldst(ldf);
-                    gen_op_ldfsr();
                     tcg_gen_helper_0_0(helper_ldfsr);
                     break;
                 case 0x22:      /* load quad fpreg */
@@ -4415,7 +4414,7 @@ static void disas_sparc_insn(DisasContext * dc)
 #ifdef CONFIG_USER_ONLY
                     gen_op_check_align_T0_3();
 #endif
-                    gen_op_stfsr();
+                    tcg_gen_helper_0_0(helper_stfsr);
                     gen_op_ldst(stf);
                     break;
                 case 0x26: