#include "console.h"
#include "cpu-all.h"
-#define VERBOSE 1
-#define TRACEW(regname, value) fprintf(stderr, "%s: %s = 0x%02x\n", __FUNCTION__, regname, value);
+//#define VERBOSE 1
-//extern CPUState *cpu_single_env;
+#ifdef VERBOSE
+#define TRACE(fmt, ...) fprintf(stderr, "%s: " fmt "\n", __FUNCTION__, __##VA_ARGS__)
+#else
+#define TRACE(...)
+#endif
struct twl4030_i2c_s {
i2c_slave i2c;
{
struct twl4030_i2c_s *s = (struct twl4030_i2c_s *) opaque;
+ TRACE("addr=0x%02x", addr);
switch (addr) {
case 0x00: /* VENDOR_ID_LO */
case 0x01: /* VENDOR_ID_HI */
case 0xff: /* PHY_CLK_CTRL */
return s->reg_data[0xfe] & 0x1;
default:
-#ifdef VERBOSE
- fprintf(stderr, "%s: unknown register %02x pc %x\n",
+ fprintf(stderr, "%s: unknown register 0x%02x pc %x\n",
__FUNCTION__, addr, cpu_single_env->regs[15]);
-#endif
break;
}
return 0;
{
struct twl4030_i2c_s *s = (struct twl4030_i2c_s *) opaque;
+ TRACE("addr=0x%02x, value=0x%02x", addr, value);
switch (addr) {
case 0x04: /* IFC_CTRL */
s->reg_data[0x04] = value & 0x80;
s->reg_data[addr] = value & 0x7;
break;
default:
-#ifdef VERBOSE
- fprintf(stderr, "%s: unknown register %02x pc %x\n",
- __FUNCTION__, addr,cpu_single_env->regs[15]);
-#endif
+ fprintf(stderr, "%s: unknown register 0x%02x pc %x\n",
+ __FUNCTION__, addr, cpu_single_env->regs[15]);
break;
}
}
{
struct twl4030_i2c_s *s = (struct twl4030_i2c_s *) opaque;
+ TRACE("addr=0x%02x", addr);
switch (addr) {
+ /* AUDIO_VOICE region */
+ case 0x01: /* CODEC_MODE */
+ case 0x02: /* OPTION */
+ case 0x04: /* MICBIAS_CTL */
+ case 0x05: /* ANAMICL */
+ case 0x06: /* ANAMICR */
+ case 0x07: /* AVADC_CTL */
+ case 0x08: /* ADCMICSEL */
+ case 0x09: /* DIGMIXING */
+ case 0x0a: /* ATXL1PGA */
+ case 0x0b: /* ATXR1PGA */
+ case 0x0c: /* AVTXL2PGA */
+ case 0x0d: /* AVTXR2PGA */
+ case 0x0e: /* AUDIO_IF */
+ case 0x0f: /* VOICE_IF */
+ case 0x10: /* ARXR1PGA */
+ case 0x11: /* ARXL1PGA */
+ case 0x12: /* ARXR2PGA */
+ case 0x13: /* ARXL2PGA */
+ case 0x14: /* VRXPGA */
+ case 0x15: /* VSTPGA */
+ case 0x16: /* VRX2ARXPGA */
+ case 0x17: /* AVDAC_CTL */
+ case 0x18: /* ARX2VTXPGA */
+ case 0x19: /* ARXL1_APGA_CTL */
+ case 0x1a: /* ARXR1_APGA_CTL */
+ case 0x1b: /* ARXL2_APGA_CTL */
+ case 0x1c: /* ARXR2_APGA_CTL */
+ case 0x1d: /* ATX2ARXPGA */
+ case 0x1e: /* BT_IF */
+ case 0x1f: /* BTPGA */
+ case 0x20: /* BTSTPGA */
+ case 0x21: /* EAR_CTL */
+ case 0x22: /* HS_SEL */
+ case 0x23: /* HS_GAIN_SET */
+ case 0x24: /* HS_POPN_SET */
+ case 0x25: /* PREDL_CTL */
+ case 0x26: /* PREDR_CTL */
+ case 0x27: /* PRECKL_CTL */
+ case 0x28: /* PRECKR_CTL */
+ case 0x29: /* HFL_CTL */
+ case 0x2a: /* HFR_CTL */
+ case 0x2b: /* ALC_CTL */
+ case 0x2c: /* ALC_SET1 */
+ case 0x2d: /* ALC_SET2 */
+ case 0x2e: /* BOOST_CTL */
+ case 0x2f: /* SOFTVOL_CTL */
+ case 0x30: /* DTMF_FREQSEL */
+ case 0x31: /* DTMF_TONEXT1H */
+ case 0x32: /* DTMF_TONEXT1L */
+ case 0x33: /* DTMF_TONEXT2H */
+ case 0x34: /* DTMF_TONEXT2L */
+ case 0x35: /* DTMF_TONOFF */
+ case 0x36: /* DTMF_WANONOFF */
+ case 0x37: /* CODEC_RX_SCRAMBLE_H */
+ case 0x38: /* CODEC_RX_SCRAMBLE_M */
+ case 0x39: /* CODEC_RX_SCRAMBLE_L */
+ case 0x3a: /* APLL_CTL */
+ case 0x3b: /* DTMF_CTL */
+ case 0x3c: /* DTMF_PGA_CTL2 */
+ case 0x3d: /* DTMF_PGA_CTL1 */
+ case 0x3e: /* MISC_SET_1 */
+ case 0x3f: /* PCMBTMUX */
+ case 0x43: /* RX_PATH_SEL */
+ case 0x44: /* VDL_APGA_CTL */
+ case 0x45: /* VIBRA_CTL */
+ case 0x46: /* VIBRA_SET */
+ case 0x48: /* ANAMIC_GAIN */
+ case 0x49: /* MISC_SET_2 */
+ /* Test region */
+ case 0x4c: /* AUDIO_TEST_CTL */
+ case 0x4d: /* INT_TEST_CTL */
+ case 0x4e: /* DAC_ADC_TEST_CTL */
+ case 0x4f: /* RXTX_TRIM_IB */
+ case 0x50: /* CLD_CONTROL */
+ case 0x51: /* CLD_MODE_TIMING */
+ case 0x52: /* CLD_TRIM_RAMP */
+ case 0x53: /* CLD_TESTV_CTL */
+ case 0x54: /* APLL_TEST_CTL */
+ case 0x55: /* APLL_TEST_DIV */
+ case 0x56: /* APLL_TEST_CTL2 */
+ case 0x57: /* APLL_TEST_CUR */
+ case 0x58: /* DIGIMIC_BIAS1_CTL */
+ case 0x59: /* DIGIMIC_BIAS2_CTL */
+ case 0x5a: /* RX_OFFSET_VOICE */
+ case 0x5b: /* RX_OFFSET_AL1 */
+ case 0x5c: /* RX_OFFSET_AR1 */
+ case 0x5d: /* RX_OFFSET_AL2 */
+ case 0x5e: /* RX_OFFSET_AR2 */
+ case 0x5f: /* OFFSET1 */
+ case 0x60: /* OFFSET2 */
+ /* PIH region */
+ case 0x81: /* PIH_ISR_P1 */
+ case 0x82: /* PIH_ISR_P2 */
+ case 0x83: /* PIH_SIR */
+ /* INTBR region */
+ case 0x85: /* IDCODE_7_0 */
+ case 0x86: /* IDCODE_15_8 */
+ case 0x87: /* IDCODE_23_16 */
+ case 0x88: /* IDCODE_31_24 */
+ case 0x89: /* DIEID_7_0 */
+ case 0x8a: /* DIEID_15_8 */
+ case 0x8b: /* DIEID_23_16 */
+ case 0x8c: /* DIEID_31_24 */
+ case 0x8d: /* DIEID_39_32 */
+ case 0x8e: /* DIEID_47_40 */
+ case 0x8f: /* DIEID_55_48 */
+ case 0x90: /* DIEID_63_56 */
+ case 0x91: /* GPBR1 */
+ case 0x92: /* PMBR1 */
+ case 0x93: /* PMBR2 */
+ case 0x94: /* GPPUPDCTR1 */
+ case 0x95: /* GPPUPDCTR2 */
+ case 0x96: /* GPPUPDCTR3 */
+ case 0x97: /* UNLOCK_TEST_REG */
+ /* GPIO region */
case 0x98: /* GPIO_DATAIN1 */
case 0x99: /* GPIO_DATAIN2 */
case 0x9a: /* GPIO_DATAIN3 */
case 0x9b: /* GPIO_DATADIR1 */
case 0x9c: /* GPIO_DATADIR2 */
case 0x9d: /* GPIO_DATADIR3 */
+ case 0x9e: /* GPIO_DATAOUT1 */
+ case 0x9f: /* GPIO_DATAOUT2 */
+ case 0xa0: /* GPIO_DATAOUT3 */
+ case 0xa1: /* GPIO_CLEARGPIODATAOUT1 */
+ case 0xa2: /* GPIO_CLEARGPIODATAOUT2 */
+ case 0xa3: /* GPIO_CLEARGPIODATAOUT3 */
+ case 0xa4: /* GPIO_SETGPIODATAOUT1 */
+ case 0xa5: /* GPIO_SETGPIODATAOUT2 */
+ case 0xa6: /* GPIO_SETGPIODATAOUT3 */
+ case 0xa7: /* GPIO_DEBEN1 */
+ case 0xa8: /* GPIO_DEBEN2 */
+ case 0xa9: /* GPIO_DEBEN3 */
+ case 0xaa: /* GPIO_CTRL */
+ case 0xab: /* GPIO_PUPDCTR1 */
+ case 0xac: /* GPIO_PUPDCTR2 */
+ case 0xad: /* GPIO_PUPDCTR3 */
+ case 0xae: /* GPIO_PUPDCTR4 */
+ case 0xaf: /* GPIO_PUPDCTR5 */
+ case 0xb0: /* GPIO_TEST */
case 0xb1: /* GPIO_ISR1A */
case 0xb2: /* GPIO_ISR2A */
case 0xb3: /* GPIO_ISR3A */
+ case 0xb4: /* GPIO_IMR1A */
+ case 0xb5: /* GPIO_IMR2A */
+ case 0xb6: /* GPIO_IMR3A */
+ case 0xb7: /* GPIO_ISR1B */
+ case 0xb8: /* GPIO_ISR2B */
+ case 0xb9: /* GPIO_ISR3B */
+ case 0xba: /* GPIO_IMR1B */
+ case 0xbb: /* GPIO_IMR2B */
+ case 0xbc: /* GPIO_IMR3B */
+ case 0xbd: /* GPIO_SIR1 */
+ case 0xbe: /* GPIO_SIR2 */
+ case 0xbf: /* GPIO_SIR3 */
case 0xc0: /* GPIO_EDR1 */
case 0xc1: /* GPIO_EDR2 */
case 0xc2: /* GPIO_EDR3 */
case 0xc3: /* GPIO_EDR4 */
case 0xc4: /* GPIO_EDR5 */
+ case 0xc5: /* GPIO_SIH_CTRL */
return s->reg_data[addr];
default:
-#ifdef VERBOSE
- fprintf(stderr, "%s: unknown register %02x pc %x\n",
- __FUNCTION__, addr,cpu_single_env->regs[15]);
-#endif
+ fprintf(stderr, "%s: unknown register 0x%02x pc %x\n",
+ __FUNCTION__, addr, cpu_single_env->regs[15]);
break;
}
return 0;
{
struct twl4030_i2c_s *s = (struct twl4030_i2c_s *) opaque;
+ TRACE("addr=0x%02x, value=0x%02x", addr, value);
switch (addr) {
+ /* AUDIO_VOICE region */
+ case 0x01: /* CODEC_MODE */
+ case 0x02: /* OPTION */
+ case 0x04: /* MICBIAS_CTL */
+ case 0x05: /* ANAMICL */
+ case 0x06: /* ANAMICR */
+ case 0x07: /* AVADC_CTL */
+ case 0x08: /* ADCMICSEL */
+ case 0x09: /* DIGMIXING */
+ case 0x0a: /* ATXL1PGA */
+ case 0x0b: /* ATXR1PGA */
+ case 0x0c: /* AVTXL2PGA */
+ case 0x0d: /* AVTXR2PGA */
+ case 0x0e: /* AUDIO_IF */
+ case 0x0f: /* VOICE_IF */
+ case 0x10: /* ARXR1PGA */
+ case 0x11: /* ARXL1PGA */
+ case 0x12: /* ARXR2PGA */
+ case 0x13: /* ARXL2PGA */
+ case 0x14: /* VRXPGA */
+ case 0x15: /* VSTPGA */
+ case 0x16: /* VRX2ARXPGA */
+ case 0x17: /* AVDAC_CTL */
+ case 0x18: /* ARX2VTXPGA */
+ case 0x19: /* ARXL1_APGA_CTL */
+ case 0x1a: /* ARXR1_APGA_CTL */
+ case 0x1b: /* ARXL2_APGA_CTL */
+ case 0x1c: /* ARXR2_APGA_CTL */
+ case 0x1d: /* ATX2ARXPGA */
+ case 0x1e: /* BT_IF */
+ case 0x1f: /* BTPGA */
+ case 0x20: /* BTSTPGA */
+ case 0x21: /* EAR_CTL */
+ case 0x22: /* HS_SEL */
+ case 0x23: /* HS_GAIN_SET */
+ case 0x24: /* HS_POPN_SET */
+ case 0x25: /* PREDL_CTL */
+ case 0x26: /* PREDR_CTL */
+ case 0x27: /* PRECKL_CTL */
+ case 0x28: /* PRECKR_CTL */
+ case 0x29: /* HFL_CTL */
+ case 0x2a: /* HFR_CTL */
+ case 0x2b: /* ALC_CTL */
+ case 0x2c: /* ALC_SET1 */
+ case 0x2d: /* ALC_SET2 */
+ case 0x2e: /* BOOST_CTL */
+ case 0x2f: /* SOFTVOL_CTL */
+ case 0x30: /* DTMF_FREQSEL */
+ case 0x31: /* DTMF_TONEXT1H */
+ case 0x32: /* DTMF_TONEXT1L */
+ case 0x33: /* DTMF_TONEXT2H */
+ case 0x34: /* DTMF_TONEXT2L */
+ case 0x35: /* DTMF_TONOFF */
+ case 0x36: /* DTMF_WANONOFF */
+ case 0x37: /* CODEC_RX_SCRAMBLE_H */
+ case 0x38: /* CODEC_RX_SCRAMBLE_M */
+ case 0x39: /* CODEC_RX_SCRAMBLE_L */
+ case 0x3a: /* APLL_CTL */
+ case 0x3b: /* DTMF_CTL */
+ case 0x3c: /* DTMF_PGA_CTL2 */
+ case 0x3d: /* DTMF_PGA_CTL1 */
+ case 0x3e: /* MISC_SET_1 */
+ case 0x3f: /* PCMBTMUX */
+ case 0x43: /* RX_PATH_SEL */
+ case 0x44: /* VDL_APGA_CTL */
+ case 0x45: /* VIBRA_CTL */
+ case 0x46: /* VIBRA_SET */
+ case 0x48: /* ANAMIC_GAIN */
+ case 0x49: /* MISC_SET_2 */
+ s->reg_data[addr] = value;
+ break;
+ /* Test region */
+ case 0x4c: /* AUDIO_TEST_CTL */
+ case 0x4d: /* INT_TEST_CTL */
+ case 0x4e: /* DAC_ADC_TEST_CTL */
+ case 0x4f: /* RXTX_TRIM_IB */
+ case 0x50: /* CLD_CONTROL */
+ case 0x51: /* CLD_MODE_TIMING */
+ case 0x52: /* CLD_TRIM_RAMP */
+ case 0x53: /* CLD_TESTV_CTL */
+ case 0x54: /* APLL_TEST_CTL */
+ case 0x55: /* APLL_TEST_DIV */
+ case 0x56: /* APLL_TEST_CTL2 */
+ case 0x57: /* APLL_TEST_CUR */
+ case 0x58: /* DIGIMIC_BIAS1_CTL */
+ case 0x59: /* DIGIMIC_BIAS2_CTL */
+ s->reg_data[addr] = value;
+ break;
+ case 0x5a: /* RX_OFFSET_VOICE */
+ case 0x5b: /* RX_OFFSET_AL1 */
+ case 0x5c: /* RX_OFFSET_AR1 */
+ case 0x5d: /* RX_OFFSET_AL2 */
+ case 0x5e: /* RX_OFFSET_AR2 */
+ case 0x5f: /* OFFSET1 */
+ case 0x60: /* OFFSET2 */
+ /* read-only, ignore */
+ break;
+ /* PIH region */
+ case 0x81: /* PIH_ISR_P1 */
+ case 0x82: /* PIH_ISR_P2 */
+ case 0x83: /* PIH_SIR */
+ s->reg_data[addr] = value;
+ break;
+ /* INTBR region */
+ case 0x85: /* IDCODE_7_0 */
+ case 0x86: /* IDCODE_15_8 */
+ case 0x87: /* IDCODE_23_16 */
+ case 0x88: /* IDCODE_31_24 */
+ case 0x89: /* DIEID_7_0 */
+ case 0x8a: /* DIEID_15_8 */
+ case 0x8b: /* DIEID_23_16 */
+ case 0x8c: /* DIEID_31_24 */
+ case 0x8d: /* DIEID_39_32 */
+ case 0x8e: /* DIEID_47_40 */
+ case 0x8f: /* DIEID_55_48 */
+ case 0x90: /* DIEID_63_56 */
+ /* read-only, ignore */
+ break;
+ case 0x91: /* GPBR1 */
+ case 0x92: /* PMBR1 */
+ case 0x93: /* PMBR2 */
+ case 0x94: /* GPPUPDCTR1 */
+ case 0x95: /* GPPUPDCTR2 */
+ case 0x96: /* GPPUPDCTR3 */
+ case 0x97: /* UNLOCK_TEST_REG */
+ s->reg_data[addr] = value;
+ break;
+ /* GPIO region */
+ case 0x98: /* GPIODATAIN1 */
+ case 0x99: /* GPIODATAIN2 */
+ case 0x9a: /* GPIODATAIN3 */
+ /* read-only, ignore */
+ break;
case 0x9b: /* GPIODATADIR1 */
case 0x9c: /* GPIODATADIR2 */
case 0x9d: /* GPIODATADIR3 */
case 0xaf: /* GPIOPUPDCTR5 */
s->reg_data[addr] = value & 0x0f;
break;
+ case 0xb0: /* GPIO_TEST */
+ case 0xb1: /* GPIO_ISR1A */
+ case 0xb2: /* GPIO_ISR2A */
+ case 0xb3: /* GPIO_ISR3A */
case 0xb4: /* GPIO_IMR1A */
case 0xb5: /* GPIO_IMR2A */
s->reg_data[addr] = value;
case 0xb6: /* GPIO_IMR3A */
s->reg_data[addr] = value & 0x03;
break;
+ case 0xb7: /* GPIO_ISR1B */
+ case 0xb8: /* GPIO_ISR2B */
+ case 0xb9: /* GPIO_ISR3B */
+ case 0xba: /* GPIO_IMR1B */
+ case 0xbb: /* GPIO_IMR2B */
+ case 0xbc: /* GPIO_IMR3B */
+ case 0xbd: /* GPIO_SIR1 */
+ case 0xbe: /* GPIO_SIR2 */
+ case 0xbf: /* GPIO_SIR3 */
case 0xc0: /* GPIO_EDR1 */
case 0xc1: /* GPIO_EDR2 */
case 0xc2: /* GPIO_EDR3 */
s->reg_data[addr] = value & 0x07;
break;
default:
-#ifdef VERBOSE
- fprintf(stderr, "%s: unknown register %02x pc %x\n",
+ fprintf(stderr, "%s: unknown register 0x%02x pc %x\n",
__FUNCTION__, addr, cpu_single_env->regs[15]);
-#endif
break;
}
}
{
struct twl4030_i2c_s *s = (struct twl4030_i2c_s *) opaque;
+ TRACE("addr=0x%02x", addr);
switch (addr) {
case 0x61: /* MADC_ISR1 */
case 0xb9: /* BCIISR1A */
case 0xee: /* LEDEN */
return s->reg_data[addr];
default:
-#ifdef VERBOSE
fprintf(stderr, "%s: unknown register %02x pc %x\n",
- __FUNCTION__, addr,cpu_single_env->regs[15] );
-#endif
+ __FUNCTION__, addr, cpu_single_env->regs[15] );
break;
}
return 0;
static void twl4030_4a_write(void *opaque, uint8_t addr, uint8_t value)
{
struct twl4030_i2c_s *s = (struct twl4030_i2c_s *) opaque;
-
+
+ TRACE("addr=0x%02x, value=0x%02x", addr, value);
switch (addr) {
case 0x61: /* MADC_ISR1 */
s->reg_data[value] &= ~(value & 0x0f);
break;
case 0xee: /* LEDEN */
s->reg_data[addr] = value;
-#ifdef VERBOSE
- fprintf(stderr, "%s: LEDA power=%s/enable=%s, LEDB power=%s/enable=%s\n", __FUNCTION__,
+ TRACE("LEDA power=%s/enable=%s, LEDB power=%s/enable=%s",
value & 0x10 ? "on" : "off", value & 0x01 ? "yes" : "no",
value & 0x20 ? "on" : "off", value & 0x02 ? "yes" : "no");
-#endif
break;
case 0xef: /* PWMAON */
s->reg_data[addr] = value;
s->reg_data[addr] = value & 0x7f;
break;
default:
-#ifdef VERBOSE
fprintf(stderr, "%s: unknown register %02x pc %x\n",
- __FUNCTION__, addr,cpu_single_env->regs[15]);
-#endif
+ __FUNCTION__, addr, cpu_single_env->regs[15]);
break;
}
}
static uint8_t twl4030_4b_read(void *opaque, uint8_t addr)
{
struct twl4030_i2c_s *s = (struct twl4030_i2c_s *) opaque;
-
+
+ TRACE("addr=0x%02x", addr);
switch (addr) {
case 0x1c: /* RTC */
case 0x1d:
case 0x45: /* STS_HW_CONDITIONS - USB plugged, no VBUS -> host usb */
return 0x4;
default:
-#ifdef VERBOSE
fprintf(stderr, "%s: unknown register %02x pc %x \n",
- __FUNCTION__, addr,cpu_single_env->regs[15] );
-#endif
+ __FUNCTION__, addr, cpu_single_env->regs[15] );
break;
}
return 0;
{
struct twl4030_i2c_s *s = (struct twl4030_i2c_s *) opaque;
uint8_t seq_addr, seq_sub;
-
+
+ TRACE("addr=0x%02x, value=0x%02x", addr, value);
switch (addr) {
case 0x1c: /* SECONDS_REG */
case 0x1d: /* MINUTES_REG */
struct twl4030_s *s = (struct twl4030_s *) qemu_mallocz(sizeof(*s));
- if (!s)
- {
- fprintf(stderr,"can not alloc memory space for twl4030_s \n");
- exit(-1);
- }
- for (i=0;i<5;i++)
- {
- s->i2c[i]=(struct twl4030_i2c_s *)i2c_slave_init(bus, 0, sizeof(struct twl4030_i2c_s));
+ for (i = 0; i < 5; i++) {
+ s->i2c[i]=(struct twl4030_i2c_s *)i2c_slave_init(
+ bus, 0, sizeof(struct twl4030_i2c_s));
s->i2c[i]->irq = irq;
s->i2c[i]->twl4030 = s;
}
projects / qemu / commitdiff