--- /dev/null
+/*
+ * QEMU Sparc Sun4c interrupt controller emulation
+ *
+ * Based on slavio_intctl, copyright (c) 2003-2005 Fabrice Bellard
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+#include "hw.h"
+#include "sun4m.h"
+#include "console.h"
+//#define DEBUG_IRQ_COUNT
+//#define DEBUG_IRQ
+
+#ifdef DEBUG_IRQ
+#define DPRINTF(fmt, args...) \
+do { printf("IRQ: " fmt , ##args); } while (0)
+#else
+#define DPRINTF(fmt, args...)
+#endif
+
+/*
+ * Registers of interrupt controller in sun4c.
+ *
+ */
+
+#define MAX_PILS 16
+
+typedef struct Sun4c_INTCTLState {
+#ifdef DEBUG_IRQ_COUNT
+ uint64_t irq_count;
+#endif
+ qemu_irq *cpu_irqs;
+ const uint32_t *intbit_to_level;
+ uint32_t pil_out;
+ uint8_t reg;
+ uint8_t pending;
+} Sun4c_INTCTLState;
+
+#define INTCTL_MAXADDR 0
+#define INTCTL_SIZE (INTCTL_MAXADDR + 1)
+
+static void sun4c_check_interrupts(void *opaque);
+
+static uint32_t sun4c_intctl_mem_readb(void *opaque, target_phys_addr_t addr)
+{
+ Sun4c_INTCTLState *s = opaque;
+ uint32_t ret;
+
+ ret = s->reg;
+ DPRINTF("read reg 0x" TARGET_FMT_plx " = %x\n", addr, ret);
+
+ return ret;
+}
+
+static void sun4c_intctl_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
+{
+ Sun4c_INTCTLState *s = opaque;
+
+ DPRINTF("write reg 0x" TARGET_FMT_plx " = %x\n", addr, val);
+ val &= 0xbf;
+ s->reg = val;
+ sun4c_check_interrupts(s);
+}
+
+static CPUReadMemoryFunc *sun4c_intctl_mem_read[3] = {
+ sun4c_intctl_mem_readb,
+ sun4c_intctl_mem_readb,
+ sun4c_intctl_mem_readb,
+};
+
+static CPUWriteMemoryFunc *sun4c_intctl_mem_write[3] = {
+ sun4c_intctl_mem_writeb,
+ sun4c_intctl_mem_writeb,
+ sun4c_intctl_mem_writeb,
+};
+
+void sun4c_pic_info(void *opaque)
+{
+ Sun4c_INTCTLState *s = opaque;
+
+ term_printf("master: pending 0x%2.2x, enabled 0x%2.2x\n", s->pending, s->reg);
+}
+
+void sun4c_irq_info(void *opaque)
+{
+#ifndef DEBUG_IRQ_COUNT
+ term_printf("irq statistic code not compiled.\n");
+#else
+ Sun4c_INTCTLState *s = opaque;
+ int64_t count;
+
+ term_printf("IRQ statistics:\n");
+ count = s->irq_count[i];
+ if (count > 0)
+ term_printf("%2d: %" PRId64 "\n", i, count);
+#endif
+}
+
+static const uint32_t intbit_to_level[] = { 0, 1, 4, 6, 8, 10, 0, 14, };
+
+static void sun4c_check_interrupts(void *opaque)
+{
+ Sun4c_INTCTLState *s = opaque;
+ uint32_t pil_pending;
+ unsigned int i;
+
+ DPRINTF("pending %x disabled %x\n", pending, s->intregm_disabled);
+ pil_pending = 0;
+ if (s->pending && !(s->reg & 0x80000000)) {
+ for (i = 0; i < 8; i++) {
+ if (s->pending & (1 << i))
+ pil_pending |= 1 << intbit_to_level[i];
+ }
+ }
+
+ for (i = 0; i < MAX_PILS; i++) {
+ if (pil_pending & (1 << i)) {
+ if (!(s->pil_out & (1 << i)))
+ qemu_irq_raise(s->cpu_irqs[i]);
+ } else {
+ if (s->pil_out & (1 << i))
+ qemu_irq_lower(s->cpu_irqs[i]);
+ }
+ }
+ s->pil_out = pil_pending;
+}
+
+/*
+ * "irq" here is the bit number in the system interrupt register
+ */
+static void sun4c_set_irq(void *opaque, int irq, int level)
+{
+ Sun4c_INTCTLState *s = opaque;
+ uint32_t mask = 1 << irq;
+ uint32_t pil = intbit_to_level[irq];
+
+ DPRINTF("Set irq %d -> pil %d level %d\n", irq, pil,
+ level);
+ if (pil > 0) {
+ if (level) {
+#ifdef DEBUG_IRQ_COUNT
+ s->irq_count[pil]++;
+#endif
+ s->pending |= mask;
+ } else {
+ s->pending &= ~mask;
+ }
+ sun4c_check_interrupts(s);
+ }
+}
+
+static void sun4c_intctl_save(QEMUFile *f, void *opaque)
+{
+ Sun4c_INTCTLState *s = opaque;
+
+ qemu_put_8s(f, &s->reg);
+ qemu_put_8s(f, &s->pending);
+}
+
+static int sun4c_intctl_load(QEMUFile *f, void *opaque, int version_id)
+{
+ Sun4c_INTCTLState *s = opaque;
+
+ if (version_id != 1)
+ return -EINVAL;
+
+ qemu_get_8s(f, &s->reg);
+ qemu_get_8s(f, &s->pending);
+ sun4c_check_interrupts(s);
+
+ return 0;
+}
+
+static void sun4c_intctl_reset(void *opaque)
+{
+ Sun4c_INTCTLState *s = opaque;
+
+ s->reg = 1;
+ s->pending = 0;
+ sun4c_check_interrupts(s);
+}
+
+void *sun4c_intctl_init(target_phys_addr_t addr, qemu_irq **irq,
+ qemu_irq *parent_irq)
+{
+ int sun4c_intctl_io_memory;
+ Sun4c_INTCTLState *s;
+
+ s = qemu_mallocz(sizeof(Sun4c_INTCTLState));
+ if (!s)
+ return NULL;
+
+ sun4c_intctl_io_memory = cpu_register_io_memory(0, sun4c_intctl_mem_read,
+ sun4c_intctl_mem_write, s);
+ cpu_register_physical_memory(addr, INTCTL_SIZE, sun4c_intctl_io_memory);
+ s->cpu_irqs = parent_irq;
+
+ register_savevm("sun4c_intctl", addr, 1, sun4c_intctl_save,
+ sun4c_intctl_load, s);
+
+ qemu_register_reset(sun4c_intctl_reset, s);
+ *irq = qemu_allocate_irqs(sun4c_set_irq, s, 8);
+
+ sun4c_intctl_reset(s);
+ return s;
+}
+
/*
- * QEMU Sun4m & Sun4d System Emulator
+ * QEMU Sun4m & Sun4d & Sun4c System Emulator
*
* Copyright (c) 2003-2005 Fabrice Bellard
*
* SPARCcenter 2000
* SPARCserver 1000
*
+ * Sun4c architecture was used in the following machines:
+ * SPARCstation 1/1+, SPARCserver 1/1+
+ * SPARCstation SLC
+ * SPARCstation IPC
+ * SPARCstation ELC
+ * SPARCstation IPX
+ *
* See for example: http://www.sunhelp.org/faq/sunref1.html
*/
target_phys_addr_t tcx_base, cs_base, power_base;
target_phys_addr_t ecc_base;
uint32_t ecc_version;
+ target_phys_addr_t sun4c_intctl_base, sun4c_counter_base;
long vram_size, nvram_size;
// IRQ numbers are not PIL ones, but master interrupt controller register
// bit numbers
ecc_init(hwdef->ecc_base, hwdef->ecc_version);
}
+static void sun4c_hw_init(const struct hwdef *hwdef, int RAM_size,
+ const char *boot_device,
+ DisplayState *ds, const char *kernel_filename,
+ const char *kernel_cmdline,
+ const char *initrd_filename, const char *cpu_model)
+{
+ CPUState *env;
+ unsigned int i;
+ void *iommu, *espdma, *ledma, *main_esp, *nvram;
+ qemu_irq *cpu_irqs, *slavio_irq, *espdma_irq, *ledma_irq;
+ qemu_irq *esp_reset, *le_reset;
+ unsigned long prom_offset, kernel_size;
+ int ret;
+ char buf[1024];
+ BlockDriverState *fd[MAX_FD];
+ int index;
+
+ /* init CPU */
+ if (!cpu_model)
+ cpu_model = hwdef->default_cpu_model;
+
+ env = cpu_init(cpu_model);
+ if (!env) {
+ fprintf(stderr, "Unable to find Sparc CPU definition\n");
+ exit(1);
+ }
+
+ cpu_sparc_set_id(env, 0);
+
+ qemu_register_reset(main_cpu_reset, env);
+ register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
+ cpu_irqs = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS);
+
+ /* allocate RAM */
+ if ((uint64_t)RAM_size > hwdef->max_mem) {
+ fprintf(stderr, "qemu: Too much memory for this machine: %d, maximum %d\n",
+ (unsigned int)RAM_size / (1024 * 1024),
+ (unsigned int)hwdef->max_mem / (1024 * 1024));
+ exit(1);
+ }
+ cpu_register_physical_memory(0, RAM_size, 0);
+
+ /* load boot prom */
+ prom_offset = RAM_size + hwdef->vram_size;
+ cpu_register_physical_memory(hwdef->slavio_base,
+ (PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) &
+ TARGET_PAGE_MASK,
+ prom_offset | IO_MEM_ROM);
+
+ if (bios_name == NULL)
+ bios_name = PROM_FILENAME;
+ snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
+ ret = load_elf(buf, hwdef->slavio_base - PROM_VADDR, NULL, NULL, NULL);
+ if (ret < 0 || ret > PROM_SIZE_MAX)
+ ret = load_image(buf, phys_ram_base + prom_offset);
+ if (ret < 0 || ret > PROM_SIZE_MAX) {
+ fprintf(stderr, "qemu: could not load prom '%s'\n",
+ buf);
+ exit(1);
+ }
+ prom_offset += (ret + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
+
+ /* set up devices */
+ slavio_intctl = sun4c_intctl_init(hwdef->sun4c_intctl_base,
+ &slavio_irq, cpu_irqs);
+
+ iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version);
+
+ espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[hwdef->esp_irq],
+ iommu, &espdma_irq, &esp_reset);
+
+ ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
+ slavio_irq[hwdef->le_irq], iommu, &ledma_irq,
+ &le_reset);
+
+ if (graphic_depth != 8 && graphic_depth != 24) {
+ fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
+ exit (1);
+ }
+ tcx_init(ds, hwdef->tcx_base, phys_ram_base + RAM_size, RAM_size,
+ hwdef->vram_size, graphic_width, graphic_height, graphic_depth);
+
+ if (nd_table[0].model == NULL
+ || strcmp(nd_table[0].model, "lance") == 0) {
+ lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset);
+ } else if (strcmp(nd_table[0].model, "?") == 0) {
+ fprintf(stderr, "qemu: Supported NICs: lance\n");
+ exit (1);
+ } else {
+ fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model);
+ exit (1);
+ }
+
+ nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0,
+ hwdef->nvram_size, 8);
+
+ slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[hwdef->ms_kb_irq],
+ nographic);
+ // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
+ // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
+ slavio_serial_init(hwdef->serial_base, slavio_irq[hwdef->ser_irq],
+ serial_hds[1], serial_hds[0]);
+
+ if (hwdef->fd_base != (target_phys_addr_t)-1) {
+ /* there is zero or one floppy drive */
+ fd[1] = fd[0] = NULL;
+ index = drive_get_index(IF_FLOPPY, 0, 0);
+ if (index != -1)
+ fd[0] = drives_table[index].bdrv;
+
+ sun4m_fdctrl_init(slavio_irq[hwdef->fd_irq], hwdef->fd_base, fd);
+ }
+
+ if (drive_get_max_bus(IF_SCSI) > 0) {
+ fprintf(stderr, "qemu: too many SCSI bus\n");
+ exit(1);
+ }
+
+ main_esp = esp_init(hwdef->esp_base, espdma, *espdma_irq,
+ esp_reset);
+
+ for (i = 0; i < ESP_MAX_DEVS; i++) {
+ index = drive_get_index(IF_SCSI, 0, i);
+ if (index == -1)
+ continue;
+ esp_scsi_attach(main_esp, drives_table[index].bdrv, i);
+ }
+
+ kernel_size = sun4m_load_kernel(kernel_filename, kernel_cmdline,
+ initrd_filename);
+
+ nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
+ boot_device, RAM_size, kernel_size, graphic_width,
+ graphic_height, graphic_depth, hwdef->machine_id, "Sun4c");
+}
+
static const struct hwdef hwdefs[] = {
/* SS-5 */
{
.le_base = 0x78c00000,
.power_base = 0x7a000000,
.ecc_base = -1,
+ .sun4c_intctl_base = -1,
+ .sun4c_counter_base = -1,
.vram_size = 0x00100000,
.nvram_size = 0x2000,
.esp_irq = 18,
.power_base = 0xefa000000ULL,
.ecc_base = 0xf00000000ULL,
.ecc_version = 0x10000000, // version 0, implementation 1
+ .sun4c_intctl_base = -1,
+ .sun4c_counter_base = -1,
.vram_size = 0x00100000,
.nvram_size = 0x2000,
.esp_irq = 18,
.power_base = 0xefa000000ULL,
.ecc_base = 0xf00000000ULL,
.ecc_version = 0x00000000, // version 0, implementation 0
+ .sun4c_intctl_base = -1,
+ .sun4c_counter_base = -1,
.vram_size = 0x00100000,
.nvram_size = 0x2000,
.esp_irq = 18,
.power_base = 0xefa000000ULL,
.ecc_base = 0xf00000000ULL,
.ecc_version = 0x20000000, // version 0, implementation 2
+ .sun4c_intctl_base = -1,
+ .sun4c_counter_base = -1,
.vram_size = 0x00100000,
.nvram_size = 0x2000,
.esp_irq = 18,
.max_mem = 0xffffffff, // XXX actually first 62GB ok
.default_cpu_model = "TI SuperSparc II",
},
+ /* SS-2 */
+ {
+ .iommu_base = 0xf8000000,
+ .tcx_base = 0xfe000000,
+ .cs_base = -1,
+ .slavio_base = 0xf6000000,
+ .ms_kb_base = 0xf0000000,
+ .serial_base = 0xf1000000,
+ .nvram_base = 0xf2000000,
+ .fd_base = 0xf7200000,
+ .counter_base = -1,
+ .intctl_base = -1,
+ .dma_base = 0xf8400000,
+ .esp_base = 0xf8800000,
+ .le_base = 0xf8c00000,
+ .power_base = -1,
+ .sun4c_intctl_base = 0xf5000000,
+ .sun4c_counter_base = 0xf3000000,
+ .vram_size = 0x00100000,
+ .nvram_size = 0x2000, // XXX 0x800,
+ .esp_irq = 2,
+ .le_irq = 3,
+ .clock_irq = 5,
+ .clock1_irq = 7,
+ .ms_kb_irq = 1,
+ .ser_irq = 1,
+ .fd_irq = 1,
+ .me_irq = 1,
+ .cs_irq = -1,
+ .machine_id = 0x55,
+ .max_mem = 0x10000000,
+ .default_cpu_model = "Cypress CY7C601",
+ },
};
/* SPARCstation 5 hardware initialisation */
kernel_cmdline, initrd_filename, cpu_model);
}
+/* SPARCstation 2 hardware initialisation */
+static void ss2_init(int RAM_size, int vga_ram_size,
+ const char *boot_device, DisplayState *ds,
+ const char *kernel_filename, const char *kernel_cmdline,
+ const char *initrd_filename, const char *cpu_model)
+{
+ sun4c_hw_init(&hwdefs[4], RAM_size, boot_device, ds, kernel_filename,
+ kernel_cmdline, initrd_filename, cpu_model);
+}
+
QEMUMachine ss5_machine = {
"SS-5",
"Sun4m platform, SPARCstation 5",
ss20_init,
};
+QEMUMachine ss2_machine = {
+ "SS-2",
+ "Sun4c platform, SPARCstation 2",
+ ss2_init,
+};
static const struct sun4d_hwdef sun4d_hwdefs[] = {
/* SS-1000 */
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