Alpha coding style and inlining fixes.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3462 c046a42c-6fe2-441c-8c8c-71466251a162

diff --git a/target-alpha/cpu.h b/target-alpha/cpu.h
index 579ce61..d65ccde 100644 (file)
--- a/target-alpha/cpu.h
+++ b/target-alpha/cpu.h
@@ -27,14 +27,13 @@
 
 #include "cpu-defs.h"
 
-
 #include <setjmp.h>
 
 #include "softfloat.h"
 
 #define TARGET_HAS_ICE 1
 
-#define ELF_MACHINE    EM_ALPHA
+#define ELF_MACHINE     EM_ALPHA
 
 #define ICACHE_LINE_SIZE 32
 #define DCACHE_LINE_SIZE 32

diff --git a/target-alpha/exec.h b/target-alpha/exec.h
index 62cd07d..3b9754d 100644 (file)
--- a/target-alpha/exec.h
+++ b/target-alpha/exec.h
@@ -64,11 +64,11 @@ register uint64_t T2 asm(AREG3);
 #include "softmmu_exec.h"
 #endif /* !defined(CONFIG_USER_ONLY) */
 
-static inline void env_to_regs(void)
+static always_inline void env_to_regs(void)
 {
 }
 
-static inline void regs_to_env(void)
+static always_inline void regs_to_env(void)
 {
 }
 
@@ -79,7 +79,7 @@ int cpu_alpha_mtpr (CPUState *env, int iprn, uint64_t val, uint64_t *oldvalp);
 
 void do_interrupt (CPUState *env);
 
-static inline int cpu_halted(CPUState *env) {
+static always_inline int cpu_halted(CPUState *env) {
     if (!env->halted)
         return 0;
     if (env->interrupt_request & CPU_INTERRUPT_HARD) {

diff --git a/target-alpha/op_helper.c b/target-alpha/op_helper.c
index 3a34df4..f9390c8 100644 (file)
--- a/target-alpha/op_helper.c
+++ b/target-alpha/op_helper.c
@@ -294,7 +294,7 @@ void helper_cttz (void)
     T0 = n;
 }
 
-static inline uint64_t byte_zap (uint64_t op, uint8_t mskb)
+static always_inline uint64_t byte_zap (uint64_t op, uint8_t mskb)
 {
     uint64_t mask;
 
@@ -609,7 +609,7 @@ void helper_ftoit (void)
     FT0 = p.d;
 }
 
-static int vaxf_is_valid (float ff)
+static always_inline int vaxf_is_valid (float ff)
 {
     union {
         float f;
@@ -628,7 +628,7 @@ static int vaxf_is_valid (float ff)
     return 1;
 }
 
-static float vaxf_to_ieee32 (float ff)
+static always_inline float vaxf_to_ieee32 (float ff)
 {
     union {
         float f;
@@ -648,7 +648,7 @@ static float vaxf_to_ieee32 (float ff)
     return p.f;
 }
 
-static float ieee32_to_vaxf (float fi)
+static always_inline float ieee32_to_vaxf (float fi)
 {
     union {
         float f;
@@ -751,7 +751,7 @@ void helper_itoff (void)
     /* XXX: TODO */
 }
 
-static int vaxg_is_valid (double ff)
+static always_inline int vaxg_is_valid (double ff)
 {
     union {
         double f;
@@ -770,7 +770,7 @@ static int vaxg_is_valid (double ff)
     return 1;
 }
 
-static double vaxg_to_ieee64 (double fg)
+static always_inline double vaxg_to_ieee64 (double fg)
 {
     union {
         double f;
@@ -790,7 +790,7 @@ static double vaxg_to_ieee64 (double fg)
     return p.f;
 }
 
-static double ieee64_to_vaxg (double fi)
+static always_inline double ieee64_to_vaxg (double fi)
 {
     union {
         double f;
@@ -1044,7 +1044,7 @@ void helper_cvtlq (void)
     FT0 = q.d;
 }
 
-static inline void __helper_cvtql (int s, int v)
+static always_inline void __helper_cvtql (int s, int v)
 {
     union {
         double d;

diff --git a/target-alpha/op_mem.h b/target-alpha/op_mem.h
index 922d0d4..4a0cfc7 100644 (file)
--- a/target-alpha/op_mem.h
+++ b/target-alpha/op_mem.h
@@ -26,21 +26,22 @@ void helper_print_mem_EA (target_ulong EA);
 #define print_mem_EA(EA) do { } while (0)
 #endif
 
-static inline uint32_t glue(ldl_l, MEMSUFFIX) (target_ulong EA)
+static always_inline uint32_t glue(ldl_l, MEMSUFFIX) (target_ulong EA)
 {
     env->lock = EA;
 
     return glue(ldl, MEMSUFFIX)(EA);
 }
 
-static inline uint32_t glue(ldq_l, MEMSUFFIX) (target_ulong EA)
+static always_inline uint32_t glue(ldq_l, MEMSUFFIX) (target_ulong EA)
 {
     env->lock = EA;
 
     return glue(ldq, MEMSUFFIX)(EA);
 }
 
-static inline void glue(stl_c, MEMSUFFIX) (target_ulong EA, uint32_t data)
+static always_inline void glue(stl_c, MEMSUFFIX) (target_ulong EA,
+                                                  uint32_t data)
 {
     if (EA == env->lock) {
         glue(stl, MEMSUFFIX)(EA, data);
@@ -51,7 +52,8 @@ static inline void glue(stl_c, MEMSUFFIX) (target_ulong EA, uint32_t data)
     env->lock = -1;
 }
 
-static inline void glue(stq_c, MEMSUFFIX) (target_ulong EA, uint64_t data)
+static always_inline void glue(stq_c, MEMSUFFIX) (target_ulong EA,
+                                                  uint64_t data)
 {
     if (EA == env->lock) {
         glue(stq, MEMSUFFIX)(EA, data);

diff --git a/target-alpha/translate.c b/target-alpha/translate.c
index c036323..6f224b0 100644 (file)
--- a/target-alpha/translate.c
+++ b/target-alpha/translate.c
@@ -59,7 +59,7 @@ static uint32_t *gen_opparam_ptr;
 
 #include "gen-op.h"
 
-static inline void gen_op_nop (void)
+static always_inline void gen_op_nop (void)
 {
 #if defined(GENERATE_NOP)
     gen_op_no_op();
@@ -77,7 +77,7 @@ NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23,                               \
 NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27,                               \
 NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31,                               \
 };                                                                            \
-static inline void func(int n)                                                \
+static always_inline void func (int n)                                        \
 {                                                                             \
     NAME ## _table[n]();                                                      \
 }
@@ -99,7 +99,7 @@ GEN32(gen_op_store_T1_ir, gen_op_store_T1_ir);
 GEN32(gen_op_store_T2_ir, gen_op_store_T2_ir);
 GEN32(gen_op_cmov_ir, gen_op_cmov_ir);
 
-static inline void gen_load_ir (DisasContext *ctx, int irn, int Tn)
+static always_inline void gen_load_ir (DisasContext *ctx, int irn, int Tn)
 {
     switch (Tn) {
     case 0:
@@ -114,7 +114,7 @@ static inline void gen_load_ir (DisasContext *ctx, int irn, int Tn)
     }
 }
 
-static inline void gen_store_ir (DisasContext *ctx, int irn, int Tn)
+static always_inline void gen_store_ir (DisasContext *ctx, int irn, int Tn)
 {
     switch (Tn) {
     case 0:
@@ -146,7 +146,7 @@ GEN32(gen_op_store_FT1_fir, gen_op_store_FT1_fir);
 GEN32(gen_op_store_FT2_fir, gen_op_store_FT2_fir);
 GEN32(gen_op_cmov_fir, gen_op_cmov_fir);
 
-static inline void gen_load_fir (DisasContext *ctx, int firn, int Tn)
+static always_inline void gen_load_fir (DisasContext *ctx, int firn, int Tn)
 {
     switch (Tn) {
     case 0:
@@ -161,7 +161,7 @@ static inline void gen_load_fir (DisasContext *ctx, int firn, int Tn)
     }
 }
 
-static inline void gen_store_fir (DisasContext *ctx, int firn, int Tn)
+static always_inline void gen_store_fir (DisasContext *ctx, int firn, int Tn)
 {
     switch (Tn) {
     case 0:
@@ -205,14 +205,14 @@ static GenOpFunc *gen_op_st##width[] = {                                      \
 
 #define GEN_LD(width)                                                         \
 OP_LD_TABLE(width);                                                           \
-static void gen_ld##width (DisasContext *ctx)                                 \
+static always_inline void gen_ld##width (DisasContext *ctx)                   \
 {                                                                             \
     (*gen_op_ld##width[ctx->mem_idx])();                                      \
 }
 
 #define GEN_ST(width)                                                         \
 OP_ST_TABLE(width);                                                           \
-static void gen_st##width (DisasContext *ctx)                                 \
+static always_inline void gen_st##width (DisasContext *ctx)                   \
 {                                                                             \
     (*gen_op_st##width[ctx->mem_idx])();                                      \
 }
@@ -244,28 +244,28 @@ GEN_LD(t);
 GEN_ST(t);
 
 #if defined(__i386__) || defined(__x86_64__)
-static inline void gen_op_set_s16_T0 (int16_t imm)
+static always_inline void gen_op_set_s16_T0 (int16_t imm)
 {
     gen_op_set_s32_T0((int32_t)imm);
 }
 
-static inline void gen_op_set_s16_T1 (int16_t imm)
+static always_inline void gen_op_set_s16_T1 (int16_t imm)
 {
     gen_op_set_s32_T1((int32_t)imm);
 }
 
-static inline void gen_op_set_u16_T0 (uint16_t imm)
+static always_inline void gen_op_set_u16_T0 (uint16_t imm)
 {
     gen_op_set_s32_T0((uint32_t)imm);
 }
 
-static inline void gen_op_set_u16_T1 (uint16_t imm)
+static always_inline void gen_op_set_u16_T1 (uint16_t imm)
 {
     gen_op_set_s32_T1((uint32_t)imm);
 }
 #endif
 
-static inline void gen_set_sT0 (DisasContext *ctx, int64_t imm)
+static always_inline void gen_set_sT0 (DisasContext *ctx, int64_t imm)
 {
     int32_t imm32;
     int16_t imm16;
@@ -291,7 +291,7 @@ static inline void gen_set_sT0 (DisasContext *ctx, int64_t imm)
     }
 }
 
-static inline void gen_set_sT1 (DisasContext *ctx, int64_t imm)
+static always_inline void gen_set_sT1 (DisasContext *ctx, int64_t imm)
 {
     int32_t imm32;
     int16_t imm16;
@@ -317,7 +317,7 @@ static inline void gen_set_sT1 (DisasContext *ctx, int64_t imm)
     }
 }
 
-static inline void gen_set_uT0 (DisasContext *ctx, uint64_t imm)
+static always_inline void gen_set_uT0 (DisasContext *ctx, uint64_t imm)
 {
     if (!(imm >> 32)) {
         if ((!imm >> 16)) {
@@ -337,7 +337,7 @@ static inline void gen_set_uT0 (DisasContext *ctx, uint64_t imm)
     }
 }
 
-static inline void gen_set_uT1 (DisasContext *ctx, uint64_t imm)
+static always_inline void gen_set_uT1 (DisasContext *ctx, uint64_t imm)
 {
     if (!(imm >> 32)) {
         if ((!imm >> 16)) {
@@ -357,7 +357,7 @@ static inline void gen_set_uT1 (DisasContext *ctx, uint64_t imm)
     }
 }
 
-static inline void gen_update_pc (DisasContext *ctx)
+static always_inline void gen_update_pc (DisasContext *ctx)
 {
     if (!(ctx->pc >> 32)) {
         gen_op_update_pc32(ctx->pc);
@@ -370,7 +370,7 @@ static inline void gen_update_pc (DisasContext *ctx)
     }
 }
 
-static inline void _gen_op_bcond (DisasContext *ctx)
+static always_inline void _gen_op_bcond (DisasContext *ctx)
 {
 #if 0 // Qemu does not know how to do this...
     gen_op_bcond(ctx->pc);
@@ -379,20 +379,22 @@ static inline void _gen_op_bcond (DisasContext *ctx)
 #endif
 }
 
-static inline void gen_excp (DisasContext *ctx, int exception, int error_code)
+static always_inline void gen_excp (DisasContext *ctx,
+                                    int exception, int error_code)
 {
     gen_update_pc(ctx);
     gen_op_excp(exception, error_code);
 }
 
-static inline void gen_invalid (DisasContext *ctx)
+static always_inline void gen_invalid (DisasContext *ctx)
 {
     gen_excp(ctx, EXCP_OPCDEC, 0);
 }
 
-static void gen_load_mem (DisasContext *ctx,
-                          void (*gen_load_op)(DisasContext *ctx),
-                          int ra, int rb, int32_t disp16, int clear)
+static always_inline void gen_load_mem (DisasContext *ctx,
+                                        void (*gen_load_op)(DisasContext *ctx),
+                                        int ra, int rb, int32_t disp16,
+                                        int clear)
 {
     if (ra == 31 && disp16 == 0) {
         /* UNOP */
@@ -410,9 +412,10 @@ static void gen_load_mem (DisasContext *ctx,
     }
 }
 
-static void gen_store_mem (DisasContext *ctx,
-                           void (*gen_store_op)(DisasContext *ctx),
-                           int ra, int rb, int32_t disp16, int clear)
+static always_inline void gen_store_mem (DisasContext *ctx,
+                                         void (*gen_store_op)(DisasContext *ctx),
+                                         int ra, int rb, int32_t disp16,
+                                         int clear)
 {
     gen_load_ir(ctx, rb, 0);
     if (disp16 != 0) {
@@ -425,9 +428,9 @@ static void gen_store_mem (DisasContext *ctx,
     (*gen_store_op)(ctx);
 }
 
-static void gen_load_fmem (DisasContext *ctx,
-                           void (*gen_load_fop)(DisasContext *ctx),
-                          int ra, int rb, int32_t disp16)
+static always_inline void gen_load_fmem (DisasContext *ctx,
+                                         void (*gen_load_fop)(DisasContext *ctx),
+                                         int ra, int rb, int32_t disp16)
 {
     gen_load_ir(ctx, rb, 0);
     if (disp16 != 0) {
@@ -438,9 +441,9 @@ static void gen_load_fmem (DisasContext *ctx,
     gen_store_fir(ctx, ra, 1);
 }
 
-static void gen_store_fmem (DisasContext *ctx,
-                            void (*gen_store_fop)(DisasContext *ctx),
-                            int ra, int rb, int32_t disp16)
+static always_inline void gen_store_fmem (DisasContext *ctx,
+                                          void (*gen_store_fop)(DisasContext *ctx),
+                                          int ra, int rb, int32_t disp16)
 {
     gen_load_ir(ctx, rb, 0);
     if (disp16 != 0) {
@@ -451,8 +454,9 @@ static void gen_store_fmem (DisasContext *ctx,
     (*gen_store_fop)(ctx);
 }
 
-static void gen_bcond (DisasContext *ctx, void (*gen_test_op)(void),
-                       int ra, int32_t disp16)
+static always_inline void gen_bcond (DisasContext *ctx,
+                                     void (*gen_test_op)(void),
+                                     int ra, int32_t disp16)
 {
     if (disp16 != 0) {
         gen_set_uT0(ctx, ctx->pc);
@@ -466,8 +470,9 @@ static void gen_bcond (DisasContext *ctx, void (*gen_test_op)(void),
     _gen_op_bcond(ctx);
 }
 
-static void gen_fbcond (DisasContext *ctx, void (*gen_test_op)(void),
-                        int ra, int32_t disp16)
+static always_inline void gen_fbcond (DisasContext *ctx,
+                                      void (*gen_test_op)(void),
+                                      int ra, int32_t disp16)
 {
     if (disp16 != 0) {
         gen_set_uT0(ctx, ctx->pc);
@@ -481,8 +486,9 @@ static void gen_fbcond (DisasContext *ctx, void (*gen_test_op)(void),
     _gen_op_bcond(ctx);
 }
 
-static void gen_arith2 (DisasContext *ctx, void (*gen_arith_op)(void),
-                        int rb, int rc, int islit, int8_t lit)
+static always_inline void gen_arith2 (DisasContext *ctx,
+                                      void (*gen_arith_op)(void),
+                                      int rb, int rc, int islit, int8_t lit)
 {
     if (islit)
         gen_set_sT0(ctx, lit);
@@ -492,8 +498,10 @@ static void gen_arith2 (DisasContext *ctx, void (*gen_arith_op)(void),
     gen_store_ir(ctx, rc, 0);
 }
 
-static void gen_arith3 (DisasContext *ctx, void (*gen_arith_op)(void),
-                        int ra, int rb, int rc, int islit, int8_t lit)
+static always_inline void gen_arith3 (DisasContext *ctx,
+                                      void (*gen_arith_op)(void),
+                                      int ra, int rb, int rc,
+                                      int islit, int8_t lit)
 {
     gen_load_ir(ctx, ra, 0);
     if (islit)
@@ -504,8 +512,10 @@ static void gen_arith3 (DisasContext *ctx, void (*gen_arith_op)(void),
     gen_store_ir(ctx, rc, 0);
 }
 
-static void gen_cmov (DisasContext *ctx, void (*gen_test_op)(void),
-                      int ra, int rb, int rc, int islit, int8_t lit)
+static always_inline void gen_cmov (DisasContext *ctx,
+                                    void (*gen_test_op)(void),
+                                    int ra, int rb, int rc,
+                                    int islit, int8_t lit)
 {
     gen_load_ir(ctx, ra, 1);
     if (islit)
@@ -516,16 +526,18 @@ static void gen_cmov (DisasContext *ctx, void (*gen_test_op)(void),
     gen_op_cmov_ir(rc);
 }
 
-static void gen_farith2 (DisasContext *ctx, void (*gen_arith_fop)(void),
-                         int rb, int rc)
+static always_inline void gen_farith2 (DisasContext *ctx,
+                                       void (*gen_arith_fop)(void),
+                                       int rb, int rc)
 {
     gen_load_fir(ctx, rb, 0);
     (*gen_arith_fop)();
     gen_store_fir(ctx, rc, 0);
 }
 
-static void gen_farith3 (DisasContext *ctx, void (*gen_arith_fop)(void),
-                         int ra, int rb, int rc)
+static always_inline void gen_farith3 (DisasContext *ctx,
+                                       void (*gen_arith_fop)(void),
+                                       int ra, int rb, int rc)
 {
     gen_load_fir(ctx, ra, 0);
     gen_load_fir(ctx, rb, 1);
@@ -533,8 +545,9 @@ static void gen_farith3 (DisasContext *ctx, void (*gen_arith_fop)(void),
     gen_store_fir(ctx, rc, 0);
 }
 
-static void gen_fcmov (DisasContext *ctx, void (*gen_test_fop)(void),
-                       int ra, int rb, int rc)
+static always_inline void gen_fcmov (DisasContext *ctx,
+                                     void (*gen_test_fop)(void),
+                                     int ra, int rb, int rc)
 {
     gen_load_fir(ctx, ra, 0);
     gen_load_fir(ctx, rb, 1);
@@ -542,77 +555,79 @@ static void gen_fcmov (DisasContext *ctx, void (*gen_test_fop)(void),
     gen_op_cmov_fir(rc);
 }
 
-static void gen_fti (DisasContext *ctx, void (*gen_move_fop)(void),
-                     int ra, int rc)
+static always_inline void gen_fti (DisasContext *ctx,
+                                   void (*gen_move_fop)(void),
+                                   int ra, int rc)
 {
     gen_load_fir(ctx, rc, 0);
     (*gen_move_fop)();
     gen_store_ir(ctx, ra, 0);
 }
 
-static void gen_itf (DisasContext *ctx, void (*gen_move_fop)(void),
-                     int ra, int rc)
+static always_inline void gen_itf (DisasContext *ctx,
+                                   void (*gen_move_fop)(void),
+                                   int ra, int rc)
 {
     gen_load_ir(ctx, ra, 0);
     (*gen_move_fop)();
     gen_store_fir(ctx, rc, 0);
 }
 
-static void gen_s4addl (void)
+static always_inline void gen_s4addl (void)
 {
     gen_op_s4();
     gen_op_addl();
 }
 
-static void gen_s4subl (void)
+static always_inline void gen_s4subl (void)
 {
     gen_op_s4();
     gen_op_subl();
 }
 
-static void gen_s8addl (void)
+static always_inline void gen_s8addl (void)
 {
     gen_op_s8();
     gen_op_addl();
 }
 
-static void gen_s8subl (void)
+static always_inline void gen_s8subl (void)
 {
     gen_op_s8();
     gen_op_subl();
 }
 
-static void gen_s4addq (void)
+static always_inline void gen_s4addq (void)
 {
     gen_op_s4();
     gen_op_addq();
 }
 
-static void gen_s4subq (void)
+static always_inline void gen_s4subq (void)
 {
     gen_op_s4();
     gen_op_subq();
 }
 
-static void gen_s8addq (void)
+static always_inline void gen_s8addq (void)
 {
     gen_op_s8();
     gen_op_addq();
 }
 
-static void gen_s8subq (void)
+static always_inline void gen_s8subq (void)
 {
     gen_op_s8();
     gen_op_subq();
 }
 
-static void gen_amask (void)
+static always_inline void gen_amask (void)
 {
     gen_op_load_amask();
     gen_op_bic();
 }
 
-static int translate_one (DisasContext *ctx, uint32_t insn)
+static always_inline int translate_one (DisasContext *ctx, uint32_t insn)
 {
     uint32_t palcode;
     int32_t disp21, disp16, disp12;
@@ -1958,8 +1973,9 @@ static int translate_one (DisasContext *ctx, uint32_t insn)
     return ret;
 }
 
-int gen_intermediate_code_internal (CPUState *env, TranslationBlock *tb,
-                                    int search_pc)
+static always_inline int gen_intermediate_code_internal (CPUState *env,
+                                                         TranslationBlock *tb,
+                                                         int search_pc)
 {
 #if defined ALPHA_DEBUG_DISAS
     static int insn_count;