2 * ALSA SoC TLV320AIC3X codec driver
4 * Author: Vladimir Barinov, <vbarinov@embeddedalley.com>
5 * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com>
7 * Based on sound/soc/codecs/wm8753.c by Liam Girdwood
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 * The AIC3X is a driver for a low power stereo audio
15 * codecs aic31, aic32, aic33.
17 * It supports full aic33 codec functionality.
18 * The compatibility with aic32, aic31 is as follows:
20 * ---------------------------------------
21 * MONO_LOUT -> N/A | MONO_LOUT -> N/A
27 * truncated internal functionality in
28 * accordance with documentation
29 * ---------------------------------------
31 * Hence the machine layer should disable unsupported inputs/outputs by
32 * snd_soc_dapm_disable_pin(codec, "MONO_LOUT"), etc.
35 #include <linux/module.h>
36 #include <linux/moduleparam.h>
37 #include <linux/init.h>
38 #include <linux/delay.h>
40 #include <linux/i2c.h>
41 #include <linux/platform_device.h>
42 #include <sound/core.h>
43 #include <sound/pcm.h>
44 #include <sound/pcm_params.h>
45 #include <sound/soc.h>
46 #include <sound/soc-dapm.h>
47 #include <sound/initval.h>
48 #include <sound/tlv.h>
49 #include <sound/hwdep.h>
51 #include "tlv320aic3x.h"
53 #define AIC3X_VERSION "0.2"
55 static int hp_dac_lim = 9;
56 module_param(hp_dac_lim, int, 0);
58 /* Data for reading/writing to the IIR Filter hwdep */
59 struct aic3x_iir_coeffs {
60 short N0, N1, N2, D1, D2;
61 short N3, N4, N5, D4, D5;
64 struct aic3x_dacfilter_t {
65 struct aic3x_iir_coeffs coeffs;
69 .N0 = 27619, .N1 = -27034, .N2 = 26461, .D1 = 32131, .D2 = -31506,
70 .N3 = 27619, .N4 = -27034, .N5 = 26461, .D4 = 32131, .D5 = -31506,
75 /* codec private data */
80 struct snd_hwdep *hwdep;
81 struct aic3x_dacfilter_t dacfilter;
85 * AIC3X register cache
86 * We can't read the AIC3X register space when we are
87 * using 2 wire for device control, so we cache them instead.
88 * There is no point in caching the reset register
90 static const u8 aic3x_reg[AIC3X_CACHEREGNUM] = {
91 0x00, 0x00, 0x00, 0x10, /* 0 */
92 0x04, 0x00, 0x00, 0x00, /* 4 */
93 0x00, 0x00, 0x00, 0x01, /* 8 */
94 0x00, 0x00, 0x00, 0x80, /* 12 */
95 0x80, 0xff, 0xff, 0x78, /* 16 */
96 0x78, 0x78, 0x78, 0x78, /* 20 */
97 0x78, 0x00, 0x00, 0xfe, /* 24 */
98 0x00, 0x00, 0xfe, 0x00, /* 28 */
99 0x00, 0x00, 0x00, 0x00, /* 32 */
100 0x00, 0x00, 0x00, 0x00, /* 36 */
101 0x00, 0x00, 0x00, 0x80, /* 40 */
102 0x80, 0x00, 0x00, 0x00, /* 44 */
103 0x00, 0x00, 0x00, 0x04, /* 48 */
104 0x00, 0x00, 0x00, 0x00, /* 52 */
105 0x00, 0x00, 0x04, 0x00, /* 56 */
106 0x00, 0x00, 0x00, 0x00, /* 60 */
107 0x00, 0x04, 0x00, 0x00, /* 64 */
108 0x00, 0x00, 0x00, 0x00, /* 68 */
109 0x04, 0x00, 0x00, 0x00, /* 72 */
110 0x00, 0x00, 0x00, 0x00, /* 76 */
111 0x00, 0x00, 0x00, 0x00, /* 80 */
112 0x00, 0x00, 0x00, 0x00, /* 84 */
113 0x00, 0x00, 0x00, 0x00, /* 88 */
114 0x00, 0x00, 0x00, 0x00, /* 92 */
115 0x00, 0x00, 0x00, 0x00, /* 96 */
116 0x00, 0x00, 0x02, 0x00, /* 100 */
117 0x00, 0x00, 0x00, 0x00, /* 104 */
118 0x00, 0x00, 0x00, 0x00, /* 108 */
119 0x00, 0x00, 0x00, 0x00, /* 112 */
120 0x00, 0x00, 0x00, 0x00, /* 116 */
121 0x00, 0x00, 0x00, 0x00, /* 120 */
122 0x00, 0x00, 0x00, 0x00, /* 124 */
123 0x01, 0x6b, 0xe3, 0x96, /* 128 */
124 0x66, 0x67, 0x5d, 0x6b, /* 132 */
125 0xe3, 0x96, 0x66, 0x67, /* 136 */
126 0x5d, 0x7d, 0x83, 0x84, /* 140 */
127 0xee, 0x7d, 0x83, 0x84, /* 144 */
128 0xee, 0x39, 0x55, 0xf3, /* 148 */
129 0x2d, 0x53, 0x7e, 0x6b, /* 152 */
130 0xe3, 0x96, 0x66, 0x67, /* 156 */
131 0x5d, 0x6b, 0xe3, 0x96, /* 160 */
132 0x66, 0x67, 0x5d, 0x7d, /* 164 */
133 0x83, 0x84, 0xee, 0x7d, /* 168 */
134 0x83, 0x84, 0xee, 0x39, /* 172 */
135 0x55, 0xf3, 0x2d, 0x53, /* 176 */
136 0x7e, 0x7f, 0xff, 0x00, /* 180 */
137 0x00, 0x00, 0x00, 0x00, /* 184 */
138 0x00, 0x00, 0x00, 0x00, /* 188 */
139 0x00, 0x39, 0x55, 0xf3, /* 192 */
140 0x2d, 0x53, 0x7e, 0x39, /* 196 */
141 0x55, 0xf3, 0x2d, 0x53, /* 200 */
146 * read aic3x register cache
148 static inline unsigned int aic3x_read_reg_cache(struct snd_soc_codec *codec,
151 u8 *cache = codec->reg_cache;
152 if (reg >= AIC3X_CACHEREGNUM)
157 static inline int aic3x_read_coeff_reg_cache
158 (struct snd_soc_codec *codec, unsigned int msbreg)
161 val = aic3x_read_reg_cache(codec, msbreg) << 8;
162 val |= aic3x_read_reg_cache(codec, msbreg+1);
163 if(val > 32767) val -= 65536;
168 * write aic3x register cache
170 static inline void aic3x_write_reg_cache(struct snd_soc_codec *codec,
173 u8 *cache = codec->reg_cache;
174 if (reg >= AIC3X_CACHEREGNUM)
180 * write to the aic3x register space
182 static int aic3x_write(struct snd_soc_codec *codec,
183 unsigned int reg, unsigned int value)
185 static char curpage = -1;
186 u8 data[2], page = 0;
187 printk("MNZ: aic3x_write(reg = %i, val = %x), curpage = %i\n",
188 reg, value, curpage);
189 /*mutex_lock(&codec->mutex);*/
195 if(reg && curpage != page){
198 if (codec->hw_write(codec->control_data, data, 2) != 2){
199 /*mutex_unlock(&codec->mutex);*/
204 printk("MNZ: aic3x_write(), switched to page%i\n", curpage);
209 * D15..D8 aic3x register offset
210 * D7...D0 register data
215 if (codec->hw_write(codec->control_data, data, 2) == 2){
216 aic3x_write_reg_cache(codec, data[0] + page * 128, data[1]);
217 if(!reg) curpage = value; /* for reg = 0, ie, page setting */
218 /*mutex_unlock(&codec->mutex);*/
221 /*mutex_unlock(&codec->mutex);*/
228 /* Convert a value to 2s compliment and write to registers */
229 static int aic3x_write_coeff(struct snd_soc_codec *codec,
230 u8 msbreg, int value)
235 outp = 65536 + value;
239 aic3x_write(codec, msbreg, outp >> 8);
240 aic3x_write(codec, msbreg+1, outp);
247 * read from the aic3x register space
249 static int aic3x_read(struct snd_soc_codec *codec, unsigned int reg,
254 /* No read access is recommended if the chip is reset after use */
255 printk(KERN_ERR "%s(): Values are may be incorrect!\n", __func__);
257 if (codec->hw_read(codec->control_data, value, 1) != 1)
260 aic3x_write_reg_cache(codec, reg, *value);
264 static int aic3x_sync_hw(struct snd_soc_codec *codec)
266 u8 *cache = codec->reg_cache;
270 aic3x_write(codec, AIC3X_PAGE_SELECT, 1);
271 /*mutex_lock(&codec->mutex);*/
272 for (i = 1; i < AIC3X_PAGE1REGNUM; i++) {
274 data[1] = cache[i+128];
275 codec->hw_write(codec->control_data, data, 2);
277 /*mutex_unlock(&codec->mutex);*/
279 /* We do not rewrite page select nor reset again */
280 aic3x_write(codec, AIC3X_PAGE_SELECT, 0);
281 /*mutex_lock(&codec->mutex);*/
282 for (i = 2; i < AIC3X_PAGE0REGNUM; i++) {
285 codec->hw_write(codec->control_data, data, 2);
287 /*mutex_unlock(&codec->mutex);*/
293 * Reset for getting low power consumption after bypass paths
295 static void aic3x_reset(struct snd_soc_codec *codec)
297 aic3x_write(codec, AIC3X_RESET, SOFT_RESET);
298 aic3x_sync_hw(codec);
301 #define SOC_DAPM_SINGLE_AIC3X(xname, reg, shift, mask, invert) \
302 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
303 .info = snd_soc_info_volsw, \
304 .get = snd_soc_dapm_get_volsw, .put = snd_soc_dapm_put_volsw_aic3x, \
305 .private_value = SOC_SINGLE_VALUE(reg, shift, mask, invert) }
308 * All input lines are connected when !0xf and disconnected with 0xf bit field,
309 * so we have to use specific dapm_put call for input mixer
311 static int snd_soc_dapm_put_volsw_aic3x(struct snd_kcontrol *kcontrol,
312 struct snd_ctl_elem_value *ucontrol)
314 struct snd_soc_dapm_widget *widget = snd_kcontrol_chip(kcontrol);
315 struct soc_mixer_control *mc =
316 (struct soc_mixer_control *)kcontrol->private_value;
317 unsigned int reg = mc->reg;
318 unsigned int shift = mc->shift;
320 unsigned int mask = (1 << fls(max)) - 1;
321 unsigned int invert = mc->invert;
322 unsigned short val, val_mask;
324 struct snd_soc_dapm_path *path;
327 val = (ucontrol->value.integer.value[0] & mask);
335 val_mask = mask << shift;
338 mutex_lock(&widget->codec->mutex);
340 if (snd_soc_test_bits(widget->codec, reg, val_mask, val)) {
341 /* find dapm widget path assoc with kcontrol */
342 list_for_each_entry(path, &widget->codec->dapm_paths, list) {
343 if (path->kcontrol != kcontrol)
346 /* found, now check type */
350 path->connect = invert ? 0 : 1;
352 /* old connection must be powered down */
353 path->connect = invert ? 1 : 0;
358 snd_soc_dapm_sync(widget->codec);
361 ret = snd_soc_update_bits(widget->codec, reg, val_mask, val);
363 mutex_unlock(&widget->codec->mutex);
367 static const char *aic3x_left_dac_mux[] = { "DAC_L1", "DAC_L3", "DAC_L2" };
368 static const char *aic3x_right_dac_mux[] = { "DAC_R1", "DAC_R3", "DAC_R2" };
369 static const char *aic3x_left_hpcom_mux[] =
370 { "differential of HPLOUT", "constant VCM", "single-ended" };
371 static const char *aic3x_right_hpcom_mux[] =
372 { "differential of HPROUT", "constant VCM", "single-ended",
373 "differential of HPLCOM", "external feedback" };
374 static const char *aic3x_linein_mode_mux[] = { "single-ended", "differential" };
375 static const char *aic3x_adc_hpf[] =
376 { "Disabled", "0.0045xFs", "0.0125xFs", "0.025xFs" };
377 static const char *aic3x_dac_filt[] =
378 { "Off", "On", "Custom" };
382 #define LHPCOM_ENUM 2
383 #define RHPCOM_ENUM 3
384 #define LINE1L_ENUM 4
385 #define LINE1R_ENUM 5
386 #define LINE2L_ENUM 6
387 #define LINE2R_ENUM 7
388 #define ADC_HPF_ENUM 8
389 #define DAC_FILT_ENUM 9
391 static const struct soc_enum aic3x_enum[] = {
392 SOC_ENUM_SINGLE(DAC_LINE_MUX, 6, 3, aic3x_left_dac_mux),
393 SOC_ENUM_SINGLE(DAC_LINE_MUX, 4, 3, aic3x_right_dac_mux),
394 SOC_ENUM_SINGLE(HPLCOM_CFG, 4, 3, aic3x_left_hpcom_mux),
395 SOC_ENUM_SINGLE(HPRCOM_CFG, 3, 5, aic3x_right_hpcom_mux),
396 SOC_ENUM_SINGLE(LINE1L_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux),
397 SOC_ENUM_SINGLE(LINE1R_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux),
398 SOC_ENUM_SINGLE(LINE2L_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux),
399 SOC_ENUM_SINGLE(LINE2R_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux),
400 SOC_ENUM_DOUBLE(AIC3X_CODEC_DFILT_CTRL, 6, 4, 4, aic3x_adc_hpf),
401 SOC_ENUM_DOUBLE(AIC3X_CODEC_DFILT_CTRL, 1, 3, 3, aic3x_dac_filt),
405 * DAC digital volumes. From -63.5 to 0 dB in 0.5 dB steps
407 static DECLARE_TLV_DB_SCALE(dac_tlv, -6350, 50, 0);
408 /* ADC PGA gain volumes. From 0 to 59.5 dB in 0.5 dB steps */
409 static DECLARE_TLV_DB_SCALE(adc_tlv, 0, 50, 0);
410 /* HP DAC Output gain values. From 0 to 9.0 dB in 1 dB steps */
411 static DECLARE_TLV_DB_SCALE(hpout_tlv, 0, 100, 0);
413 * Output stage volumes. From -78.3 to 0 dB. Muted below -78.3 dB.
414 * Step size is approximately 0.5 dB over most of the scale but increasing
415 * near the very low levels.
416 * Define dB scale so that it is mostly correct for range about -55 to 0 dB
417 * but having increasing dB difference below that (and where it doesn't count
418 * so much). This setting shows -50 dB (actual is -50.3 dB) for register
419 * value 100 and -58.5 dB (actual is -78.3 dB) for register value 117.
421 static DECLARE_TLV_DB_SCALE(output_stage_tlv, -5900, 50, 1);
423 #define SOC_DOUBLE_R_TLV_TLV320ALC3X(xname, reg_left, reg_right, xshift, xmax,\
424 xinvert, tlv_array) \
425 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
426 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
427 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
428 .tlv.p = (tlv_array), \
429 .info = tlv320alc3x_info_volsw, \
430 .get = snd_soc_get_volsw_2r,\
431 .put = snd_soc_put_volsw_2r,\
432 .private_value = (unsigned long)&(struct soc_mixer_control) \
433 {.reg = reg_left, .rreg = reg_right, .shift = xshift, \
434 .max = xmax, .invert = xinvert} }
436 static int tlv320alc3x_info_volsw(struct snd_kcontrol *kcontrol,
437 struct snd_ctl_elem_info *uinfo)
439 struct soc_mixer_control *mc =
440 (struct soc_mixer_control *)kcontrol->private_value;
443 if (hp_dac_lim != max && hp_dac_lim >= 2 && hp_dac_lim <= 9)
447 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
449 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
452 uinfo->value.integer.min = 0;
453 uinfo->value.integer.max = max;
457 /* DAC Filter Functions */
459 static int aic3x_dacfilter_write_coeffs
460 (struct snd_soc_codec *codec, struct aic3x_iir_coeffs *coeffs)
462 struct aic3x_priv *aic3x = codec->private_data;
463 printk("MNZ: dacfilter_write_coeffs\n");
464 snd_soc_update_bits(codec, AIC3X_CODEC_DFILT_CTRL, EFFECTS_ON, 0);
465 aic3x_write_coeff(codec, EFFECTS_LEFT_N0, coeffs->N0);
466 aic3x_write_coeff(codec, EFFECTS_LEFT_N1, coeffs->N1);
467 aic3x_write_coeff(codec, EFFECTS_LEFT_N2, coeffs->N2);
468 aic3x_write_coeff(codec, EFFECTS_LEFT_D1, coeffs->D1);
469 aic3x_write_coeff(codec, EFFECTS_LEFT_D2, coeffs->D2);
470 aic3x_write_coeff(codec, EFFECTS_LEFT_N3, coeffs->N3);
471 aic3x_write_coeff(codec, EFFECTS_LEFT_N4, coeffs->N4);
472 aic3x_write_coeff(codec, EFFECTS_LEFT_N5, coeffs->N5);
473 aic3x_write_coeff(codec, EFFECTS_LEFT_D4, coeffs->D4);
474 aic3x_write_coeff(codec, EFFECTS_LEFT_D5, coeffs->D5);
476 aic3x_write_coeff(codec, EFFECTS_RIGHT_N0, coeffs->N0);
477 aic3x_write_coeff(codec, EFFECTS_RIGHT_N1, coeffs->N1);
478 aic3x_write_coeff(codec, EFFECTS_RIGHT_N2, coeffs->N2);
479 aic3x_write_coeff(codec, EFFECTS_RIGHT_D1, coeffs->D1);
480 aic3x_write_coeff(codec, EFFECTS_RIGHT_D2, coeffs->D2);
481 aic3x_write_coeff(codec, EFFECTS_RIGHT_N3, coeffs->N3);
482 aic3x_write_coeff(codec, EFFECTS_RIGHT_N4, coeffs->N4);
483 aic3x_write_coeff(codec, EFFECTS_RIGHT_N5, coeffs->N5);
484 aic3x_write_coeff(codec, EFFECTS_RIGHT_D4, coeffs->D4);
485 aic3x_write_coeff(codec, EFFECTS_RIGHT_D5, coeffs->D5);
487 snd_soc_update_bits(codec, AIC3X_CODEC_DFILT_CTRL, EFFECTS_ON, EFFECTS_ON);
489 memcpy((void*)&aic3x->dacfilter.coeffs, (void*)coeffs,
490 sizeof(struct aic3x_iir_coeffs));
494 static int aic3x_dacfilter_set_state(struct snd_soc_codec *codec,
497 struct aic3x_priv *aic3x = codec->private_data;
498 printk("MNZ: dacfilter_set_state(state = %i)\n", state);
500 if(aic3x->dacfilter.state == state) return 0;
502 aic3x->dacfilter.state = state;
505 snd_soc_update_bits(codec, AIC3X_CODEC_DFILT_CTRL,
507 else if(state == 1) {}
508 /* FIXME MNZ. Set preset from current chosen preset */
510 return aic3x_dacfilter_write_coeffs(codec,
511 &aic3x->dacfilter.coeffs);
515 /* DAC Filter hwdep device callbacks */
517 static int snd_hwdep_dacfilter_ioctl_aic3x(struct snd_hwdep *hw,
518 struct file *file, unsigned int cmd, unsigned long arg)
520 /* Only IOCTL command is for enabling/disabling filter, cmd = 1
521 * arg = 0 to disable, 1 to enable and set to bass/treble,
522 * 2 to enable and set to custom coeffs
524 struct snd_soc_codec *codec = hw->private_data;
525 if (cmd != 1) return -EINVAL;
526 return aic3x_dacfilter_set_state(codec, *((int*)arg));
530 static long snd_hwdep_dacfilter_read_aic3x(struct snd_hwdep *hw,
531 char __user *buf, long count, loff_t *offset)
533 struct aic3x_priv *aic3x =
534 ((struct snd_soc_codec*)hw->private_data)->private_data;
535 if(count != sizeof(struct aic3x_iir_coeffs)) return -EINVAL;
536 memcpy((void*)buf, (void*)&aic3x->dacfilter.coeffs, count);
540 static long snd_hwdep_dacfilter_write_aic3x(struct snd_hwdep *hw,
541 const char __user *buf, long count, loff_t *offset)
543 struct snd_soc_codec *codec = hw->private_data;
544 if(count != sizeof(struct aic3x_iir_coeffs)) return -EINVAL;
546 ((struct aic3x_priv*)codec->private_data)->dacfilter.state = 2;
548 return aic3x_dacfilter_write_coeffs(codec,
549 (struct aic3x_iir_coeffs*)buf);
552 /* DAC filter and 3D depth alsa controls callbacks */
554 static int snd_soc_get_dacfilter_aic3x(struct snd_kcontrol *kcontrol,
555 struct snd_ctl_elem_value *ucontrol)
557 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
558 printk("MNZ: get_dacfilter getting state: %i\n",((struct aic3x_priv*)codec->private_data)->dacfilter.state );
559 ucontrol->value.enumerated.item[0] =
560 ((struct aic3x_priv*)codec->private_data)->dacfilter.state;
564 static int snd_soc_put_dacfilter_aic3x(struct snd_kcontrol *kcontrol,
565 struct snd_ctl_elem_value *ucontrol)
567 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
568 printk("MNZ: put_dacfilter setting to %i\n", ucontrol->value.enumerated.item[0]);
569 if (ucontrol->value.enumerated.item[0] > 2)
571 aic3x_dacfilter_set_state(codec, ucontrol->value.enumerated.item[0]);
575 static int snd_soc_get_3d_attenuation_aic3x
576 (struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
578 int val = aic3x_read_coeff_reg_cache
579 (snd_kcontrol_chip(kcontrol), EFFECTS_3DATTEN);
580 val = ((val*100)/65530) + 50;
581 ucontrol->value.integer.value[0] = val;
585 static int snd_soc_put_3d_attenuation_aic3x
586 (struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
588 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
589 int val = ucontrol->value.integer.value[0];
590 if(val > 100 || val < 0) return -EINVAL;
593 snd_soc_update_bits(codec, AIC3X_ASD_INTF_CTRLA,
594 EFFECTS_3D_ON, EFFECTS_3D_ON);
595 val = ((val - 50) * 65535) / 100 ;
597 snd_soc_update_bits(codec, AIC3X_ASD_INTF_CTRLA,
602 aic3x_write_coeff(codec, EFFECTS_3DATTEN, val);
607 static const struct snd_kcontrol_new aic3x_snd_controls[] = {
609 SOC_DOUBLE_R_TLV("PCM Playback Volume",
610 LDAC_VOL, RDAC_VOL, 0, 0x7f, 1, dac_tlv),
612 SOC_DOUBLE_R_TLV("Line DAC Playback Volume",
613 DACL1_2_LLOPM_VOL, DACR1_2_RLOPM_VOL,
614 0, 118, 1, output_stage_tlv),
615 SOC_DOUBLE_R("Line DAC Playback Switch", LLOPM_CTRL, RLOPM_CTRL, 3,
617 SOC_DOUBLE_R_TLV("Line PGA Bypass Playback Volume",
618 PGAL_2_LLOPM_VOL, PGAR_2_RLOPM_VOL,
619 0, 118, 1, output_stage_tlv),
620 SOC_DOUBLE_R_TLV("Line Line2 Bypass Playback Volume",
621 LINE2L_2_LLOPM_VOL, LINE2R_2_RLOPM_VOL,
622 0, 118, 1, output_stage_tlv),
624 SOC_DOUBLE_R_TLV("Mono DAC Playback Volume",
625 DACL1_2_MONOLOPM_VOL, DACR1_2_MONOLOPM_VOL,
626 0, 118, 1, output_stage_tlv),
627 SOC_SINGLE("Mono DAC Playback Switch", MONOLOPM_CTRL, 3, 0x01, 0),
628 SOC_DOUBLE_R_TLV("Mono PGA Bypass Playback Volume",
629 PGAL_2_MONOLOPM_VOL, PGAR_2_MONOLOPM_VOL,
630 0, 118, 1, output_stage_tlv),
631 SOC_DOUBLE_R_TLV("Mono Line2 Bypass Playback Volume",
632 LINE2L_2_MONOLOPM_VOL, LINE2R_2_MONOLOPM_VOL,
633 0, 118, 1, output_stage_tlv),
635 SOC_DOUBLE_R_TLV("HP DAC Playback Volume",
636 DACL1_2_HPLOUT_VOL, DACR1_2_HPROUT_VOL,
637 0, 118, 1, output_stage_tlv),
638 SOC_DOUBLE_R("HP DAC Playback Switch", HPLOUT_CTRL, HPROUT_CTRL, 3,
640 SOC_DOUBLE_R_TLV_TLV320ALC3X("HP DAC Output Volume", HPLOUT_CTRL,
641 HPROUT_CTRL, 4, 9, 0, hpout_tlv),
642 SOC_DOUBLE_R_TLV("HP PGA Bypass Playback Volume",
643 PGAL_2_HPLOUT_VOL, PGAR_2_HPROUT_VOL,
644 0, 118, 1, output_stage_tlv),
645 SOC_DOUBLE_R_TLV("HP Line2 Bypass Playback Volume",
646 LINE2L_2_HPLOUT_VOL, LINE2R_2_HPROUT_VOL,
647 0, 118, 1, output_stage_tlv),
649 SOC_DOUBLE_R_TLV("HPCOM DAC Playback Volume",
650 DACL1_2_HPLCOM_VOL, DACR1_2_HPRCOM_VOL,
651 0, 118, 1, output_stage_tlv),
652 SOC_DOUBLE_R("HPCOM DAC Playback Switch", HPLCOM_CTRL, HPRCOM_CTRL, 3,
654 SOC_DOUBLE_R_TLV_TLV320ALC3X("HPCOM DAC Output Volume", HPLCOM_CTRL,
655 HPRCOM_CTRL, 4, 9, 0, hpout_tlv),
656 SOC_DOUBLE_R_TLV("HPCOM PGA Bypass Playback Volume",
657 PGAL_2_HPLCOM_VOL, PGAR_2_HPRCOM_VOL,
658 0, 118, 1, output_stage_tlv),
659 SOC_DOUBLE_R_TLV("HPCOM Line2 Bypass Playback Volume",
660 LINE2L_2_HPLCOM_VOL, LINE2R_2_HPRCOM_VOL,
661 0, 118, 1, output_stage_tlv),
664 * Note: enable Automatic input Gain Controller with care. It can
665 * adjust PGA to max value when ADC is on and will never go back.
667 SOC_DOUBLE_R("AGC Switch", LAGC_CTRL_A, RAGC_CTRL_A, 7, 0x01, 0),
670 SOC_DOUBLE_R_TLV("PGA Capture Volume", LADC_VOL, RADC_VOL,
672 SOC_DOUBLE_R("PGA Capture Switch", LADC_VOL, RADC_VOL, 7, 0x01, 1),
674 SOC_ENUM("ADC HPF Cut-off", aic3x_enum[ADC_HPF_ENUM]),
676 SOC_ENUM_EXT("Hardware EQ", aic3x_enum[DAC_FILT_ENUM],
677 snd_soc_get_dacfilter_aic3x, snd_soc_put_dacfilter_aic3x),
679 SOC_SINGLE_EXT("3D Control - Depth", EFFECTS_3DATTEN, 0, 100, 0,
680 snd_soc_get_3d_attenuation_aic3x, snd_soc_put_3d_attenuation_aic3x),
683 /* add non dapm controls */
684 static int aic3x_add_controls(struct snd_soc_codec *codec)
688 for (i = 0; i < ARRAY_SIZE(aic3x_snd_controls); i++) {
689 err = snd_ctl_add(codec->card,
690 snd_soc_cnew(&aic3x_snd_controls[i],
699 static int reset_after_bypass(struct snd_soc_dapm_widget *w,
700 struct snd_kcontrol *kcontrol, int event)
702 struct aic3x_priv *aic3x = w->codec->private_data;
703 struct soc_mixer_control *mc = NULL;
704 unsigned int reg = 0;
707 mc = (struct soc_mixer_control *)kcontrol->private_value;
711 if (reg == PGAL_2_LLOPM_VOL || reg == PGAR_2_RLOPM_VOL ||
712 reg == PGAL_2_HPLOUT_VOL || reg == PGAR_2_HPROUT_VOL) {
713 if (w->value & 0x80) {
714 /* Prepare reset on the chip */
715 if (reg == PGAL_2_LLOPM_VOL)
716 aic3x->prepare_reset |= 0x01;
717 else if (reg == PGAR_2_RLOPM_VOL)
718 aic3x->prepare_reset |= 0x02;
719 else if (reg == PGAL_2_HPLOUT_VOL)
720 aic3x->prepare_reset |= 0x04;
721 else if (reg == PGAR_2_HPROUT_VOL)
722 aic3x->prepare_reset |= 0x08;
724 if (aic3x->prepare_reset) {
725 if (reg == PGAL_2_LLOPM_VOL)
726 aic3x->prepare_reset &= ~0x01;
727 else if (reg == PGAR_2_RLOPM_VOL)
728 aic3x->prepare_reset &= ~0x02;
729 else if (reg == PGAL_2_HPLOUT_VOL)
730 aic3x->prepare_reset &= ~0x04;
731 else if (reg == PGAR_2_HPROUT_VOL)
732 aic3x->prepare_reset &= ~0x08;
734 * Controls may have now been turned off,
735 * once they were on, so schedule or
736 * issue a reset on the chip.
738 if (!aic3x->prepare_reset) {
739 if (!((w->codec->bias_level ==
741 (w->codec->bias_level ==
742 SND_SOC_BIAS_PREPARE)))
743 aic3x_reset(w->codec);
753 static const struct snd_kcontrol_new aic3x_left_dac_mux_controls =
754 SOC_DAPM_ENUM("Route", aic3x_enum[LDAC_ENUM]);
757 static const struct snd_kcontrol_new aic3x_right_dac_mux_controls =
758 SOC_DAPM_ENUM("Route", aic3x_enum[RDAC_ENUM]);
761 static const struct snd_kcontrol_new aic3x_left_hpcom_mux_controls =
762 SOC_DAPM_ENUM("Route", aic3x_enum[LHPCOM_ENUM]);
764 /* Right HPCOM Mux */
765 static const struct snd_kcontrol_new aic3x_right_hpcom_mux_controls =
766 SOC_DAPM_ENUM("Route", aic3x_enum[RHPCOM_ENUM]);
768 /* Left DAC_L1 Mixer */
769 static const struct snd_kcontrol_new aic3x_left_dac_mixer_controls[] = {
770 SOC_DAPM_SINGLE("Line Switch", DACL1_2_LLOPM_VOL, 7, 1, 0),
771 SOC_DAPM_SINGLE("Mono Switch", DACL1_2_MONOLOPM_VOL, 7, 1, 0),
772 SOC_DAPM_SINGLE("HP Switch", DACL1_2_HPLOUT_VOL, 7, 1, 0),
773 SOC_DAPM_SINGLE("HPCOM Switch", DACL1_2_HPLCOM_VOL, 7, 1, 0),
776 /* Right DAC_R1 Mixer */
777 static const struct snd_kcontrol_new aic3x_right_dac_mixer_controls[] = {
778 SOC_DAPM_SINGLE("Line Switch", DACR1_2_RLOPM_VOL, 7, 1, 0),
779 SOC_DAPM_SINGLE("Mono Switch", DACR1_2_MONOLOPM_VOL, 7, 1, 0),
780 SOC_DAPM_SINGLE("HP Switch", DACR1_2_HPROUT_VOL, 7, 1, 0),
781 SOC_DAPM_SINGLE("HPCOM Switch", DACR1_2_HPRCOM_VOL, 7, 1, 0),
785 static const struct snd_kcontrol_new aic3x_left_pga_mixer_controls[] = {
786 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_LADC_CTRL, 3, 1, 1),
787 SOC_DAPM_SINGLE_AIC3X("Line2L Switch", LINE2L_2_LADC_CTRL, 3, 1, 1),
788 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_LADC_CTRL, 4, 1, 1),
791 /* Right PGA Mixer */
792 static const struct snd_kcontrol_new aic3x_right_pga_mixer_controls[] = {
793 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_RADC_CTRL, 3, 1, 1),
794 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_RADC_CTRL, 3, 1, 1),
795 SOC_DAPM_SINGLE_AIC3X("Line2R Switch", LINE2R_2_RADC_CTRL, 3, 1, 1),
796 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_RADC_CTRL, 0, 1, 1),
800 static const struct snd_kcontrol_new aic3x_left_line1_mux_controls =
801 SOC_DAPM_ENUM("Route", aic3x_enum[LINE1L_ENUM]);
803 /* Right Line1 Mux */
804 static const struct snd_kcontrol_new aic3x_right_line1_mux_controls =
805 SOC_DAPM_ENUM("Route", aic3x_enum[LINE1R_ENUM]);
808 static const struct snd_kcontrol_new aic3x_left_line2_mux_controls =
809 SOC_DAPM_ENUM("Route", aic3x_enum[LINE2L_ENUM]);
811 /* Right Line2 Mux */
812 static const struct snd_kcontrol_new aic3x_right_line2_mux_controls =
813 SOC_DAPM_ENUM("Route", aic3x_enum[LINE2R_ENUM]);
815 /* Left PGA Bypass Mixer */
816 static const struct snd_kcontrol_new aic3x_left_pga_bp_mixer_controls[] = {
817 SOC_DAPM_SINGLE("Line Switch", PGAL_2_LLOPM_VOL, 7, 1, 0),
818 SOC_DAPM_SINGLE("Mono Switch", PGAL_2_MONOLOPM_VOL, 7, 1, 0),
819 SOC_DAPM_SINGLE("HP Switch", PGAL_2_HPLOUT_VOL, 7, 1, 0),
820 SOC_DAPM_SINGLE("HPCOM Switch", PGAL_2_HPLCOM_VOL, 7, 1, 0),
823 /* Right PGA Bypass Mixer */
824 static const struct snd_kcontrol_new aic3x_right_pga_bp_mixer_controls[] = {
825 SOC_DAPM_SINGLE("Line Switch", PGAR_2_RLOPM_VOL, 7, 1, 0),
826 SOC_DAPM_SINGLE("Mono Switch", PGAR_2_MONOLOPM_VOL, 7, 1, 0),
827 SOC_DAPM_SINGLE("HP Switch", PGAR_2_HPROUT_VOL, 7, 1, 0),
828 SOC_DAPM_SINGLE("HPCOM Switch", PGAR_2_HPRCOM_VOL, 7, 1, 0),
831 /* Left Line2 Bypass Mixer */
832 static const struct snd_kcontrol_new aic3x_left_line2_bp_mixer_controls[] = {
833 SOC_DAPM_SINGLE("Line Switch", LINE2L_2_LLOPM_VOL, 7, 1, 0),
834 SOC_DAPM_SINGLE("Mono Switch", LINE2L_2_MONOLOPM_VOL, 7, 1, 0),
835 SOC_DAPM_SINGLE("HP Switch", LINE2L_2_HPLOUT_VOL, 7, 1, 0),
836 SOC_DAPM_SINGLE("HPCOM Switch", LINE2L_2_HPLCOM_VOL, 7, 1, 0),
839 /* Right Line2 Bypass Mixer */
840 static const struct snd_kcontrol_new aic3x_right_line2_bp_mixer_controls[] = {
841 SOC_DAPM_SINGLE("Line Switch", LINE2R_2_RLOPM_VOL, 7, 1, 0),
842 SOC_DAPM_SINGLE("Mono Switch", LINE2R_2_MONOLOPM_VOL, 7, 1, 0),
843 SOC_DAPM_SINGLE("HP Switch", LINE2R_2_HPROUT_VOL, 7, 1, 0),
844 SOC_DAPM_SINGLE("HPCOM Switch", LINE2R_2_HPRCOM_VOL, 7, 1, 0),
847 static const struct snd_soc_dapm_widget aic3x_dapm_widgets[] = {
848 /* Left DAC to Left Outputs */
849 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", DAC_PWR, 7, 0),
850 SND_SOC_DAPM_MUX("Left DAC Mux", SND_SOC_NOPM, 0, 0,
851 &aic3x_left_dac_mux_controls),
852 SND_SOC_DAPM_MIXER("Left DAC_L1 Mixer", SND_SOC_NOPM, 0, 0,
853 &aic3x_left_dac_mixer_controls[0],
854 ARRAY_SIZE(aic3x_left_dac_mixer_controls)),
855 SND_SOC_DAPM_MUX("Left HPCOM Mux", SND_SOC_NOPM, 0, 0,
856 &aic3x_left_hpcom_mux_controls),
857 SND_SOC_DAPM_PGA("Left Line Out", LLOPM_CTRL, 0, 0, NULL, 0),
858 SND_SOC_DAPM_PGA("Left HP Out", HPLOUT_CTRL, 0, 0, NULL, 0),
859 SND_SOC_DAPM_PGA("Left HP Com", HPLCOM_CTRL, 0, 0, NULL, 0),
861 /* Right DAC to Right Outputs */
862 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", DAC_PWR, 6, 0),
863 SND_SOC_DAPM_MUX("Right DAC Mux", SND_SOC_NOPM, 0, 0,
864 &aic3x_right_dac_mux_controls),
865 SND_SOC_DAPM_MIXER("Right DAC_R1 Mixer", SND_SOC_NOPM, 0, 0,
866 &aic3x_right_dac_mixer_controls[0],
867 ARRAY_SIZE(aic3x_right_dac_mixer_controls)),
868 SND_SOC_DAPM_MUX("Right HPCOM Mux", SND_SOC_NOPM, 0, 0,
869 &aic3x_right_hpcom_mux_controls),
870 SND_SOC_DAPM_PGA("Right Line Out", RLOPM_CTRL, 0, 0, NULL, 0),
871 SND_SOC_DAPM_PGA("Right HP Out", HPROUT_CTRL, 0, 0, NULL, 0),
872 SND_SOC_DAPM_PGA("Right HP Com", HPRCOM_CTRL, 0, 0, NULL, 0),
875 SND_SOC_DAPM_PGA("Mono Out", MONOLOPM_CTRL, 0, 0, NULL, 0),
877 /* Left Inputs to Left ADC */
878 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", LINE1L_2_LADC_CTRL, 2, 0),
879 SND_SOC_DAPM_MIXER("Left PGA Mixer", SND_SOC_NOPM, 0, 0,
880 &aic3x_left_pga_mixer_controls[0],
881 ARRAY_SIZE(aic3x_left_pga_mixer_controls)),
882 SND_SOC_DAPM_MUX("Left Line1L Mux", SND_SOC_NOPM, 0, 0,
883 &aic3x_left_line1_mux_controls),
884 SND_SOC_DAPM_MUX("Left Line2L Mux", SND_SOC_NOPM, 0, 0,
885 &aic3x_left_line2_mux_controls),
887 /* Right Inputs to Right ADC */
888 SND_SOC_DAPM_ADC("Right ADC", "Right Capture",
889 LINE1R_2_RADC_CTRL, 2, 0),
890 SND_SOC_DAPM_MIXER("Right PGA Mixer", SND_SOC_NOPM, 0, 0,
891 &aic3x_right_pga_mixer_controls[0],
892 ARRAY_SIZE(aic3x_right_pga_mixer_controls)),
893 SND_SOC_DAPM_MUX("Right Line1L Mux", SND_SOC_NOPM, 0, 0,
894 &aic3x_right_line1_mux_controls),
895 SND_SOC_DAPM_MUX("Right Line1R Mux", SND_SOC_NOPM, 0, 0,
896 &aic3x_right_line1_mux_controls),
897 SND_SOC_DAPM_MUX("Right Line2R Mux", SND_SOC_NOPM, 0, 0,
898 &aic3x_right_line2_mux_controls),
901 * Not a real mic bias widget but similar function. This is for dynamic
902 * control of GPIO1 digital mic modulator clock output function when
905 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "GPIO1 dmic modclk",
906 AIC3X_GPIO1_REG, 4, 0xf,
907 AIC3X_GPIO1_FUNC_DIGITAL_MIC_MODCLK,
908 AIC3X_GPIO1_FUNC_DISABLED),
911 * Also similar function like mic bias. Selects digital mic with
912 * configurable oversampling rate instead of ADC converter.
914 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 128",
915 AIC3X_ASD_INTF_CTRLA, 0, 3, 1, 0),
916 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 64",
917 AIC3X_ASD_INTF_CTRLA, 0, 3, 2, 0),
918 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 32",
919 AIC3X_ASD_INTF_CTRLA, 0, 3, 3, 0),
922 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias 2V",
923 MICBIAS_CTRL, 6, 3, 1, 0),
924 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias 2.5V",
925 MICBIAS_CTRL, 6, 3, 2, 0),
926 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias AVDD",
927 MICBIAS_CTRL, 6, 3, 3, 0),
929 /* Left PGA to Left Output bypass */
930 SND_SOC_DAPM_MIXER_E("Left PGA Bypass Mixer", SND_SOC_NOPM, 0, 0,
931 &aic3x_left_pga_bp_mixer_controls[0],
932 ARRAY_SIZE(aic3x_left_pga_bp_mixer_controls),
933 reset_after_bypass, SND_SOC_DAPM_POST_REG),
935 /* Right PGA to Right Output bypass */
936 SND_SOC_DAPM_MIXER_E("Right PGA Bypass Mixer", SND_SOC_NOPM, 0, 0,
937 &aic3x_right_pga_bp_mixer_controls[0],
938 ARRAY_SIZE(aic3x_right_pga_bp_mixer_controls),
939 reset_after_bypass, SND_SOC_DAPM_POST_REG),
941 /* Left Line2 to Left Output bypass */
942 SND_SOC_DAPM_MIXER("Left Line2 Bypass Mixer", SND_SOC_NOPM, 0, 0,
943 &aic3x_left_line2_bp_mixer_controls[0],
944 ARRAY_SIZE(aic3x_left_line2_bp_mixer_controls)),
946 /* Right Line2 to Right Output bypass */
947 SND_SOC_DAPM_MIXER("Right Line2 Bypass Mixer", SND_SOC_NOPM, 0, 0,
948 &aic3x_right_line2_bp_mixer_controls[0],
949 ARRAY_SIZE(aic3x_right_line2_bp_mixer_controls)),
951 SND_SOC_DAPM_OUTPUT("LLOUT"),
952 SND_SOC_DAPM_OUTPUT("RLOUT"),
953 SND_SOC_DAPM_OUTPUT("MONO_LOUT"),
954 SND_SOC_DAPM_OUTPUT("HPLOUT"),
955 SND_SOC_DAPM_OUTPUT("HPROUT"),
956 SND_SOC_DAPM_OUTPUT("HPLCOM"),
957 SND_SOC_DAPM_OUTPUT("HPRCOM"),
959 SND_SOC_DAPM_INPUT("MIC3L"),
960 SND_SOC_DAPM_INPUT("MIC3R"),
961 SND_SOC_DAPM_INPUT("LINE1L"),
962 SND_SOC_DAPM_INPUT("LINE1R"),
963 SND_SOC_DAPM_INPUT("LINE2L"),
964 SND_SOC_DAPM_INPUT("LINE2R"),
967 static const struct snd_soc_dapm_route intercon[] = {
969 {"Left DAC Mux", "DAC_L1", "Left DAC"},
970 {"Left DAC Mux", "DAC_L2", "Left DAC"},
971 {"Left DAC Mux", "DAC_L3", "Left DAC"},
973 {"Left DAC_L1 Mixer", "Line Switch", "Left DAC Mux"},
974 {"Left DAC_L1 Mixer", "Mono Switch", "Left DAC Mux"},
975 {"Left DAC_L1 Mixer", "HP Switch", "Left DAC Mux"},
976 {"Left DAC_L1 Mixer", "HPCOM Switch", "Left DAC Mux"},
977 {"Left Line Out", NULL, "Left DAC Mux"},
978 {"Left HP Out", NULL, "Left DAC Mux"},
980 {"Left HPCOM Mux", "differential of HPLOUT", "Left DAC_L1 Mixer"},
981 {"Left HPCOM Mux", "constant VCM", "Left DAC_L1 Mixer"},
982 {"Left HPCOM Mux", "single-ended", "Left DAC_L1 Mixer"},
984 {"Left Line Out", NULL, "Left DAC_L1 Mixer"},
985 {"Mono Out", NULL, "Left DAC_L1 Mixer"},
986 {"Left HP Out", NULL, "Left DAC_L1 Mixer"},
987 {"Left HP Com", NULL, "Left HPCOM Mux"},
989 {"LLOUT", NULL, "Left Line Out"},
990 {"LLOUT", NULL, "Left Line Out"},
991 {"HPLOUT", NULL, "Left HP Out"},
992 {"HPLCOM", NULL, "Left HP Com"},
995 {"Right DAC Mux", "DAC_R1", "Right DAC"},
996 {"Right DAC Mux", "DAC_R2", "Right DAC"},
997 {"Right DAC Mux", "DAC_R3", "Right DAC"},
999 {"Right DAC_R1 Mixer", "Line Switch", "Right DAC Mux"},
1000 {"Right DAC_R1 Mixer", "Mono Switch", "Right DAC Mux"},
1001 {"Right DAC_R1 Mixer", "HP Switch", "Right DAC Mux"},
1002 {"Right DAC_R1 Mixer", "HPCOM Switch", "Right DAC Mux"},
1003 {"Right Line Out", NULL, "Right DAC Mux"},
1004 {"Right HP Out", NULL, "Right DAC Mux"},
1006 {"Right HPCOM Mux", "differential of HPROUT", "Right DAC_R1 Mixer"},
1007 {"Right HPCOM Mux", "constant VCM", "Right DAC_R1 Mixer"},
1008 {"Right HPCOM Mux", "single-ended", "Right DAC_R1 Mixer"},
1009 {"Right HPCOM Mux", "differential of HPLCOM", "Right DAC_R1 Mixer"},
1010 {"Right HPCOM Mux", "external feedback", "Right DAC_R1 Mixer"},
1012 {"Right Line Out", NULL, "Right DAC_R1 Mixer"},
1013 {"Mono Out", NULL, "Right DAC_R1 Mixer"},
1014 {"Right HP Out", NULL, "Right DAC_R1 Mixer"},
1015 {"Right HP Com", NULL, "Right HPCOM Mux"},
1017 {"RLOUT", NULL, "Right Line Out"},
1018 {"RLOUT", NULL, "Right Line Out"},
1019 {"HPROUT", NULL, "Right HP Out"},
1020 {"HPRCOM", NULL, "Right HP Com"},
1023 {"MONO_LOUT", NULL, "Mono Out"},
1024 {"MONO_LOUT", NULL, "Mono Out"},
1027 {"Left Line1L Mux", "single-ended", "LINE1L"},
1028 {"Left Line1L Mux", "differential", "LINE1L"},
1030 {"Left Line2L Mux", "single-ended", "LINE2L"},
1031 {"Left Line2L Mux", "differential", "LINE2L"},
1033 {"Left PGA Mixer", "Line1L Switch", "Left Line1L Mux"},
1034 {"Left PGA Mixer", "Line2L Switch", "Left Line2L Mux"},
1035 {"Left PGA Mixer", "Mic3L Switch", "MIC3L"},
1037 {"Left ADC", NULL, "Left PGA Mixer"},
1038 {"Left ADC", NULL, "GPIO1 dmic modclk"},
1041 {"Right Line1L Mux", "single-ended", "LINE1L"},
1042 {"Right Line1L Mux", "differential", "LINE1L"},
1044 {"Right Line1R Mux", "single-ended", "LINE1R"},
1045 {"Right Line1R Mux", "differential", "LINE1R"},
1047 {"Right Line2R Mux", "single-ended", "LINE2R"},
1048 {"Right Line2R Mux", "differential", "LINE2R"},
1050 {"Right PGA Mixer", "Line1L Switch", "Right Line1L Mux"},
1051 {"Right PGA Mixer", "Line1R Switch", "Right Line1R Mux"},
1052 {"Right PGA Mixer", "Line2R Switch", "Right Line2R Mux"},
1053 {"Right PGA Mixer", "Mic3R Switch", "MIC3R"},
1055 {"Right ADC", NULL, "Right PGA Mixer"},
1056 {"Right ADC", NULL, "GPIO1 dmic modclk"},
1058 /* Left PGA Bypass */
1059 {"Left PGA Bypass Mixer", "Line Switch", "Left PGA Mixer"},
1060 {"Left PGA Bypass Mixer", "Mono Switch", "Left PGA Mixer"},
1061 {"Left PGA Bypass Mixer", "HP Switch", "Left PGA Mixer"},
1062 {"Left PGA Bypass Mixer", "HPCOM Switch", "Left PGA Mixer"},
1064 {"Left HPCOM Mux", "differential of HPLOUT", "Left PGA Bypass Mixer"},
1065 {"Left HPCOM Mux", "constant VCM", "Left PGA Bypass Mixer"},
1066 {"Left HPCOM Mux", "single-ended", "Left PGA Bypass Mixer"},
1068 {"Left Line Out", NULL, "Left PGA Bypass Mixer"},
1069 {"Mono Out", NULL, "Left PGA Bypass Mixer"},
1070 {"Left HP Out", NULL, "Left PGA Bypass Mixer"},
1072 /* Right PGA Bypass */
1073 {"Right PGA Bypass Mixer", "Line Switch", "Right PGA Mixer"},
1074 {"Right PGA Bypass Mixer", "Mono Switch", "Right PGA Mixer"},
1075 {"Right PGA Bypass Mixer", "HP Switch", "Right PGA Mixer"},
1076 {"Right PGA Bypass Mixer", "HPCOM Switch", "Right PGA Mixer"},
1078 {"Right HPCOM Mux", "differential of HPROUT", "Right PGA Bypass Mixer"},
1079 {"Right HPCOM Mux", "constant VCM", "Right PGA Bypass Mixer"},
1080 {"Right HPCOM Mux", "single-ended", "Right PGA Bypass Mixer"},
1081 {"Right HPCOM Mux", "differential of HPLCOM", "Right PGA Bypass Mixer"},
1082 {"Right HPCOM Mux", "external feedback", "Right PGA Bypass Mixer"},
1084 {"Right Line Out", NULL, "Right PGA Bypass Mixer"},
1085 {"Mono Out", NULL, "Right PGA Bypass Mixer"},
1086 {"Right HP Out", NULL, "Right PGA Bypass Mixer"},
1088 /* Left Line2 Bypass */
1089 {"Left Line2 Bypass Mixer", "Line Switch", "Left Line2L Mux"},
1090 {"Left Line2 Bypass Mixer", "Mono Switch", "Left Line2L Mux"},
1091 {"Left Line2 Bypass Mixer", "HP Switch", "Left Line2L Mux"},
1092 {"Left Line2 Bypass Mixer", "HPCOM Switch", "Left Line2L Mux"},
1094 {"Left HPCOM Mux", "differential of HPLOUT", "Left Line2 Bypass Mixer"},
1095 {"Left HPCOM Mux", "constant VCM", "Left Line2 Bypass Mixer"},
1096 {"Left HPCOM Mux", "single-ended", "Left Line2 Bypass Mixer"},
1098 {"Left Line Out", NULL, "Left Line2 Bypass Mixer"},
1099 {"Mono Out", NULL, "Left Line2 Bypass Mixer"},
1100 {"Left HP Out", NULL, "Left Line2 Bypass Mixer"},
1102 /* Right Line2 Bypass */
1103 {"Right Line2 Bypass Mixer", "Line Switch", "Right Line2R Mux"},
1104 {"Right Line2 Bypass Mixer", "Mono Switch", "Right Line2R Mux"},
1105 {"Right Line2 Bypass Mixer", "HP Switch", "Right Line2R Mux"},
1106 {"Right Line2 Bypass Mixer", "HPCOM Switch", "Right Line2R Mux"},
1108 {"Right HPCOM Mux", "differential of HPROUT", "Right Line2 Bypass Mixer"},
1109 {"Right HPCOM Mux", "constant VCM", "Right Line2 Bypass Mixer"},
1110 {"Right HPCOM Mux", "single-ended", "Right Line2 Bypass Mixer"},
1111 {"Right HPCOM Mux", "differential of HPLCOM", "Right Line2 Bypass Mixer"},
1112 {"Right HPCOM Mux", "external feedback", "Right Line2 Bypass Mixer"},
1114 {"Right Line Out", NULL, "Right Line2 Bypass Mixer"},
1115 {"Mono Out", NULL, "Right Line2 Bypass Mixer"},
1116 {"Right HP Out", NULL, "Right Line2 Bypass Mixer"},
1119 * Logical path between digital mic enable and GPIO1 modulator clock
1122 {"GPIO1 dmic modclk", NULL, "DMic Rate 128"},
1123 {"GPIO1 dmic modclk", NULL, "DMic Rate 64"},
1124 {"GPIO1 dmic modclk", NULL, "DMic Rate 32"},
1127 static int aic3x_add_widgets(struct snd_soc_codec *codec)
1129 snd_soc_dapm_new_controls(codec, aic3x_dapm_widgets,
1130 ARRAY_SIZE(aic3x_dapm_widgets));
1132 /* set up audio path interconnects */
1133 snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
1135 snd_soc_dapm_new_widgets(codec);
1139 static int aic3x_hw_params(struct snd_pcm_substream *substream,
1140 struct snd_pcm_hw_params *params)
1142 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1143 struct snd_soc_device *socdev = rtd->socdev;
1144 struct snd_soc_codec *codec = socdev->codec;
1145 struct aic3x_priv *aic3x = codec->private_data;
1146 int codec_clk = 0, bypass_pll = 0, fsref, last_clk = 0;
1147 u8 data, r, p, pll_q, pll_p = 1, pll_r = 1, pll_j = 1;
1150 /* select data word length */
1152 aic3x_read_reg_cache(codec, AIC3X_ASD_INTF_CTRLB) & (~(0x3 << 4));
1153 switch (params_format(params)) {
1154 case SNDRV_PCM_FORMAT_S16_LE:
1156 case SNDRV_PCM_FORMAT_S20_3LE:
1157 data |= (0x01 << 4);
1159 case SNDRV_PCM_FORMAT_S24_LE:
1160 data |= (0x02 << 4);
1162 case SNDRV_PCM_FORMAT_S32_LE:
1163 data |= (0x03 << 4);
1166 aic3x_write(codec, AIC3X_ASD_INTF_CTRLB, data);
1168 /* Fsref can be 44100 or 48000 */
1169 fsref = (params_rate(params) % 11025 == 0) ? 44100 : 48000;
1171 /* Try to find a value for Q which allows us to bypass the PLL and
1172 * generate CODEC_CLK directly. */
1173 for (pll_q = 2; pll_q < 18; pll_q++)
1174 if (aic3x->sysclk / (128 * pll_q) == fsref) {
1181 aic3x_write(codec, AIC3X_PLL_PROGA_REG, pll_q << PLLQ_SHIFT);
1182 aic3x_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_CLKDIV);
1184 aic3x_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_PLLDIV);
1186 /* Route Left DAC to left channel input and
1187 * right DAC to right channel input */
1188 data = (LDAC2LCH | RDAC2RCH);
1189 data |= (fsref == 44100) ? FSREF_44100 : FSREF_48000;
1190 if (params_rate(params) >= 64000)
1191 data |= DUAL_RATE_MODE;
1192 aic3x_write(codec, AIC3X_CODEC_DATAPATH_REG, data);
1194 /* codec sample rate select */
1195 data = (fsref * 20) / params_rate(params);
1196 if (params_rate(params) < 64000)
1200 data |= (data << 4);
1201 aic3x_write(codec, AIC3X_SAMPLE_RATE_SEL_REG, data);
1207 * find an apropriate setup for j, d, r and p by iterating over
1208 * p and r - j and d are calculated for each fraction.
1209 * Up to 128 values are probed, the closest one wins the game.
1210 * The sysclk is divided by 1000 to prevent integer overflows.
1212 codec_clk = (2048 * fsref) / (aic3x->sysclk / 1000);
1214 for (r = 1; r <= 16; r++)
1215 for (p = 1; p <= 8; p++) {
1216 int clk, tmp = (codec_clk * pll_r * 10) / pll_p;
1218 u16 d = tmp % 10000;
1223 if (d != 0 && aic3x->sysclk < 10000000)
1226 /* This is actually 1000 * ((j + (d/10000)) * r) / p
1227 * The term had to be converted to get rid of the
1228 * division by 10000 */
1229 clk = ((10000 * j * r) + (d * r)) / (10 * p);
1231 /* check whether this values get closer than the best
1232 * ones we had before */
1233 if (abs(codec_clk - clk) < abs(codec_clk - last_clk)) {
1234 pll_j = j; pll_d = d; pll_r = r; pll_p = p;
1238 /* Early exit for exact matches */
1239 if (clk == codec_clk)
1243 if (last_clk == 0) {
1244 printk(KERN_ERR "%s(): unable to setup PLL\n", __func__);
1248 data = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
1249 aic3x_write(codec, AIC3X_PLL_PROGA_REG, data | (pll_p << PLLP_SHIFT));
1250 aic3x_write(codec, AIC3X_OVRF_STATUS_AND_PLLR_REG, pll_r << PLLR_SHIFT);
1251 aic3x_write(codec, AIC3X_PLL_PROGB_REG, pll_j << PLLJ_SHIFT);
1252 aic3x_write(codec, AIC3X_PLL_PROGC_REG, (pll_d >> 6) << PLLD_MSB_SHIFT);
1253 aic3x_write(codec, AIC3X_PLL_PROGD_REG,
1254 (pll_d & 0x3F) << PLLD_LSB_SHIFT);
1259 static int aic3x_mute(struct snd_soc_dai *dai, int mute)
1261 struct snd_soc_codec *codec = dai->codec;
1262 u8 ldac_reg = aic3x_read_reg_cache(codec, LDAC_VOL) & ~MUTE_ON;
1263 u8 rdac_reg = aic3x_read_reg_cache(codec, RDAC_VOL) & ~MUTE_ON;
1266 aic3x_write(codec, LDAC_VOL, ldac_reg | MUTE_ON);
1267 aic3x_write(codec, RDAC_VOL, rdac_reg | MUTE_ON);
1269 aic3x_write(codec, LDAC_VOL, ldac_reg);
1270 aic3x_write(codec, RDAC_VOL, rdac_reg);
1276 static int aic3x_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1277 int clk_id, unsigned int freq, int dir)
1279 struct snd_soc_codec *codec = codec_dai->codec;
1280 struct aic3x_priv *aic3x = codec->private_data;
1282 aic3x->sysclk = freq;
1286 static int aic3x_set_dai_fmt(struct snd_soc_dai *codec_dai,
1289 struct snd_soc_codec *codec = codec_dai->codec;
1290 struct aic3x_priv *aic3x = codec->private_data;
1291 u8 iface_areg, iface_breg;
1294 iface_areg = aic3x_read_reg_cache(codec, AIC3X_ASD_INTF_CTRLA) & 0x3f;
1295 iface_breg = aic3x_read_reg_cache(codec, AIC3X_ASD_INTF_CTRLB) & 0x3f;
1297 /* set master/slave audio interface */
1298 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1299 case SND_SOC_DAIFMT_CBM_CFM:
1301 iface_areg |= BIT_CLK_MASTER | WORD_CLK_MASTER;
1303 case SND_SOC_DAIFMT_CBS_CFS:
1311 * match both interface format and signal polarities since they
1314 switch (fmt & (SND_SOC_DAIFMT_FORMAT_MASK |
1315 SND_SOC_DAIFMT_INV_MASK)) {
1316 case (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF):
1318 case (SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_IB_NF):
1320 case (SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_IB_NF):
1321 iface_breg |= (0x01 << 6);
1323 case (SND_SOC_DAIFMT_RIGHT_J | SND_SOC_DAIFMT_NB_NF):
1324 iface_breg |= (0x02 << 6);
1326 case (SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_NB_NF):
1327 iface_breg |= (0x03 << 6);
1334 aic3x_write(codec, AIC3X_ASD_INTF_CTRLA, iface_areg);
1335 aic3x_write(codec, AIC3X_ASD_INTF_CTRLB, iface_breg);
1336 aic3x_write(codec, AIC3X_ASD_INTF_CTRLC, delay);
1341 static int aic3x_set_bias_level(struct snd_soc_codec *codec,
1342 enum snd_soc_bias_level level)
1344 struct aic3x_priv *aic3x = codec->private_data;
1348 case SND_SOC_BIAS_ON:
1349 /* all power is driven by DAPM system */
1350 if (aic3x->master) {
1352 reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
1353 aic3x_write(codec, AIC3X_PLL_PROGA_REG,
1356 * ensure that bit and word clocks are running also if
1357 * DAC and ADC are shutdown
1359 reg = aic3x_read_reg_cache(codec, AIC3X_ASD_INTF_CTRLA);
1360 aic3x_write(codec, AIC3X_ASD_INTF_CTRLA, reg | 0x10);
1363 case SND_SOC_BIAS_PREPARE:
1365 case SND_SOC_BIAS_STANDBY:
1367 * all power is driven by DAPM system,
1368 * so output power is safe if bypass was set
1370 if (aic3x->master) {
1371 reg = aic3x_read_reg_cache(codec, AIC3X_ASD_INTF_CTRLA);
1372 aic3x_write(codec, AIC3X_ASD_INTF_CTRLA, reg & ~0x10);
1374 reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
1375 aic3x_write(codec, AIC3X_PLL_PROGA_REG,
1378 /* Reset cannot be issued, if bypass paths are in use */
1379 if (!aic3x->prepare_reset)
1382 case SND_SOC_BIAS_OFF:
1383 /* force all power off */
1384 reg = aic3x_read_reg_cache(codec, LINE1L_2_LADC_CTRL);
1385 aic3x_write(codec, LINE1L_2_LADC_CTRL, reg & ~LADC_PWR_ON);
1386 reg = aic3x_read_reg_cache(codec, LINE1R_2_RADC_CTRL);
1387 aic3x_write(codec, LINE1R_2_RADC_CTRL, reg & ~RADC_PWR_ON);
1389 reg = aic3x_read_reg_cache(codec, DAC_PWR);
1390 aic3x_write(codec, DAC_PWR, reg & ~(LDAC_PWR_ON | RDAC_PWR_ON));
1392 reg = aic3x_read_reg_cache(codec, HPLOUT_CTRL);
1393 aic3x_write(codec, HPLOUT_CTRL, reg & ~HPLOUT_PWR_ON);
1394 reg = aic3x_read_reg_cache(codec, HPROUT_CTRL);
1395 aic3x_write(codec, HPROUT_CTRL, reg & ~HPROUT_PWR_ON);
1397 reg = aic3x_read_reg_cache(codec, HPLCOM_CTRL);
1398 aic3x_write(codec, HPLCOM_CTRL, reg & ~HPLCOM_PWR_ON);
1399 reg = aic3x_read_reg_cache(codec, HPRCOM_CTRL);
1400 aic3x_write(codec, HPRCOM_CTRL, reg & ~HPRCOM_PWR_ON);
1402 reg = aic3x_read_reg_cache(codec, MONOLOPM_CTRL);
1403 aic3x_write(codec, MONOLOPM_CTRL, reg & ~MONOLOPM_PWR_ON);
1405 reg = aic3x_read_reg_cache(codec, LLOPM_CTRL);
1406 aic3x_write(codec, LLOPM_CTRL, reg & ~LLOPM_PWR_ON);
1407 reg = aic3x_read_reg_cache(codec, RLOPM_CTRL);
1408 aic3x_write(codec, RLOPM_CTRL, reg & ~RLOPM_PWR_ON);
1410 if (aic3x->master) {
1411 reg = aic3x_read_reg_cache(codec, AIC3X_ASD_INTF_CTRLA);
1412 aic3x_write(codec, AIC3X_ASD_INTF_CTRLA, reg & ~0x10);
1414 reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
1415 aic3x_write(codec, AIC3X_PLL_PROGA_REG,
1420 codec->bias_level = level;
1425 void aic3x_set_gpio(struct snd_soc_codec *codec, int gpio, int state)
1427 u8 reg = gpio ? AIC3X_GPIO2_REG : AIC3X_GPIO1_REG;
1428 u8 bit = gpio ? 3: 0;
1429 u8 val = aic3x_read_reg_cache(codec, reg) & ~(1 << bit);
1430 aic3x_write(codec, reg, val | (!!state << bit));
1432 EXPORT_SYMBOL_GPL(aic3x_set_gpio);
1434 int aic3x_get_gpio(struct snd_soc_codec *codec, int gpio)
1436 u8 reg = gpio ? AIC3X_GPIO2_REG : AIC3X_GPIO1_REG;
1437 u8 val, bit = gpio ? 2: 1;
1439 aic3x_read(codec, reg, &val);
1440 return (val >> bit) & 1;
1442 EXPORT_SYMBOL_GPL(aic3x_get_gpio);
1444 int aic3x_headset_detected(struct snd_soc_codec *codec)
1447 aic3x_read(codec, AIC3X_RT_IRQ_FLAGS_REG, &val);
1448 return (val >> 2) & 1;
1450 EXPORT_SYMBOL_GPL(aic3x_headset_detected);
1452 #define AIC3X_RATES SNDRV_PCM_RATE_8000_96000
1453 #define AIC3X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1454 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
1456 struct snd_soc_dai aic3x_dai = {
1457 .name = "tlv320aic3x",
1459 .stream_name = "Playback",
1462 .rates = AIC3X_RATES,
1463 .formats = AIC3X_FORMATS,},
1465 .stream_name = "Capture",
1468 .rates = AIC3X_RATES,
1469 .formats = AIC3X_FORMATS,},
1471 .hw_params = aic3x_hw_params,
1474 .digital_mute = aic3x_mute,
1475 .set_sysclk = aic3x_set_dai_sysclk,
1476 .set_fmt = aic3x_set_dai_fmt,
1479 EXPORT_SYMBOL_GPL(aic3x_dai);
1481 static int aic3x_suspend(struct platform_device *pdev, pm_message_t state)
1483 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1484 struct snd_soc_codec *codec = socdev->codec;
1486 aic3x_write(codec, AIC3X_RESET, SOFT_RESET);
1491 static int aic3x_resume(struct platform_device *pdev)
1493 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1494 aic3x_sync_hw(socdev->codec);
1495 aic3x_set_bias_level(socdev->codec,
1496 socdev->codec->suspend_bias_level);
1502 * initialise the AIC3X driver
1503 * register the mixer and dsp interfaces with the kernel
1505 static int aic3x_init(struct snd_soc_device *socdev)
1507 struct snd_soc_codec *codec = socdev->codec;
1508 struct aic3x_setup_data *setup = socdev->codec_data;
1511 codec->name = "tlv320aic3x";
1512 codec->owner = THIS_MODULE;
1513 codec->read = aic3x_read_reg_cache;
1514 codec->write = aic3x_write;
1515 codec->set_bias_level = aic3x_set_bias_level;
1516 codec->dai = &aic3x_dai;
1518 codec->reg_cache_size = ARRAY_SIZE(aic3x_reg);
1519 codec->reg_cache = kmemdup(aic3x_reg, sizeof(aic3x_reg), GFP_KERNEL);
1520 if (codec->reg_cache == NULL)
1523 aic3x_write(codec, AIC3X_PAGE_SELECT, PAGE0_SELECT);
1524 aic3x_write(codec, AIC3X_RESET, SOFT_RESET);
1527 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
1529 printk(KERN_ERR "aic3x: failed to create pcms\n");
1533 /* DAC default volume and mute */
1534 aic3x_write(codec, LDAC_VOL, DEFAULT_VOL | MUTE_ON);
1535 aic3x_write(codec, RDAC_VOL, DEFAULT_VOL | MUTE_ON);
1537 /* DAC to HP default volume and route to Output mixer */
1538 aic3x_write(codec, DACL1_2_HPLOUT_VOL, DEFAULT_VOL | ROUTE_ON);
1539 aic3x_write(codec, DACR1_2_HPROUT_VOL, DEFAULT_VOL | ROUTE_ON);
1540 aic3x_write(codec, DACL1_2_HPLCOM_VOL, DEFAULT_VOL | ROUTE_ON);
1541 aic3x_write(codec, DACR1_2_HPRCOM_VOL, DEFAULT_VOL | ROUTE_ON);
1542 /* DAC to Line Out default volume and route to Output mixer */
1543 aic3x_write(codec, DACL1_2_LLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1544 aic3x_write(codec, DACR1_2_RLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1545 /* DAC to Mono Line Out default volume and route to Output mixer */
1546 aic3x_write(codec, DACL1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1547 aic3x_write(codec, DACR1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1549 /* unmute all outputs */
1550 reg = aic3x_read_reg_cache(codec, LLOPM_CTRL);
1551 aic3x_write(codec, LLOPM_CTRL, reg | UNMUTE);
1552 reg = aic3x_read_reg_cache(codec, RLOPM_CTRL);
1553 aic3x_write(codec, RLOPM_CTRL, reg | UNMUTE);
1554 reg = aic3x_read_reg_cache(codec, MONOLOPM_CTRL);
1555 aic3x_write(codec, MONOLOPM_CTRL, reg | UNMUTE);
1556 reg = aic3x_read_reg_cache(codec, HPLOUT_CTRL);
1557 aic3x_write(codec, HPLOUT_CTRL, reg | UNMUTE);
1558 reg = aic3x_read_reg_cache(codec, HPROUT_CTRL);
1559 aic3x_write(codec, HPROUT_CTRL, reg | UNMUTE);
1560 reg = aic3x_read_reg_cache(codec, HPLCOM_CTRL);
1561 aic3x_write(codec, HPLCOM_CTRL, reg | UNMUTE);
1562 reg = aic3x_read_reg_cache(codec, HPRCOM_CTRL);
1563 aic3x_write(codec, HPRCOM_CTRL, reg | UNMUTE);
1565 /* ADC default volume and unmute */
1566 aic3x_write(codec, LADC_VOL, DEFAULT_GAIN);
1567 aic3x_write(codec, RADC_VOL, DEFAULT_GAIN);
1568 /* By default route Line1 to ADC PGA mixer */
1569 aic3x_write(codec, LINE1L_2_LADC_CTRL, 0x0);
1570 aic3x_write(codec, LINE1R_2_RADC_CTRL, 0x0);
1572 /* PGA to HP Bypass default volume, disconnect from Output Mixer */
1573 aic3x_write(codec, PGAL_2_HPLOUT_VOL, DEFAULT_VOL);
1574 aic3x_write(codec, PGAR_2_HPROUT_VOL, DEFAULT_VOL);
1575 aic3x_write(codec, PGAL_2_HPLCOM_VOL, DEFAULT_VOL);
1576 aic3x_write(codec, PGAR_2_HPRCOM_VOL, DEFAULT_VOL);
1577 /* PGA to Line Out default volume, disconnect from Output Mixer */
1578 aic3x_write(codec, PGAL_2_LLOPM_VOL, DEFAULT_VOL);
1579 aic3x_write(codec, PGAR_2_RLOPM_VOL, DEFAULT_VOL);
1580 /* PGA to Mono Line Out default volume, disconnect from Output Mixer */
1581 aic3x_write(codec, PGAL_2_MONOLOPM_VOL, DEFAULT_VOL);
1582 aic3x_write(codec, PGAR_2_MONOLOPM_VOL, DEFAULT_VOL);
1584 /* Line2 to HP Bypass default volume, disconnect from Output Mixer */
1585 aic3x_write(codec, LINE2L_2_HPLOUT_VOL, DEFAULT_VOL);
1586 aic3x_write(codec, LINE2R_2_HPROUT_VOL, DEFAULT_VOL);
1587 aic3x_write(codec, LINE2L_2_HPLCOM_VOL, DEFAULT_VOL);
1588 aic3x_write(codec, LINE2R_2_HPRCOM_VOL, DEFAULT_VOL);
1589 /* Line2 Line Out default volume, disconnect from Output Mixer */
1590 aic3x_write(codec, LINE2L_2_LLOPM_VOL, DEFAULT_VOL);
1591 aic3x_write(codec, LINE2R_2_RLOPM_VOL, DEFAULT_VOL);
1592 /* Line2 to Mono Out default volume, disconnect from Output Mixer */
1593 aic3x_write(codec, LINE2L_2_MONOLOPM_VOL, DEFAULT_VOL);
1594 aic3x_write(codec, LINE2R_2_MONOLOPM_VOL, DEFAULT_VOL);
1596 /* off, with power on */
1597 aic3x_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1599 /* setup GPIO functions */
1600 aic3x_write(codec, AIC3X_GPIO1_REG, (setup->gpio_func[0] & 0xf) << 4);
1601 aic3x_write(codec, AIC3X_GPIO2_REG, (setup->gpio_func[1] & 0xf) << 4);
1603 aic3x_add_controls(codec);
1604 aic3x_add_widgets(codec);
1605 ret = snd_soc_register_card(socdev);
1607 printk(KERN_ERR "aic3x: failed to register card\n");
1611 /* Set some defaults for coefficients */
1612 aic3x_write_coeff(codec, EFFECTS_3DATTEN, -32768);
1617 snd_soc_free_pcms(socdev);
1618 snd_soc_dapm_free(socdev);
1620 kfree(codec->reg_cache);
1624 static struct snd_soc_device *aic3x_socdev;
1626 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1628 * AIC3X 2 wire address can be up to 4 devices with device addresses
1629 * 0x18, 0x19, 0x1A, 0x1B
1633 * If the i2c layer weren't so broken, we could pass this kind of data
1636 static int aic3x_i2c_probe(struct i2c_client *i2c,
1637 const struct i2c_device_id *id)
1639 struct snd_soc_device *socdev = aic3x_socdev;
1640 struct snd_soc_codec *codec = socdev->codec;
1643 i2c_set_clientdata(i2c, codec);
1644 codec->control_data = i2c;
1646 ret = aic3x_init(socdev);
1648 printk(KERN_ERR "aic3x: failed to initialise AIC3X\n");
1652 static int aic3x_i2c_remove(struct i2c_client *client)
1654 struct snd_soc_codec *codec = i2c_get_clientdata(client);
1655 kfree(codec->reg_cache);
1659 static const struct i2c_device_id aic3x_i2c_id[] = {
1660 { "tlv320aic3x", 0 },
1663 MODULE_DEVICE_TABLE(i2c, aic3x_i2c_id);
1665 /* machine i2c codec control layer */
1666 static struct i2c_driver aic3x_i2c_driver = {
1668 .name = "aic3x I2C Codec",
1669 .owner = THIS_MODULE,
1671 .probe = aic3x_i2c_probe,
1672 .remove = aic3x_i2c_remove,
1673 .id_table = aic3x_i2c_id,
1676 static int aic3x_i2c_read(struct i2c_client *client, u8 *value, int len)
1678 value[0] = i2c_smbus_read_byte_data(client, value[0]);
1682 static int aic3x_add_i2c_device(struct platform_device *pdev,
1683 const struct aic3x_setup_data *setup)
1685 struct i2c_board_info info;
1686 struct i2c_adapter *adapter;
1687 struct i2c_client *client;
1690 ret = i2c_add_driver(&aic3x_i2c_driver);
1692 dev_err(&pdev->dev, "can't add i2c driver\n");
1696 memset(&info, 0, sizeof(struct i2c_board_info));
1697 info.addr = setup->i2c_address;
1698 strlcpy(info.type, "tlv320aic3x", I2C_NAME_SIZE);
1700 adapter = i2c_get_adapter(setup->i2c_bus);
1702 dev_err(&pdev->dev, "can't get i2c adapter %d\n",
1707 client = i2c_new_device(adapter, &info);
1708 i2c_put_adapter(adapter);
1710 dev_err(&pdev->dev, "can't add i2c device at 0x%x\n",
1711 (unsigned int)info.addr);
1718 i2c_del_driver(&aic3x_i2c_driver);
1723 static int aic3x_probe(struct platform_device *pdev)
1725 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1726 struct aic3x_setup_data *setup;
1727 struct snd_soc_codec *codec;
1728 struct aic3x_priv *aic3x;
1729 struct snd_hwdep *hwdep;
1732 printk(KERN_INFO "AIC3X Audio Codec %s\n", AIC3X_VERSION);
1734 setup = socdev->codec_data;
1735 codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
1739 aic3x = kzalloc(sizeof(struct aic3x_priv), GFP_KERNEL);
1740 memcpy(&aic3x->dacfilter, &aic3x_dacfilter, sizeof(aic3x_dacfilter));
1742 if (aic3x == NULL) {
1747 codec->private_data = aic3x;
1748 socdev->codec = codec;
1749 mutex_init(&codec->mutex);
1750 INIT_LIST_HEAD(&codec->dapm_widgets);
1751 INIT_LIST_HEAD(&codec->dapm_paths);
1753 aic3x_socdev = socdev;
1754 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1755 if (setup->i2c_address) {
1756 codec->hw_write = (hw_write_t) i2c_master_send;
1757 codec->hw_read = (hw_read_t) aic3x_i2c_read;
1758 ret = aic3x_add_i2c_device(pdev, setup);
1761 /* Add other interfaces here */
1764 if(snd_hwdep_new(codec->card, "IIR Filter", 0, &hwdep) == 0){
1765 printk("MNZ: hwdep initialized\n");
1766 hwdep->private_data = codec;
1767 hwdep->ops.ioctl = snd_hwdep_dacfilter_ioctl_aic3x;
1768 hwdep->ops.read = snd_hwdep_dacfilter_read_aic3x;
1769 hwdep->ops.write = snd_hwdep_dacfilter_write_aic3x;
1770 aic3x->hwdep = hwdep;
1774 kfree(codec->private_data);
1780 static int aic3x_remove(struct platform_device *pdev)
1782 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1783 struct snd_soc_codec *codec = socdev->codec;
1785 /* power down chip */
1786 if (codec->control_data)
1787 aic3x_set_bias_level(codec, SND_SOC_BIAS_OFF);
1789 snd_soc_free_pcms(socdev);
1790 snd_soc_dapm_free(socdev);
1791 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1792 if (codec->control_data)
1793 i2c_unregister_device(codec->control_data);
1794 i2c_del_driver(&aic3x_i2c_driver);
1796 kfree(codec->private_data);
1802 struct snd_soc_codec_device soc_codec_dev_aic3x = {
1803 .probe = aic3x_probe,
1804 .remove = aic3x_remove,
1805 .suspend = aic3x_suspend,
1806 .resume = aic3x_resume,
1808 EXPORT_SYMBOL_GPL(soc_codec_dev_aic3x);
1810 MODULE_DESCRIPTION("ASoC TLV320AIC3X codec driver");
1811 MODULE_AUTHOR("Vladimir Barinov");
1812 MODULE_LICENSE("GPL");