2 * ALSA SoC TLV320AIC3X codec driver
4 * Author: Vladimir Barinov, <vbarinov@embeddedalley.com>
5 * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com>
7 * Based on sound/soc/codecs/wm8753.c by Liam Girdwood
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 * The AIC3X is a driver for a low power stereo audio
15 * codecs aic31, aic32, aic33.
17 * It supports full aic33 codec functionality.
18 * The compatibility with aic32, aic31 is as follows:
20 * ---------------------------------------
21 * MONO_LOUT -> N/A | MONO_LOUT -> N/A
27 * truncated internal functionality in
28 * accordance with documentation
29 * ---------------------------------------
31 * Hence the machine layer should disable unsupported inputs/outputs by
32 * snd_soc_dapm_disable_pin(codec, "MONO_LOUT"), etc.
35 #include <linux/module.h>
36 #include <linux/moduleparam.h>
37 #include <linux/init.h>
38 #include <linux/delay.h>
40 #include <linux/i2c.h>
41 #include <linux/platform_device.h>
42 #include <sound/core.h>
43 #include <sound/pcm.h>
44 #include <sound/pcm_params.h>
45 #include <sound/soc.h>
46 #include <sound/soc-dapm.h>
47 #include <sound/initval.h>
48 #include <sound/tlv.h>
49 #include <sound/hwdep.h>
51 #include "tlv320aic3x.h"
53 #define AIC3X_VERSION "0.2"
55 static int hp_dac_lim = 9;
56 module_param(hp_dac_lim, int, 0);
58 /* Data for reading/writing to the IIR Filter hwdep */
59 struct aic3x_iir_coeffs {
60 short N0, N1, N2, D1, D2;
61 short N3, N4, N5, D4, D5;
64 struct aic3x_dacfilter_t {
65 struct aic3x_iir_coeffs coeffs;
69 .N0 = 27619, .N1 = -27034, .N2 = 26461, .D1 = 32131, .D2 = -31506,
70 .N3 = 27619, .N4 = -27034, .N5 = 26461, .D4 = 32131, .D5 = -31506,
75 /* codec private data */
80 struct snd_hwdep *hwdep;
81 struct aic3x_dacfilter_t dacfilter;
85 * AIC3X register cache
86 * We can't read the AIC3X register space when we are
87 * using 2 wire for device control, so we cache them instead.
88 * There is no point in caching the reset register
90 static const u8 aic3x_reg[AIC3X_CACHEREGNUM] = {
91 0x00, 0x00, 0x00, 0x10, /* 0 */
92 0x04, 0x00, 0x00, 0x00, /* 4 */
93 0x00, 0x00, 0x00, 0x01, /* 8 */
94 0x00, 0x00, 0x00, 0x80, /* 12 */
95 0x80, 0xff, 0xff, 0x78, /* 16 */
96 0x78, 0x78, 0x78, 0x78, /* 20 */
97 0x78, 0x00, 0x00, 0xfe, /* 24 */
98 0x00, 0x00, 0xfe, 0x00, /* 28 */
99 0x00, 0x00, 0x00, 0x00, /* 32 */
100 0x00, 0x00, 0x00, 0x00, /* 36 */
101 0x00, 0x00, 0x00, 0x80, /* 40 */
102 0x80, 0x00, 0x00, 0x00, /* 44 */
103 0x00, 0x00, 0x00, 0x04, /* 48 */
104 0x00, 0x00, 0x00, 0x00, /* 52 */
105 0x00, 0x00, 0x04, 0x00, /* 56 */
106 0x00, 0x00, 0x00, 0x00, /* 60 */
107 0x00, 0x04, 0x00, 0x00, /* 64 */
108 0x00, 0x00, 0x00, 0x00, /* 68 */
109 0x04, 0x00, 0x00, 0x00, /* 72 */
110 0x00, 0x00, 0x00, 0x00, /* 76 */
111 0x00, 0x00, 0x00, 0x00, /* 80 */
112 0x00, 0x00, 0x00, 0x00, /* 84 */
113 0x00, 0x00, 0x00, 0x00, /* 88 */
114 0x00, 0x00, 0x00, 0x00, /* 92 */
115 0x00, 0x00, 0x00, 0x00, /* 96 */
116 0x00, 0x00, 0x02, 0x00, /* 100 */
117 0x00, 0x00, 0x00, 0x00, /* 104 */
118 0x00, 0x00, 0x00, 0x00, /* 108 */
119 0x00, 0x00, 0x00, 0x00, /* 112 */
120 0x00, 0x00, 0x00, 0x00, /* 116 */
121 0x00, 0x00, 0x00, 0x00, /* 120 */
122 0x00, 0x00, 0x00, 0x00, /* 124 */
123 0x01, 0x6b, 0xe3, 0x96, /* 128 */
124 0x66, 0x67, 0x5d, 0x6b, /* 132 */
125 0xe3, 0x96, 0x66, 0x67, /* 136 */
126 0x5d, 0x7d, 0x83, 0x84, /* 140 */
127 0xee, 0x7d, 0x83, 0x84, /* 144 */
128 0xee, 0x39, 0x55, 0xf3, /* 148 */
129 0x2d, 0x53, 0x7e, 0x6b, /* 152 */
130 0xe3, 0x96, 0x66, 0x67, /* 156 */
131 0x5d, 0x6b, 0xe3, 0x96, /* 160 */
132 0x66, 0x67, 0x5d, 0x7d, /* 164 */
133 0x83, 0x84, 0xee, 0x7d, /* 168 */
134 0x83, 0x84, 0xee, 0x39, /* 172 */
135 0x55, 0xf3, 0x2d, 0x53, /* 176 */
136 0x7e, 0x7f, 0xff, 0x00, /* 180 */
137 0x00, 0x00, 0x00, 0x00, /* 184 */
138 0x00, 0x00, 0x00, 0x00, /* 188 */
139 0x00, 0x39, 0x55, 0xf3, /* 192 */
140 0x2d, 0x53, 0x7e, 0x39, /* 196 */
141 0x55, 0xf3, 0x2d, 0x53, /* 200 */
146 * read aic3x register cache
148 static inline unsigned int aic3x_read_reg_cache(struct snd_soc_codec *codec,
151 u8 *cache = codec->reg_cache;
152 if (reg >= AIC3X_CACHEREGNUM)
157 static inline int aic3x_read_coeff_reg_cache
158 (struct snd_soc_codec *codec, unsigned int msbreg)
161 val = aic3x_read_reg_cache(codec, msbreg) << 8;
162 val |= aic3x_read_reg_cache(codec, msbreg+1);
163 if(val > 32767) val -= 65536;
168 * write aic3x register cache
170 static inline void aic3x_write_reg_cache(struct snd_soc_codec *codec,
173 u8 *cache = codec->reg_cache;
174 if (reg >= AIC3X_CACHEREGNUM)
180 * write to the aic3x register space
182 static int aic3x_write(struct snd_soc_codec *codec,
183 unsigned int reg, unsigned int value)
185 static char curpage = -1;
186 u8 data[2], page = 0;
188 /*mutex_lock(&codec->mutex);*/
194 printk("MNZ: aic3x_write(reg = %i, val = 0x%x, page = %i)\n",
196 if(reg && curpage != page){
199 if (codec->hw_write(codec->control_data, data, 2) != 2){
200 /*mutex_unlock(&codec->mutex);*/
209 * D15..D8 aic3x register offset
210 * D7...D0 register data
215 if (codec->hw_write(codec->control_data, data, 2) == 2){
216 aic3x_write_reg_cache(codec, data[0] + page * 128, data[1]);
217 if(!reg) curpage = value; /* for reg = 0, ie, page setting */
218 /*mutex_unlock(&codec->mutex);*/
221 /*mutex_unlock(&codec->mutex);*/
228 /* Convert a value to 2s compliment and write to registers */
229 static int aic3x_write_coeff(struct snd_soc_codec *codec,
230 u8 msbreg, int value)
235 outp = 65536 + value;
239 aic3x_write(codec, msbreg, outp >> 8);
240 aic3x_write(codec, msbreg+1, outp);
247 * read from the aic3x register space
249 static int aic3x_read(struct snd_soc_codec *codec, unsigned int reg,
254 /* No read access is recommended if the chip is reset after use */
255 printk(KERN_ERR "%s(): Values are may be incorrect!\n", __func__);
257 if (codec->hw_read(codec->control_data, value, 1) != 1)
260 aic3x_write_reg_cache(codec, reg, *value);
264 static int aic3x_sync_hw(struct snd_soc_codec *codec)
266 u8 *cache = codec->reg_cache;
270 aic3x_write(codec, AIC3X_PAGE_SELECT, 1);
271 /*mutex_lock(&codec->mutex);*/
272 for (i = 1; i < AIC3X_PAGE1REGNUM; i++) {
274 data[1] = cache[i+128];
275 codec->hw_write(codec->control_data, data, 2);
277 /*mutex_unlock(&codec->mutex);*/
279 /* We do not rewrite page select nor reset again */
280 aic3x_write(codec, AIC3X_PAGE_SELECT, 0);
281 /*mutex_lock(&codec->mutex);*/
282 for (i = 2; i < AIC3X_PAGE0REGNUM; i++) {
285 codec->hw_write(codec->control_data, data, 2);
287 /*mutex_unlock(&codec->mutex);*/
293 * Reset for getting low power consumption after bypass paths
295 static void aic3x_reset(struct snd_soc_codec *codec)
297 aic3x_write(codec, AIC3X_RESET, SOFT_RESET);
298 aic3x_sync_hw(codec);
301 #define SOC_DAPM_SINGLE_AIC3X(xname, reg, shift, mask, invert) \
302 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
303 .info = snd_soc_info_volsw, \
304 .get = snd_soc_dapm_get_volsw, .put = snd_soc_dapm_put_volsw_aic3x, \
305 .private_value = SOC_SINGLE_VALUE(reg, shift, mask, invert) }
308 * All input lines are connected when !0xf and disconnected with 0xf bit field,
309 * so we have to use specific dapm_put call for input mixer
311 static int snd_soc_dapm_put_volsw_aic3x(struct snd_kcontrol *kcontrol,
312 struct snd_ctl_elem_value *ucontrol)
314 struct snd_soc_dapm_widget *widget = snd_kcontrol_chip(kcontrol);
315 struct soc_mixer_control *mc =
316 (struct soc_mixer_control *)kcontrol->private_value;
317 unsigned int reg = mc->reg;
318 unsigned int shift = mc->shift;
320 unsigned int mask = (1 << fls(max)) - 1;
321 unsigned int invert = mc->invert;
322 unsigned short val, val_mask;
324 struct snd_soc_dapm_path *path;
327 val = (ucontrol->value.integer.value[0] & mask);
335 val_mask = mask << shift;
338 mutex_lock(&widget->codec->mutex);
340 if (snd_soc_test_bits(widget->codec, reg, val_mask, val)) {
341 /* find dapm widget path assoc with kcontrol */
342 list_for_each_entry(path, &widget->codec->dapm_paths, list) {
343 if (path->kcontrol != kcontrol)
346 /* found, now check type */
350 path->connect = invert ? 0 : 1;
352 /* old connection must be powered down */
353 path->connect = invert ? 1 : 0;
358 snd_soc_dapm_sync(widget->codec);
361 ret = snd_soc_update_bits(widget->codec, reg, val_mask, val);
363 mutex_unlock(&widget->codec->mutex);
367 static const char *aic3x_left_dac_mux[] = { "DAC_L1", "DAC_L3", "DAC_L2" };
368 static const char *aic3x_right_dac_mux[] = { "DAC_R1", "DAC_R3", "DAC_R2" };
369 static const char *aic3x_left_hpcom_mux[] =
370 { "differential of HPLOUT", "constant VCM", "single-ended" };
371 static const char *aic3x_right_hpcom_mux[] =
372 { "differential of HPROUT", "constant VCM", "single-ended",
373 "differential of HPLCOM", "external feedback" };
374 static const char *aic3x_linein_mode_mux[] = { "single-ended", "differential" };
375 static const char *aic3x_adc_hpf[] =
376 { "Disabled", "0.0045xFs", "0.0125xFs", "0.025xFs" };
377 static const char *aic3x_dac_filt[] =
378 { "Off", "Bass/Treble", "Custom" };
382 #define LHPCOM_ENUM 2
383 #define RHPCOM_ENUM 3
384 #define LINE1L_ENUM 4
385 #define LINE1R_ENUM 5
386 #define LINE2L_ENUM 6
387 #define LINE2R_ENUM 7
388 #define ADC_HPF_ENUM 8
389 #define DAC_FILT_ENUM 9
391 static const struct soc_enum aic3x_enum[] = {
392 SOC_ENUM_SINGLE(DAC_LINE_MUX, 6, 3, aic3x_left_dac_mux),
393 SOC_ENUM_SINGLE(DAC_LINE_MUX, 4, 3, aic3x_right_dac_mux),
394 SOC_ENUM_SINGLE(HPLCOM_CFG, 4, 3, aic3x_left_hpcom_mux),
395 SOC_ENUM_SINGLE(HPRCOM_CFG, 3, 5, aic3x_right_hpcom_mux),
396 SOC_ENUM_SINGLE(LINE1L_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux),
397 SOC_ENUM_SINGLE(LINE1R_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux),
398 SOC_ENUM_SINGLE(LINE2L_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux),
399 SOC_ENUM_SINGLE(LINE2R_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux),
400 SOC_ENUM_DOUBLE(AIC3X_CODEC_DFILT_CTRL, 6, 4, 4, aic3x_adc_hpf),
401 SOC_ENUM_DOUBLE(AIC3X_CODEC_DFILT_CTRL, 1, 3, 3, aic3x_dac_filt),
405 * DAC digital volumes. From -63.5 to 0 dB in 0.5 dB steps
407 static DECLARE_TLV_DB_SCALE(dac_tlv, -6350, 50, 0);
408 /* ADC PGA gain volumes. From 0 to 59.5 dB in 0.5 dB steps */
409 static DECLARE_TLV_DB_SCALE(adc_tlv, 0, 50, 0);
410 /* HP DAC Output gain values. From 0 to 9.0 dB in 1 dB steps */
411 static DECLARE_TLV_DB_SCALE(hpout_tlv, 0, 100, 0);
413 * Output stage volumes. From -78.3 to 0 dB. Muted below -78.3 dB.
414 * Step size is approximately 0.5 dB over most of the scale but increasing
415 * near the very low levels.
416 * Define dB scale so that it is mostly correct for range about -55 to 0 dB
417 * but having increasing dB difference below that (and where it doesn't count
418 * so much). This setting shows -50 dB (actual is -50.3 dB) for register
419 * value 100 and -58.5 dB (actual is -78.3 dB) for register value 117.
421 static DECLARE_TLV_DB_SCALE(output_stage_tlv, -5900, 50, 1);
423 #define SOC_DOUBLE_R_TLV_TLV320ALC3X(xname, reg_left, reg_right, xshift, xmax,\
424 xinvert, tlv_array) \
425 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
426 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
427 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
428 .tlv.p = (tlv_array), \
429 .info = tlv320alc3x_info_volsw, \
430 .get = snd_soc_get_volsw_2r,\
431 .put = snd_soc_put_volsw_2r,\
432 .private_value = (unsigned long)&(struct soc_mixer_control) \
433 {.reg = reg_left, .rreg = reg_right, .shift = xshift, \
434 .max = xmax, .invert = xinvert} }
436 static int tlv320alc3x_info_volsw(struct snd_kcontrol *kcontrol,
437 struct snd_ctl_elem_info *uinfo)
439 struct soc_mixer_control *mc =
440 (struct soc_mixer_control *)kcontrol->private_value;
443 if (hp_dac_lim != max && hp_dac_lim >= 2 && hp_dac_lim <= 9)
447 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
449 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
452 uinfo->value.integer.min = 0;
453 uinfo->value.integer.max = max;
457 /* DAC Filter Functions */
459 static int aic3x_dacfilter_write_coeffs
460 (struct snd_soc_codec *codec, struct aic3x_iir_coeffs *coeffs)
462 struct aic3x_priv *aic3x = codec->private_data;
463 printk("MNZ: dacfilter_write_coeffs\n");
464 snd_soc_update_bits(codec, AIC3X_CODEC_DFILT_CTRL, EFFECTS_ON, 0);
465 aic3x_write_coeff(codec, EFFECTS_LEFT_N0, coeffs->N0);
466 aic3x_write_coeff(codec, EFFECTS_LEFT_N1, coeffs->N1);
467 aic3x_write_coeff(codec, EFFECTS_LEFT_N2, coeffs->N2);
468 aic3x_write_coeff(codec, EFFECTS_LEFT_D1, coeffs->D1);
469 aic3x_write_coeff(codec, EFFECTS_LEFT_D2, coeffs->D2);
470 aic3x_write_coeff(codec, EFFECTS_LEFT_N3, coeffs->N3);
471 aic3x_write_coeff(codec, EFFECTS_LEFT_N4, coeffs->N4);
472 aic3x_write_coeff(codec, EFFECTS_LEFT_N5, coeffs->N5);
473 aic3x_write_coeff(codec, EFFECTS_LEFT_D4, coeffs->D4);
474 aic3x_write_coeff(codec, EFFECTS_LEFT_D5, coeffs->D5);
476 aic3x_write_coeff(codec, EFFECTS_RIGHT_N0, coeffs->N0);
477 aic3x_write_coeff(codec, EFFECTS_RIGHT_N1, coeffs->N1);
478 aic3x_write_coeff(codec, EFFECTS_RIGHT_N2, coeffs->N2);
479 aic3x_write_coeff(codec, EFFECTS_RIGHT_D1, coeffs->D1);
480 aic3x_write_coeff(codec, EFFECTS_RIGHT_D2, coeffs->D2);
481 aic3x_write_coeff(codec, EFFECTS_RIGHT_N3, coeffs->N3);
482 aic3x_write_coeff(codec, EFFECTS_RIGHT_N4, coeffs->N4);
483 aic3x_write_coeff(codec, EFFECTS_RIGHT_N5, coeffs->N5);
484 aic3x_write_coeff(codec, EFFECTS_RIGHT_D4, coeffs->D4);
485 aic3x_write_coeff(codec, EFFECTS_RIGHT_D5, coeffs->D5);
487 snd_soc_update_bits(codec, AIC3X_CODEC_DFILT_CTRL, EFFECTS_ON, EFFECTS_ON);
489 memcpy((void*)&aic3x->dacfilter.coeffs, (void*)coeffs,
490 sizeof(struct aic3x_iir_coeffs));
494 static int aic3x_dacfilter_set_state(struct snd_soc_codec *codec,
497 struct aic3x_priv *aic3x = codec->private_data;
499 if(aic3x->dacfilter.state == state) return 0;
501 aic3x->dacfilter.state = state;
504 snd_soc_update_bits(codec, AIC3X_CODEC_DFILT_CTRL,
506 else if(state == 1) {}
507 /* FIXME MNZ. Set preset from current chosen preset */
509 return aic3x_dacfilter_write_coeffs(codec,
510 &aic3x->dacfilter.coeffs);
514 /* DAC Filter hwdep device callbacks */
516 static int snd_hwdep_dacfilter_open_aic3x(struct snd_hwdep *hw,
522 static int snd_hwdep_dacfilter_ioctl_aic3x(struct snd_hwdep *hw,
523 struct file *file, unsigned int cmd, unsigned long arg)
525 /* Only IOCTL command is for enabling/disabling filter, cmd = 1
526 * arg = 0 to disable, 1 to enable and set to bass/treble,
527 * 2 to enable and set to custom coeffs
529 struct snd_soc_codec *codec = hw->private_data;
530 if (cmd != 1) return -EINVAL;
531 return aic3x_dacfilter_set_state(codec, *((int*)arg));
535 static long snd_hwdep_dacfilter_read_aic3x(struct snd_hwdep *hw,
536 char __user *buf, long count, loff_t *offset)
538 struct aic3x_priv *aic3x =
539 ((struct snd_soc_codec*)hw->private_data)->private_data;
540 if(count != sizeof(struct aic3x_iir_coeffs)) return -EINVAL;
541 memcpy((void*)buf, (void*)&aic3x->dacfilter.coeffs, count);
545 static long snd_hwdep_dacfilter_write_aic3x(struct snd_hwdep *hw,
546 const char __user *buf, long count, loff_t *offset)
548 struct snd_soc_codec *codec = hw->private_data;
549 if(count != sizeof(struct aic3x_iir_coeffs)) return -EINVAL;
551 ((struct aic3x_priv*)codec->private_data)->dacfilter.state = 2;
553 return aic3x_dacfilter_write_coeffs(codec,
554 (struct aic3x_iir_coeffs*)buf);
557 /* DAC filter and 3D depth alsa controls callbacks */
559 static int snd_soc_get_dacfilter_aic3x(struct snd_kcontrol *kcontrol,
560 struct snd_ctl_elem_value *ucontrol)
562 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
563 ucontrol->value.enumerated.item[0] =
564 ((struct aic3x_priv*)codec->private_data)->dacfilter.state;
568 static int snd_soc_put_dacfilter_aic3x(struct snd_kcontrol *kcontrol,
569 struct snd_ctl_elem_value *ucontrol)
571 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
572 if (ucontrol->value.enumerated.item[0] > 2)
574 aic3x_dacfilter_set_state(codec, ucontrol->value.enumerated.item[0]);
578 static int snd_soc_get_3d_attenuation_aic3x
579 (struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
581 int val = aic3x_read_coeff_reg_cache
582 (snd_kcontrol_chip(kcontrol), EFFECTS_3DATTEN);
583 val = ((val*100)/65530) + 50;
584 ucontrol->value.integer.value[0] = val;
588 static int snd_soc_put_3d_attenuation_aic3x
589 (struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
591 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
592 int val = ucontrol->value.integer.value[0];
593 if(val > 100 || val < 0) return -EINVAL;
596 snd_soc_update_bits(codec, AIC3X_ASD_INTF_CTRLA,
597 EFFECTS_3D_ON, EFFECTS_3D_ON);
598 val = ((val - 50) * 65535) / 100 ;
600 snd_soc_update_bits(codec, AIC3X_ASD_INTF_CTRLA,
605 aic3x_write_coeff(codec, EFFECTS_3DATTEN, val);
610 static const struct snd_kcontrol_new aic3x_snd_controls[] = {
612 SOC_DOUBLE_R_TLV("PCM Playback Volume",
613 LDAC_VOL, RDAC_VOL, 0, 0x7f, 1, dac_tlv),
615 SOC_DOUBLE_R_TLV("Line DAC Playback Volume",
616 DACL1_2_LLOPM_VOL, DACR1_2_RLOPM_VOL,
617 0, 118, 1, output_stage_tlv),
618 SOC_DOUBLE_R("Line DAC Playback Switch", LLOPM_CTRL, RLOPM_CTRL, 3,
620 SOC_DOUBLE_R_TLV("Line PGA Bypass Playback Volume",
621 PGAL_2_LLOPM_VOL, PGAR_2_RLOPM_VOL,
622 0, 118, 1, output_stage_tlv),
623 SOC_DOUBLE_R_TLV("Line Line2 Bypass Playback Volume",
624 LINE2L_2_LLOPM_VOL, LINE2R_2_RLOPM_VOL,
625 0, 118, 1, output_stage_tlv),
627 SOC_DOUBLE_R_TLV("Mono DAC Playback Volume",
628 DACL1_2_MONOLOPM_VOL, DACR1_2_MONOLOPM_VOL,
629 0, 118, 1, output_stage_tlv),
630 SOC_SINGLE("Mono DAC Playback Switch", MONOLOPM_CTRL, 3, 0x01, 0),
631 SOC_DOUBLE_R_TLV("Mono PGA Bypass Playback Volume",
632 PGAL_2_MONOLOPM_VOL, PGAR_2_MONOLOPM_VOL,
633 0, 118, 1, output_stage_tlv),
634 SOC_DOUBLE_R_TLV("Mono Line2 Bypass Playback Volume",
635 LINE2L_2_MONOLOPM_VOL, LINE2R_2_MONOLOPM_VOL,
636 0, 118, 1, output_stage_tlv),
638 SOC_DOUBLE_R_TLV("HP DAC Playback Volume",
639 DACL1_2_HPLOUT_VOL, DACR1_2_HPROUT_VOL,
640 0, 118, 1, output_stage_tlv),
641 SOC_DOUBLE_R("HP DAC Playback Switch", HPLOUT_CTRL, HPROUT_CTRL, 3,
643 SOC_DOUBLE_R_TLV_TLV320ALC3X("HP DAC Output Volume", HPLOUT_CTRL,
644 HPROUT_CTRL, 4, 9, 0, hpout_tlv),
645 SOC_DOUBLE_R_TLV("HP PGA Bypass Playback Volume",
646 PGAL_2_HPLOUT_VOL, PGAR_2_HPROUT_VOL,
647 0, 118, 1, output_stage_tlv),
648 SOC_DOUBLE_R_TLV("HP Line2 Bypass Playback Volume",
649 LINE2L_2_HPLOUT_VOL, LINE2R_2_HPROUT_VOL,
650 0, 118, 1, output_stage_tlv),
652 SOC_DOUBLE_R_TLV("HPCOM DAC Playback Volume",
653 DACL1_2_HPLCOM_VOL, DACR1_2_HPRCOM_VOL,
654 0, 118, 1, output_stage_tlv),
655 SOC_DOUBLE_R("HPCOM DAC Playback Switch", HPLCOM_CTRL, HPRCOM_CTRL, 3,
657 SOC_DOUBLE_R_TLV_TLV320ALC3X("HPCOM DAC Output Volume", HPLCOM_CTRL,
658 HPRCOM_CTRL, 4, 9, 0, hpout_tlv),
659 SOC_DOUBLE_R_TLV("HPCOM PGA Bypass Playback Volume",
660 PGAL_2_HPLCOM_VOL, PGAR_2_HPRCOM_VOL,
661 0, 118, 1, output_stage_tlv),
662 SOC_DOUBLE_R_TLV("HPCOM Line2 Bypass Playback Volume",
663 LINE2L_2_HPLCOM_VOL, LINE2R_2_HPRCOM_VOL,
664 0, 118, 1, output_stage_tlv),
667 * Note: enable Automatic input Gain Controller with care. It can
668 * adjust PGA to max value when ADC is on and will never go back.
670 SOC_DOUBLE_R("AGC Switch", LAGC_CTRL_A, RAGC_CTRL_A, 7, 0x01, 0),
673 SOC_DOUBLE_R_TLV("PGA Capture Volume", LADC_VOL, RADC_VOL,
675 SOC_DOUBLE_R("PGA Capture Switch", LADC_VOL, RADC_VOL, 7, 0x01, 1),
677 SOC_ENUM("ADC HPF Cut-off", aic3x_enum[ADC_HPF_ENUM]),
679 SOC_ENUM_EXT("Hardware EQ", aic3x_enum[DAC_FILT_ENUM],
680 snd_soc_get_dacfilter_aic3x, snd_soc_put_dacfilter_aic3x),
682 SOC_SINGLE_EXT("3D Control - Depth", EFFECTS_3DATTEN, 0, 100, 0,
683 snd_soc_get_3d_attenuation_aic3x, snd_soc_put_3d_attenuation_aic3x),
686 /* add non dapm controls */
687 static int aic3x_add_controls(struct snd_soc_codec *codec)
691 for (i = 0; i < ARRAY_SIZE(aic3x_snd_controls); i++) {
692 err = snd_ctl_add(codec->card,
693 snd_soc_cnew(&aic3x_snd_controls[i],
702 static int reset_after_bypass(struct snd_soc_dapm_widget *w,
703 struct snd_kcontrol *kcontrol, int event)
705 struct aic3x_priv *aic3x = w->codec->private_data;
706 struct soc_mixer_control *mc = NULL;
707 unsigned int reg = 0;
710 mc = (struct soc_mixer_control *)kcontrol->private_value;
714 if (reg == PGAL_2_LLOPM_VOL || reg == PGAR_2_RLOPM_VOL ||
715 reg == PGAL_2_HPLOUT_VOL || reg == PGAR_2_HPROUT_VOL) {
716 if (w->value & 0x80) {
717 /* Prepare reset on the chip */
718 if (reg == PGAL_2_LLOPM_VOL)
719 aic3x->prepare_reset |= 0x01;
720 else if (reg == PGAR_2_RLOPM_VOL)
721 aic3x->prepare_reset |= 0x02;
722 else if (reg == PGAL_2_HPLOUT_VOL)
723 aic3x->prepare_reset |= 0x04;
724 else if (reg == PGAR_2_HPROUT_VOL)
725 aic3x->prepare_reset |= 0x08;
727 if (aic3x->prepare_reset) {
728 if (reg == PGAL_2_LLOPM_VOL)
729 aic3x->prepare_reset &= ~0x01;
730 else if (reg == PGAR_2_RLOPM_VOL)
731 aic3x->prepare_reset &= ~0x02;
732 else if (reg == PGAL_2_HPLOUT_VOL)
733 aic3x->prepare_reset &= ~0x04;
734 else if (reg == PGAR_2_HPROUT_VOL)
735 aic3x->prepare_reset &= ~0x08;
737 * Controls may have now been turned off,
738 * once they were on, so schedule or
739 * issue a reset on the chip.
741 if (!aic3x->prepare_reset) {
742 if (!((w->codec->bias_level ==
744 (w->codec->bias_level ==
745 SND_SOC_BIAS_PREPARE)))
746 aic3x_reset(w->codec);
756 static const struct snd_kcontrol_new aic3x_left_dac_mux_controls =
757 SOC_DAPM_ENUM("Route", aic3x_enum[LDAC_ENUM]);
760 static const struct snd_kcontrol_new aic3x_right_dac_mux_controls =
761 SOC_DAPM_ENUM("Route", aic3x_enum[RDAC_ENUM]);
764 static const struct snd_kcontrol_new aic3x_left_hpcom_mux_controls =
765 SOC_DAPM_ENUM("Route", aic3x_enum[LHPCOM_ENUM]);
767 /* Right HPCOM Mux */
768 static const struct snd_kcontrol_new aic3x_right_hpcom_mux_controls =
769 SOC_DAPM_ENUM("Route", aic3x_enum[RHPCOM_ENUM]);
771 /* Left DAC_L1 Mixer */
772 static const struct snd_kcontrol_new aic3x_left_dac_mixer_controls[] = {
773 SOC_DAPM_SINGLE("Line Switch", DACL1_2_LLOPM_VOL, 7, 1, 0),
774 SOC_DAPM_SINGLE("Mono Switch", DACL1_2_MONOLOPM_VOL, 7, 1, 0),
775 SOC_DAPM_SINGLE("HP Switch", DACL1_2_HPLOUT_VOL, 7, 1, 0),
776 SOC_DAPM_SINGLE("HPCOM Switch", DACL1_2_HPLCOM_VOL, 7, 1, 0),
779 /* Right DAC_R1 Mixer */
780 static const struct snd_kcontrol_new aic3x_right_dac_mixer_controls[] = {
781 SOC_DAPM_SINGLE("Line Switch", DACR1_2_RLOPM_VOL, 7, 1, 0),
782 SOC_DAPM_SINGLE("Mono Switch", DACR1_2_MONOLOPM_VOL, 7, 1, 0),
783 SOC_DAPM_SINGLE("HP Switch", DACR1_2_HPROUT_VOL, 7, 1, 0),
784 SOC_DAPM_SINGLE("HPCOM Switch", DACR1_2_HPRCOM_VOL, 7, 1, 0),
788 static const struct snd_kcontrol_new aic3x_left_pga_mixer_controls[] = {
789 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_LADC_CTRL, 3, 1, 1),
790 SOC_DAPM_SINGLE_AIC3X("Line2L Switch", LINE2L_2_LADC_CTRL, 3, 1, 1),
791 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_LADC_CTRL, 4, 1, 1),
794 /* Right PGA Mixer */
795 static const struct snd_kcontrol_new aic3x_right_pga_mixer_controls[] = {
796 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_RADC_CTRL, 3, 1, 1),
797 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_RADC_CTRL, 3, 1, 1),
798 SOC_DAPM_SINGLE_AIC3X("Line2R Switch", LINE2R_2_RADC_CTRL, 3, 1, 1),
799 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_RADC_CTRL, 0, 1, 1),
803 static const struct snd_kcontrol_new aic3x_left_line1_mux_controls =
804 SOC_DAPM_ENUM("Route", aic3x_enum[LINE1L_ENUM]);
806 /* Right Line1 Mux */
807 static const struct snd_kcontrol_new aic3x_right_line1_mux_controls =
808 SOC_DAPM_ENUM("Route", aic3x_enum[LINE1R_ENUM]);
811 static const struct snd_kcontrol_new aic3x_left_line2_mux_controls =
812 SOC_DAPM_ENUM("Route", aic3x_enum[LINE2L_ENUM]);
814 /* Right Line2 Mux */
815 static const struct snd_kcontrol_new aic3x_right_line2_mux_controls =
816 SOC_DAPM_ENUM("Route", aic3x_enum[LINE2R_ENUM]);
818 /* Left PGA Bypass Mixer */
819 static const struct snd_kcontrol_new aic3x_left_pga_bp_mixer_controls[] = {
820 SOC_DAPM_SINGLE("Line Switch", PGAL_2_LLOPM_VOL, 7, 1, 0),
821 SOC_DAPM_SINGLE("Mono Switch", PGAL_2_MONOLOPM_VOL, 7, 1, 0),
822 SOC_DAPM_SINGLE("HP Switch", PGAL_2_HPLOUT_VOL, 7, 1, 0),
823 SOC_DAPM_SINGLE("HPCOM Switch", PGAL_2_HPLCOM_VOL, 7, 1, 0),
826 /* Right PGA Bypass Mixer */
827 static const struct snd_kcontrol_new aic3x_right_pga_bp_mixer_controls[] = {
828 SOC_DAPM_SINGLE("Line Switch", PGAR_2_RLOPM_VOL, 7, 1, 0),
829 SOC_DAPM_SINGLE("Mono Switch", PGAR_2_MONOLOPM_VOL, 7, 1, 0),
830 SOC_DAPM_SINGLE("HP Switch", PGAR_2_HPROUT_VOL, 7, 1, 0),
831 SOC_DAPM_SINGLE("HPCOM Switch", PGAR_2_HPRCOM_VOL, 7, 1, 0),
834 /* Left Line2 Bypass Mixer */
835 static const struct snd_kcontrol_new aic3x_left_line2_bp_mixer_controls[] = {
836 SOC_DAPM_SINGLE("Line Switch", LINE2L_2_LLOPM_VOL, 7, 1, 0),
837 SOC_DAPM_SINGLE("Mono Switch", LINE2L_2_MONOLOPM_VOL, 7, 1, 0),
838 SOC_DAPM_SINGLE("HP Switch", LINE2L_2_HPLOUT_VOL, 7, 1, 0),
839 SOC_DAPM_SINGLE("HPCOM Switch", LINE2L_2_HPLCOM_VOL, 7, 1, 0),
842 /* Right Line2 Bypass Mixer */
843 static const struct snd_kcontrol_new aic3x_right_line2_bp_mixer_controls[] = {
844 SOC_DAPM_SINGLE("Line Switch", LINE2R_2_RLOPM_VOL, 7, 1, 0),
845 SOC_DAPM_SINGLE("Mono Switch", LINE2R_2_MONOLOPM_VOL, 7, 1, 0),
846 SOC_DAPM_SINGLE("HP Switch", LINE2R_2_HPROUT_VOL, 7, 1, 0),
847 SOC_DAPM_SINGLE("HPCOM Switch", LINE2R_2_HPRCOM_VOL, 7, 1, 0),
850 static const struct snd_soc_dapm_widget aic3x_dapm_widgets[] = {
851 /* Left DAC to Left Outputs */
852 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", DAC_PWR, 7, 0),
853 SND_SOC_DAPM_MUX("Left DAC Mux", SND_SOC_NOPM, 0, 0,
854 &aic3x_left_dac_mux_controls),
855 SND_SOC_DAPM_MIXER("Left DAC_L1 Mixer", SND_SOC_NOPM, 0, 0,
856 &aic3x_left_dac_mixer_controls[0],
857 ARRAY_SIZE(aic3x_left_dac_mixer_controls)),
858 SND_SOC_DAPM_MUX("Left HPCOM Mux", SND_SOC_NOPM, 0, 0,
859 &aic3x_left_hpcom_mux_controls),
860 SND_SOC_DAPM_PGA("Left Line Out", LLOPM_CTRL, 0, 0, NULL, 0),
861 SND_SOC_DAPM_PGA("Left HP Out", HPLOUT_CTRL, 0, 0, NULL, 0),
862 SND_SOC_DAPM_PGA("Left HP Com", HPLCOM_CTRL, 0, 0, NULL, 0),
864 /* Right DAC to Right Outputs */
865 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", DAC_PWR, 6, 0),
866 SND_SOC_DAPM_MUX("Right DAC Mux", SND_SOC_NOPM, 0, 0,
867 &aic3x_right_dac_mux_controls),
868 SND_SOC_DAPM_MIXER("Right DAC_R1 Mixer", SND_SOC_NOPM, 0, 0,
869 &aic3x_right_dac_mixer_controls[0],
870 ARRAY_SIZE(aic3x_right_dac_mixer_controls)),
871 SND_SOC_DAPM_MUX("Right HPCOM Mux", SND_SOC_NOPM, 0, 0,
872 &aic3x_right_hpcom_mux_controls),
873 SND_SOC_DAPM_PGA("Right Line Out", RLOPM_CTRL, 0, 0, NULL, 0),
874 SND_SOC_DAPM_PGA("Right HP Out", HPROUT_CTRL, 0, 0, NULL, 0),
875 SND_SOC_DAPM_PGA("Right HP Com", HPRCOM_CTRL, 0, 0, NULL, 0),
878 SND_SOC_DAPM_PGA("Mono Out", MONOLOPM_CTRL, 0, 0, NULL, 0),
880 /* Left Inputs to Left ADC */
881 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", LINE1L_2_LADC_CTRL, 2, 0),
882 SND_SOC_DAPM_MIXER("Left PGA Mixer", SND_SOC_NOPM, 0, 0,
883 &aic3x_left_pga_mixer_controls[0],
884 ARRAY_SIZE(aic3x_left_pga_mixer_controls)),
885 SND_SOC_DAPM_MUX("Left Line1L Mux", SND_SOC_NOPM, 0, 0,
886 &aic3x_left_line1_mux_controls),
887 SND_SOC_DAPM_MUX("Left Line2L Mux", SND_SOC_NOPM, 0, 0,
888 &aic3x_left_line2_mux_controls),
890 /* Right Inputs to Right ADC */
891 SND_SOC_DAPM_ADC("Right ADC", "Right Capture",
892 LINE1R_2_RADC_CTRL, 2, 0),
893 SND_SOC_DAPM_MIXER("Right PGA Mixer", SND_SOC_NOPM, 0, 0,
894 &aic3x_right_pga_mixer_controls[0],
895 ARRAY_SIZE(aic3x_right_pga_mixer_controls)),
896 SND_SOC_DAPM_MUX("Right Line1L Mux", SND_SOC_NOPM, 0, 0,
897 &aic3x_right_line1_mux_controls),
898 SND_SOC_DAPM_MUX("Right Line1R Mux", SND_SOC_NOPM, 0, 0,
899 &aic3x_right_line1_mux_controls),
900 SND_SOC_DAPM_MUX("Right Line2R Mux", SND_SOC_NOPM, 0, 0,
901 &aic3x_right_line2_mux_controls),
904 * Not a real mic bias widget but similar function. This is for dynamic
905 * control of GPIO1 digital mic modulator clock output function when
908 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "GPIO1 dmic modclk",
909 AIC3X_GPIO1_REG, 4, 0xf,
910 AIC3X_GPIO1_FUNC_DIGITAL_MIC_MODCLK,
911 AIC3X_GPIO1_FUNC_DISABLED),
914 * Also similar function like mic bias. Selects digital mic with
915 * configurable oversampling rate instead of ADC converter.
917 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 128",
918 AIC3X_ASD_INTF_CTRLA, 0, 3, 1, 0),
919 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 64",
920 AIC3X_ASD_INTF_CTRLA, 0, 3, 2, 0),
921 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 32",
922 AIC3X_ASD_INTF_CTRLA, 0, 3, 3, 0),
925 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias 2V",
926 MICBIAS_CTRL, 6, 3, 1, 0),
927 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias 2.5V",
928 MICBIAS_CTRL, 6, 3, 2, 0),
929 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias AVDD",
930 MICBIAS_CTRL, 6, 3, 3, 0),
932 /* Left PGA to Left Output bypass */
933 SND_SOC_DAPM_MIXER_E("Left PGA Bypass Mixer", SND_SOC_NOPM, 0, 0,
934 &aic3x_left_pga_bp_mixer_controls[0],
935 ARRAY_SIZE(aic3x_left_pga_bp_mixer_controls),
936 reset_after_bypass, SND_SOC_DAPM_POST_REG),
938 /* Right PGA to Right Output bypass */
939 SND_SOC_DAPM_MIXER_E("Right PGA Bypass Mixer", SND_SOC_NOPM, 0, 0,
940 &aic3x_right_pga_bp_mixer_controls[0],
941 ARRAY_SIZE(aic3x_right_pga_bp_mixer_controls),
942 reset_after_bypass, SND_SOC_DAPM_POST_REG),
944 /* Left Line2 to Left Output bypass */
945 SND_SOC_DAPM_MIXER("Left Line2 Bypass Mixer", SND_SOC_NOPM, 0, 0,
946 &aic3x_left_line2_bp_mixer_controls[0],
947 ARRAY_SIZE(aic3x_left_line2_bp_mixer_controls)),
949 /* Right Line2 to Right Output bypass */
950 SND_SOC_DAPM_MIXER("Right Line2 Bypass Mixer", SND_SOC_NOPM, 0, 0,
951 &aic3x_right_line2_bp_mixer_controls[0],
952 ARRAY_SIZE(aic3x_right_line2_bp_mixer_controls)),
954 SND_SOC_DAPM_OUTPUT("LLOUT"),
955 SND_SOC_DAPM_OUTPUT("RLOUT"),
956 SND_SOC_DAPM_OUTPUT("MONO_LOUT"),
957 SND_SOC_DAPM_OUTPUT("HPLOUT"),
958 SND_SOC_DAPM_OUTPUT("HPROUT"),
959 SND_SOC_DAPM_OUTPUT("HPLCOM"),
960 SND_SOC_DAPM_OUTPUT("HPRCOM"),
962 SND_SOC_DAPM_INPUT("MIC3L"),
963 SND_SOC_DAPM_INPUT("MIC3R"),
964 SND_SOC_DAPM_INPUT("LINE1L"),
965 SND_SOC_DAPM_INPUT("LINE1R"),
966 SND_SOC_DAPM_INPUT("LINE2L"),
967 SND_SOC_DAPM_INPUT("LINE2R"),
970 static const struct snd_soc_dapm_route intercon[] = {
972 {"Left DAC Mux", "DAC_L1", "Left DAC"},
973 {"Left DAC Mux", "DAC_L2", "Left DAC"},
974 {"Left DAC Mux", "DAC_L3", "Left DAC"},
976 {"Left DAC_L1 Mixer", "Line Switch", "Left DAC Mux"},
977 {"Left DAC_L1 Mixer", "Mono Switch", "Left DAC Mux"},
978 {"Left DAC_L1 Mixer", "HP Switch", "Left DAC Mux"},
979 {"Left DAC_L1 Mixer", "HPCOM Switch", "Left DAC Mux"},
980 {"Left Line Out", NULL, "Left DAC Mux"},
981 {"Left HP Out", NULL, "Left DAC Mux"},
983 {"Left HPCOM Mux", "differential of HPLOUT", "Left DAC_L1 Mixer"},
984 {"Left HPCOM Mux", "constant VCM", "Left DAC_L1 Mixer"},
985 {"Left HPCOM Mux", "single-ended", "Left DAC_L1 Mixer"},
987 {"Left Line Out", NULL, "Left DAC_L1 Mixer"},
988 {"Mono Out", NULL, "Left DAC_L1 Mixer"},
989 {"Left HP Out", NULL, "Left DAC_L1 Mixer"},
990 {"Left HP Com", NULL, "Left HPCOM Mux"},
992 {"LLOUT", NULL, "Left Line Out"},
993 {"LLOUT", NULL, "Left Line Out"},
994 {"HPLOUT", NULL, "Left HP Out"},
995 {"HPLCOM", NULL, "Left HP Com"},
998 {"Right DAC Mux", "DAC_R1", "Right DAC"},
999 {"Right DAC Mux", "DAC_R2", "Right DAC"},
1000 {"Right DAC Mux", "DAC_R3", "Right DAC"},
1002 {"Right DAC_R1 Mixer", "Line Switch", "Right DAC Mux"},
1003 {"Right DAC_R1 Mixer", "Mono Switch", "Right DAC Mux"},
1004 {"Right DAC_R1 Mixer", "HP Switch", "Right DAC Mux"},
1005 {"Right DAC_R1 Mixer", "HPCOM Switch", "Right DAC Mux"},
1006 {"Right Line Out", NULL, "Right DAC Mux"},
1007 {"Right HP Out", NULL, "Right DAC Mux"},
1009 {"Right HPCOM Mux", "differential of HPROUT", "Right DAC_R1 Mixer"},
1010 {"Right HPCOM Mux", "constant VCM", "Right DAC_R1 Mixer"},
1011 {"Right HPCOM Mux", "single-ended", "Right DAC_R1 Mixer"},
1012 {"Right HPCOM Mux", "differential of HPLCOM", "Right DAC_R1 Mixer"},
1013 {"Right HPCOM Mux", "external feedback", "Right DAC_R1 Mixer"},
1015 {"Right Line Out", NULL, "Right DAC_R1 Mixer"},
1016 {"Mono Out", NULL, "Right DAC_R1 Mixer"},
1017 {"Right HP Out", NULL, "Right DAC_R1 Mixer"},
1018 {"Right HP Com", NULL, "Right HPCOM Mux"},
1020 {"RLOUT", NULL, "Right Line Out"},
1021 {"RLOUT", NULL, "Right Line Out"},
1022 {"HPROUT", NULL, "Right HP Out"},
1023 {"HPRCOM", NULL, "Right HP Com"},
1026 {"MONO_LOUT", NULL, "Mono Out"},
1027 {"MONO_LOUT", NULL, "Mono Out"},
1030 {"Left Line1L Mux", "single-ended", "LINE1L"},
1031 {"Left Line1L Mux", "differential", "LINE1L"},
1033 {"Left Line2L Mux", "single-ended", "LINE2L"},
1034 {"Left Line2L Mux", "differential", "LINE2L"},
1036 {"Left PGA Mixer", "Line1L Switch", "Left Line1L Mux"},
1037 {"Left PGA Mixer", "Line2L Switch", "Left Line2L Mux"},
1038 {"Left PGA Mixer", "Mic3L Switch", "MIC3L"},
1040 {"Left ADC", NULL, "Left PGA Mixer"},
1041 {"Left ADC", NULL, "GPIO1 dmic modclk"},
1044 {"Right Line1L Mux", "single-ended", "LINE1L"},
1045 {"Right Line1L Mux", "differential", "LINE1L"},
1047 {"Right Line1R Mux", "single-ended", "LINE1R"},
1048 {"Right Line1R Mux", "differential", "LINE1R"},
1050 {"Right Line2R Mux", "single-ended", "LINE2R"},
1051 {"Right Line2R Mux", "differential", "LINE2R"},
1053 {"Right PGA Mixer", "Line1L Switch", "Right Line1L Mux"},
1054 {"Right PGA Mixer", "Line1R Switch", "Right Line1R Mux"},
1055 {"Right PGA Mixer", "Line2R Switch", "Right Line2R Mux"},
1056 {"Right PGA Mixer", "Mic3R Switch", "MIC3R"},
1058 {"Right ADC", NULL, "Right PGA Mixer"},
1059 {"Right ADC", NULL, "GPIO1 dmic modclk"},
1061 /* Left PGA Bypass */
1062 {"Left PGA Bypass Mixer", "Line Switch", "Left PGA Mixer"},
1063 {"Left PGA Bypass Mixer", "Mono Switch", "Left PGA Mixer"},
1064 {"Left PGA Bypass Mixer", "HP Switch", "Left PGA Mixer"},
1065 {"Left PGA Bypass Mixer", "HPCOM Switch", "Left PGA Mixer"},
1067 {"Left HPCOM Mux", "differential of HPLOUT", "Left PGA Bypass Mixer"},
1068 {"Left HPCOM Mux", "constant VCM", "Left PGA Bypass Mixer"},
1069 {"Left HPCOM Mux", "single-ended", "Left PGA Bypass Mixer"},
1071 {"Left Line Out", NULL, "Left PGA Bypass Mixer"},
1072 {"Mono Out", NULL, "Left PGA Bypass Mixer"},
1073 {"Left HP Out", NULL, "Left PGA Bypass Mixer"},
1075 /* Right PGA Bypass */
1076 {"Right PGA Bypass Mixer", "Line Switch", "Right PGA Mixer"},
1077 {"Right PGA Bypass Mixer", "Mono Switch", "Right PGA Mixer"},
1078 {"Right PGA Bypass Mixer", "HP Switch", "Right PGA Mixer"},
1079 {"Right PGA Bypass Mixer", "HPCOM Switch", "Right PGA Mixer"},
1081 {"Right HPCOM Mux", "differential of HPROUT", "Right PGA Bypass Mixer"},
1082 {"Right HPCOM Mux", "constant VCM", "Right PGA Bypass Mixer"},
1083 {"Right HPCOM Mux", "single-ended", "Right PGA Bypass Mixer"},
1084 {"Right HPCOM Mux", "differential of HPLCOM", "Right PGA Bypass Mixer"},
1085 {"Right HPCOM Mux", "external feedback", "Right PGA Bypass Mixer"},
1087 {"Right Line Out", NULL, "Right PGA Bypass Mixer"},
1088 {"Mono Out", NULL, "Right PGA Bypass Mixer"},
1089 {"Right HP Out", NULL, "Right PGA Bypass Mixer"},
1091 /* Left Line2 Bypass */
1092 {"Left Line2 Bypass Mixer", "Line Switch", "Left Line2L Mux"},
1093 {"Left Line2 Bypass Mixer", "Mono Switch", "Left Line2L Mux"},
1094 {"Left Line2 Bypass Mixer", "HP Switch", "Left Line2L Mux"},
1095 {"Left Line2 Bypass Mixer", "HPCOM Switch", "Left Line2L Mux"},
1097 {"Left HPCOM Mux", "differential of HPLOUT", "Left Line2 Bypass Mixer"},
1098 {"Left HPCOM Mux", "constant VCM", "Left Line2 Bypass Mixer"},
1099 {"Left HPCOM Mux", "single-ended", "Left Line2 Bypass Mixer"},
1101 {"Left Line Out", NULL, "Left Line2 Bypass Mixer"},
1102 {"Mono Out", NULL, "Left Line2 Bypass Mixer"},
1103 {"Left HP Out", NULL, "Left Line2 Bypass Mixer"},
1105 /* Right Line2 Bypass */
1106 {"Right Line2 Bypass Mixer", "Line Switch", "Right Line2R Mux"},
1107 {"Right Line2 Bypass Mixer", "Mono Switch", "Right Line2R Mux"},
1108 {"Right Line2 Bypass Mixer", "HP Switch", "Right Line2R Mux"},
1109 {"Right Line2 Bypass Mixer", "HPCOM Switch", "Right Line2R Mux"},
1111 {"Right HPCOM Mux", "differential of HPROUT", "Right Line2 Bypass Mixer"},
1112 {"Right HPCOM Mux", "constant VCM", "Right Line2 Bypass Mixer"},
1113 {"Right HPCOM Mux", "single-ended", "Right Line2 Bypass Mixer"},
1114 {"Right HPCOM Mux", "differential of HPLCOM", "Right Line2 Bypass Mixer"},
1115 {"Right HPCOM Mux", "external feedback", "Right Line2 Bypass Mixer"},
1117 {"Right Line Out", NULL, "Right Line2 Bypass Mixer"},
1118 {"Mono Out", NULL, "Right Line2 Bypass Mixer"},
1119 {"Right HP Out", NULL, "Right Line2 Bypass Mixer"},
1122 * Logical path between digital mic enable and GPIO1 modulator clock
1125 {"GPIO1 dmic modclk", NULL, "DMic Rate 128"},
1126 {"GPIO1 dmic modclk", NULL, "DMic Rate 64"},
1127 {"GPIO1 dmic modclk", NULL, "DMic Rate 32"},
1130 static int aic3x_add_widgets(struct snd_soc_codec *codec)
1132 snd_soc_dapm_new_controls(codec, aic3x_dapm_widgets,
1133 ARRAY_SIZE(aic3x_dapm_widgets));
1135 /* set up audio path interconnects */
1136 snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
1138 snd_soc_dapm_new_widgets(codec);
1142 static int aic3x_hw_params(struct snd_pcm_substream *substream,
1143 struct snd_pcm_hw_params *params)
1145 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1146 struct snd_soc_device *socdev = rtd->socdev;
1147 struct snd_soc_codec *codec = socdev->codec;
1148 struct aic3x_priv *aic3x = codec->private_data;
1149 int codec_clk = 0, bypass_pll = 0, fsref, last_clk = 0;
1150 u8 data, r, p, pll_q, pll_p = 1, pll_r = 1, pll_j = 1;
1153 /* select data word length */
1155 aic3x_read_reg_cache(codec, AIC3X_ASD_INTF_CTRLB) & (~(0x3 << 4));
1156 switch (params_format(params)) {
1157 case SNDRV_PCM_FORMAT_S16_LE:
1159 case SNDRV_PCM_FORMAT_S20_3LE:
1160 data |= (0x01 << 4);
1162 case SNDRV_PCM_FORMAT_S24_LE:
1163 data |= (0x02 << 4);
1165 case SNDRV_PCM_FORMAT_S32_LE:
1166 data |= (0x03 << 4);
1169 aic3x_write(codec, AIC3X_ASD_INTF_CTRLB, data);
1171 /* Fsref can be 44100 or 48000 */
1172 fsref = (params_rate(params) % 11025 == 0) ? 44100 : 48000;
1174 /* Try to find a value for Q which allows us to bypass the PLL and
1175 * generate CODEC_CLK directly. */
1176 for (pll_q = 2; pll_q < 18; pll_q++)
1177 if (aic3x->sysclk / (128 * pll_q) == fsref) {
1184 aic3x_write(codec, AIC3X_PLL_PROGA_REG, pll_q << PLLQ_SHIFT);
1185 aic3x_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_CLKDIV);
1187 aic3x_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_PLLDIV);
1189 /* Route Left DAC to left channel input and
1190 * right DAC to right channel input */
1191 data = (LDAC2LCH | RDAC2RCH);
1192 data |= (fsref == 44100) ? FSREF_44100 : FSREF_48000;
1193 if (params_rate(params) >= 64000)
1194 data |= DUAL_RATE_MODE;
1195 aic3x_write(codec, AIC3X_CODEC_DATAPATH_REG, data);
1197 /* codec sample rate select */
1198 data = (fsref * 20) / params_rate(params);
1199 if (params_rate(params) < 64000)
1203 data |= (data << 4);
1204 aic3x_write(codec, AIC3X_SAMPLE_RATE_SEL_REG, data);
1210 * find an apropriate setup for j, d, r and p by iterating over
1211 * p and r - j and d are calculated for each fraction.
1212 * Up to 128 values are probed, the closest one wins the game.
1213 * The sysclk is divided by 1000 to prevent integer overflows.
1215 codec_clk = (2048 * fsref) / (aic3x->sysclk / 1000);
1217 for (r = 1; r <= 16; r++)
1218 for (p = 1; p <= 8; p++) {
1219 int clk, tmp = (codec_clk * pll_r * 10) / pll_p;
1221 u16 d = tmp % 10000;
1226 if (d != 0 && aic3x->sysclk < 10000000)
1229 /* This is actually 1000 * ((j + (d/10000)) * r) / p
1230 * The term had to be converted to get rid of the
1231 * division by 10000 */
1232 clk = ((10000 * j * r) + (d * r)) / (10 * p);
1234 /* check whether this values get closer than the best
1235 * ones we had before */
1236 if (abs(codec_clk - clk) < abs(codec_clk - last_clk)) {
1237 pll_j = j; pll_d = d; pll_r = r; pll_p = p;
1241 /* Early exit for exact matches */
1242 if (clk == codec_clk)
1246 if (last_clk == 0) {
1247 printk(KERN_ERR "%s(): unable to setup PLL\n", __func__);
1251 data = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
1252 aic3x_write(codec, AIC3X_PLL_PROGA_REG, data | (pll_p << PLLP_SHIFT));
1253 aic3x_write(codec, AIC3X_OVRF_STATUS_AND_PLLR_REG, pll_r << PLLR_SHIFT);
1254 aic3x_write(codec, AIC3X_PLL_PROGB_REG, pll_j << PLLJ_SHIFT);
1255 aic3x_write(codec, AIC3X_PLL_PROGC_REG, (pll_d >> 6) << PLLD_MSB_SHIFT);
1256 aic3x_write(codec, AIC3X_PLL_PROGD_REG,
1257 (pll_d & 0x3F) << PLLD_LSB_SHIFT);
1262 static int aic3x_mute(struct snd_soc_dai *dai, int mute)
1264 struct snd_soc_codec *codec = dai->codec;
1265 u8 ldac_reg = aic3x_read_reg_cache(codec, LDAC_VOL) & ~MUTE_ON;
1266 u8 rdac_reg = aic3x_read_reg_cache(codec, RDAC_VOL) & ~MUTE_ON;
1269 aic3x_write(codec, LDAC_VOL, ldac_reg | MUTE_ON);
1270 aic3x_write(codec, RDAC_VOL, rdac_reg | MUTE_ON);
1272 aic3x_write(codec, LDAC_VOL, ldac_reg);
1273 aic3x_write(codec, RDAC_VOL, rdac_reg);
1279 static int aic3x_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1280 int clk_id, unsigned int freq, int dir)
1282 struct snd_soc_codec *codec = codec_dai->codec;
1283 struct aic3x_priv *aic3x = codec->private_data;
1285 aic3x->sysclk = freq;
1289 static int aic3x_set_dai_fmt(struct snd_soc_dai *codec_dai,
1292 struct snd_soc_codec *codec = codec_dai->codec;
1293 struct aic3x_priv *aic3x = codec->private_data;
1294 u8 iface_areg, iface_breg;
1297 iface_areg = aic3x_read_reg_cache(codec, AIC3X_ASD_INTF_CTRLA) & 0x3f;
1298 iface_breg = aic3x_read_reg_cache(codec, AIC3X_ASD_INTF_CTRLB) & 0x3f;
1300 /* set master/slave audio interface */
1301 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1302 case SND_SOC_DAIFMT_CBM_CFM:
1304 iface_areg |= BIT_CLK_MASTER | WORD_CLK_MASTER;
1306 case SND_SOC_DAIFMT_CBS_CFS:
1314 * match both interface format and signal polarities since they
1317 switch (fmt & (SND_SOC_DAIFMT_FORMAT_MASK |
1318 SND_SOC_DAIFMT_INV_MASK)) {
1319 case (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF):
1321 case (SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_IB_NF):
1323 case (SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_IB_NF):
1324 iface_breg |= (0x01 << 6);
1326 case (SND_SOC_DAIFMT_RIGHT_J | SND_SOC_DAIFMT_NB_NF):
1327 iface_breg |= (0x02 << 6);
1329 case (SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_NB_NF):
1330 iface_breg |= (0x03 << 6);
1337 aic3x_write(codec, AIC3X_ASD_INTF_CTRLA, iface_areg);
1338 aic3x_write(codec, AIC3X_ASD_INTF_CTRLB, iface_breg);
1339 aic3x_write(codec, AIC3X_ASD_INTF_CTRLC, delay);
1344 static int aic3x_set_bias_level(struct snd_soc_codec *codec,
1345 enum snd_soc_bias_level level)
1347 struct aic3x_priv *aic3x = codec->private_data;
1351 case SND_SOC_BIAS_ON:
1352 /* all power is driven by DAPM system */
1353 if (aic3x->master) {
1355 reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
1356 aic3x_write(codec, AIC3X_PLL_PROGA_REG,
1359 * ensure that bit and word clocks are running also if
1360 * DAC and ADC are shutdown
1362 reg = aic3x_read_reg_cache(codec, AIC3X_ASD_INTF_CTRLA);
1363 aic3x_write(codec, AIC3X_ASD_INTF_CTRLA, reg | 0x10);
1366 case SND_SOC_BIAS_PREPARE:
1368 case SND_SOC_BIAS_STANDBY:
1370 * all power is driven by DAPM system,
1371 * so output power is safe if bypass was set
1373 if (aic3x->master) {
1374 reg = aic3x_read_reg_cache(codec, AIC3X_ASD_INTF_CTRLA);
1375 aic3x_write(codec, AIC3X_ASD_INTF_CTRLA, reg & ~0x10);
1377 reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
1378 aic3x_write(codec, AIC3X_PLL_PROGA_REG,
1381 /* Reset cannot be issued, if bypass paths are in use */
1382 if (!aic3x->prepare_reset)
1385 case SND_SOC_BIAS_OFF:
1386 /* force all power off */
1387 reg = aic3x_read_reg_cache(codec, LINE1L_2_LADC_CTRL);
1388 aic3x_write(codec, LINE1L_2_LADC_CTRL, reg & ~LADC_PWR_ON);
1389 reg = aic3x_read_reg_cache(codec, LINE1R_2_RADC_CTRL);
1390 aic3x_write(codec, LINE1R_2_RADC_CTRL, reg & ~RADC_PWR_ON);
1392 reg = aic3x_read_reg_cache(codec, DAC_PWR);
1393 aic3x_write(codec, DAC_PWR, reg & ~(LDAC_PWR_ON | RDAC_PWR_ON));
1395 reg = aic3x_read_reg_cache(codec, HPLOUT_CTRL);
1396 aic3x_write(codec, HPLOUT_CTRL, reg & ~HPLOUT_PWR_ON);
1397 reg = aic3x_read_reg_cache(codec, HPROUT_CTRL);
1398 aic3x_write(codec, HPROUT_CTRL, reg & ~HPROUT_PWR_ON);
1400 reg = aic3x_read_reg_cache(codec, HPLCOM_CTRL);
1401 aic3x_write(codec, HPLCOM_CTRL, reg & ~HPLCOM_PWR_ON);
1402 reg = aic3x_read_reg_cache(codec, HPRCOM_CTRL);
1403 aic3x_write(codec, HPRCOM_CTRL, reg & ~HPRCOM_PWR_ON);
1405 reg = aic3x_read_reg_cache(codec, MONOLOPM_CTRL);
1406 aic3x_write(codec, MONOLOPM_CTRL, reg & ~MONOLOPM_PWR_ON);
1408 reg = aic3x_read_reg_cache(codec, LLOPM_CTRL);
1409 aic3x_write(codec, LLOPM_CTRL, reg & ~LLOPM_PWR_ON);
1410 reg = aic3x_read_reg_cache(codec, RLOPM_CTRL);
1411 aic3x_write(codec, RLOPM_CTRL, reg & ~RLOPM_PWR_ON);
1413 if (aic3x->master) {
1414 reg = aic3x_read_reg_cache(codec, AIC3X_ASD_INTF_CTRLA);
1415 aic3x_write(codec, AIC3X_ASD_INTF_CTRLA, reg & ~0x10);
1417 reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
1418 aic3x_write(codec, AIC3X_PLL_PROGA_REG,
1423 codec->bias_level = level;
1428 void aic3x_set_gpio(struct snd_soc_codec *codec, int gpio, int state)
1430 u8 reg = gpio ? AIC3X_GPIO2_REG : AIC3X_GPIO1_REG;
1431 u8 bit = gpio ? 3: 0;
1432 u8 val = aic3x_read_reg_cache(codec, reg) & ~(1 << bit);
1433 aic3x_write(codec, reg, val | (!!state << bit));
1435 EXPORT_SYMBOL_GPL(aic3x_set_gpio);
1437 int aic3x_get_gpio(struct snd_soc_codec *codec, int gpio)
1439 u8 reg = gpio ? AIC3X_GPIO2_REG : AIC3X_GPIO1_REG;
1440 u8 val, bit = gpio ? 2: 1;
1442 aic3x_read(codec, reg, &val);
1443 return (val >> bit) & 1;
1445 EXPORT_SYMBOL_GPL(aic3x_get_gpio);
1447 int aic3x_headset_detected(struct snd_soc_codec *codec)
1450 aic3x_read(codec, AIC3X_RT_IRQ_FLAGS_REG, &val);
1451 return (val >> 2) & 1;
1453 EXPORT_SYMBOL_GPL(aic3x_headset_detected);
1455 #define AIC3X_RATES SNDRV_PCM_RATE_8000_96000
1456 #define AIC3X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1457 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
1459 struct snd_soc_dai aic3x_dai = {
1460 .name = "tlv320aic3x",
1462 .stream_name = "Playback",
1465 .rates = AIC3X_RATES,
1466 .formats = AIC3X_FORMATS,},
1468 .stream_name = "Capture",
1471 .rates = AIC3X_RATES,
1472 .formats = AIC3X_FORMATS,},
1474 .hw_params = aic3x_hw_params,
1477 .digital_mute = aic3x_mute,
1478 .set_sysclk = aic3x_set_dai_sysclk,
1479 .set_fmt = aic3x_set_dai_fmt,
1482 EXPORT_SYMBOL_GPL(aic3x_dai);
1484 static int aic3x_suspend(struct platform_device *pdev, pm_message_t state)
1486 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1487 struct snd_soc_codec *codec = socdev->codec;
1489 aic3x_write(codec, AIC3X_RESET, SOFT_RESET);
1494 static int aic3x_resume(struct platform_device *pdev)
1496 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1497 aic3x_sync_hw(socdev->codec);
1498 aic3x_set_bias_level(socdev->codec,
1499 socdev->codec->suspend_bias_level);
1505 * initialise the AIC3X driver
1506 * register the mixer and dsp interfaces with the kernel
1508 static int aic3x_init(struct snd_soc_device *socdev)
1510 struct snd_soc_codec *codec = socdev->codec;
1511 struct aic3x_setup_data *setup = socdev->codec_data;
1512 struct snd_hwdep *hwdep;
1513 char hwdepid[] = "IIR Filter";
1516 codec->name = "tlv320aic3x";
1517 codec->owner = THIS_MODULE;
1518 codec->read = aic3x_read_reg_cache;
1519 codec->write = aic3x_write;
1520 codec->set_bias_level = aic3x_set_bias_level;
1521 codec->dai = &aic3x_dai;
1523 codec->reg_cache_size = ARRAY_SIZE(aic3x_reg);
1524 codec->reg_cache = kmemdup(aic3x_reg, sizeof(aic3x_reg), GFP_KERNEL);
1525 if (codec->reg_cache == NULL)
1528 aic3x_write(codec, AIC3X_PAGE_SELECT, PAGE0_SELECT);
1529 aic3x_write(codec, AIC3X_RESET, SOFT_RESET);
1532 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
1534 printk(KERN_ERR "aic3x: failed to create pcms\n");
1538 /* DAC default volume and mute */
1539 aic3x_write(codec, LDAC_VOL, DEFAULT_VOL | MUTE_ON);
1540 aic3x_write(codec, RDAC_VOL, DEFAULT_VOL | MUTE_ON);
1542 /* DAC to HP default volume and route to Output mixer */
1543 aic3x_write(codec, DACL1_2_HPLOUT_VOL, DEFAULT_VOL | ROUTE_ON);
1544 aic3x_write(codec, DACR1_2_HPROUT_VOL, DEFAULT_VOL | ROUTE_ON);
1545 aic3x_write(codec, DACL1_2_HPLCOM_VOL, DEFAULT_VOL | ROUTE_ON);
1546 aic3x_write(codec, DACR1_2_HPRCOM_VOL, DEFAULT_VOL | ROUTE_ON);
1547 /* DAC to Line Out default volume and route to Output mixer */
1548 aic3x_write(codec, DACL1_2_LLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1549 aic3x_write(codec, DACR1_2_RLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1550 /* DAC to Mono Line Out default volume and route to Output mixer */
1551 aic3x_write(codec, DACL1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1552 aic3x_write(codec, DACR1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1554 /* unmute all outputs */
1555 reg = aic3x_read_reg_cache(codec, LLOPM_CTRL);
1556 aic3x_write(codec, LLOPM_CTRL, reg | UNMUTE);
1557 reg = aic3x_read_reg_cache(codec, RLOPM_CTRL);
1558 aic3x_write(codec, RLOPM_CTRL, reg | UNMUTE);
1559 reg = aic3x_read_reg_cache(codec, MONOLOPM_CTRL);
1560 aic3x_write(codec, MONOLOPM_CTRL, reg | UNMUTE);
1561 reg = aic3x_read_reg_cache(codec, HPLOUT_CTRL);
1562 aic3x_write(codec, HPLOUT_CTRL, reg | UNMUTE);
1563 reg = aic3x_read_reg_cache(codec, HPROUT_CTRL);
1564 aic3x_write(codec, HPROUT_CTRL, reg | UNMUTE);
1565 reg = aic3x_read_reg_cache(codec, HPLCOM_CTRL);
1566 aic3x_write(codec, HPLCOM_CTRL, reg | UNMUTE);
1567 reg = aic3x_read_reg_cache(codec, HPRCOM_CTRL);
1568 aic3x_write(codec, HPRCOM_CTRL, reg | UNMUTE);
1570 /* ADC default volume and unmute */
1571 aic3x_write(codec, LADC_VOL, DEFAULT_GAIN);
1572 aic3x_write(codec, RADC_VOL, DEFAULT_GAIN);
1573 /* By default route Line1 to ADC PGA mixer */
1574 aic3x_write(codec, LINE1L_2_LADC_CTRL, 0x0);
1575 aic3x_write(codec, LINE1R_2_RADC_CTRL, 0x0);
1577 /* PGA to HP Bypass default volume, disconnect from Output Mixer */
1578 aic3x_write(codec, PGAL_2_HPLOUT_VOL, DEFAULT_VOL);
1579 aic3x_write(codec, PGAR_2_HPROUT_VOL, DEFAULT_VOL);
1580 aic3x_write(codec, PGAL_2_HPLCOM_VOL, DEFAULT_VOL);
1581 aic3x_write(codec, PGAR_2_HPRCOM_VOL, DEFAULT_VOL);
1582 /* PGA to Line Out default volume, disconnect from Output Mixer */
1583 aic3x_write(codec, PGAL_2_LLOPM_VOL, DEFAULT_VOL);
1584 aic3x_write(codec, PGAR_2_RLOPM_VOL, DEFAULT_VOL);
1585 /* PGA to Mono Line Out default volume, disconnect from Output Mixer */
1586 aic3x_write(codec, PGAL_2_MONOLOPM_VOL, DEFAULT_VOL);
1587 aic3x_write(codec, PGAR_2_MONOLOPM_VOL, DEFAULT_VOL);
1589 /* Line2 to HP Bypass default volume, disconnect from Output Mixer */
1590 aic3x_write(codec, LINE2L_2_HPLOUT_VOL, DEFAULT_VOL);
1591 aic3x_write(codec, LINE2R_2_HPROUT_VOL, DEFAULT_VOL);
1592 aic3x_write(codec, LINE2L_2_HPLCOM_VOL, DEFAULT_VOL);
1593 aic3x_write(codec, LINE2R_2_HPRCOM_VOL, DEFAULT_VOL);
1594 /* Line2 Line Out default volume, disconnect from Output Mixer */
1595 aic3x_write(codec, LINE2L_2_LLOPM_VOL, DEFAULT_VOL);
1596 aic3x_write(codec, LINE2R_2_RLOPM_VOL, DEFAULT_VOL);
1597 /* Line2 to Mono Out default volume, disconnect from Output Mixer */
1598 aic3x_write(codec, LINE2L_2_MONOLOPM_VOL, DEFAULT_VOL);
1599 aic3x_write(codec, LINE2R_2_MONOLOPM_VOL, DEFAULT_VOL);
1601 /* off, with power on */
1602 aic3x_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1604 /* setup GPIO functions */
1605 aic3x_write(codec, AIC3X_GPIO1_REG, (setup->gpio_func[0] & 0xf) << 4);
1606 aic3x_write(codec, AIC3X_GPIO2_REG, (setup->gpio_func[1] & 0xf) << 4);
1608 aic3x_add_controls(codec);
1609 aic3x_add_widgets(codec);
1611 if(snd_hwdep_new(codec->card, hwdepid, 0, &hwdep) == 0){
1612 hwdep->private_data = codec;
1613 sprintf(hwdep->name, hwdepid);
1614 hwdep->ops.open = snd_hwdep_dacfilter_open_aic3x;
1615 hwdep->ops.ioctl = snd_hwdep_dacfilter_ioctl_aic3x;
1616 hwdep->ops.read = snd_hwdep_dacfilter_read_aic3x;
1617 hwdep->ops.write = snd_hwdep_dacfilter_write_aic3x;
1618 ((struct aic3x_priv*)codec->private_data)->hwdep = hwdep;
1621 ret = snd_soc_register_card(socdev);
1624 printk(KERN_ERR "aic3x: failed to register card\n");
1628 /* Set some defaults for coefficients */
1629 aic3x_write_coeff(codec, EFFECTS_3DATTEN, -32768);
1634 snd_soc_free_pcms(socdev);
1635 snd_soc_dapm_free(socdev);
1637 kfree(codec->reg_cache);
1641 static struct snd_soc_device *aic3x_socdev;
1643 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1645 * AIC3X 2 wire address can be up to 4 devices with device addresses
1646 * 0x18, 0x19, 0x1A, 0x1B
1650 * If the i2c layer weren't so broken, we could pass this kind of data
1653 static int aic3x_i2c_probe(struct i2c_client *i2c,
1654 const struct i2c_device_id *id)
1656 struct snd_soc_device *socdev = aic3x_socdev;
1657 struct snd_soc_codec *codec = socdev->codec;
1660 i2c_set_clientdata(i2c, codec);
1661 codec->control_data = i2c;
1663 ret = aic3x_init(socdev);
1665 printk(KERN_ERR "aic3x: failed to initialise AIC3X\n");
1669 static int aic3x_i2c_remove(struct i2c_client *client)
1671 struct snd_soc_codec *codec = i2c_get_clientdata(client);
1672 kfree(codec->reg_cache);
1676 static const struct i2c_device_id aic3x_i2c_id[] = {
1677 { "tlv320aic3x", 0 },
1680 MODULE_DEVICE_TABLE(i2c, aic3x_i2c_id);
1682 /* machine i2c codec control layer */
1683 static struct i2c_driver aic3x_i2c_driver = {
1685 .name = "aic3x I2C Codec",
1686 .owner = THIS_MODULE,
1688 .probe = aic3x_i2c_probe,
1689 .remove = aic3x_i2c_remove,
1690 .id_table = aic3x_i2c_id,
1693 static int aic3x_i2c_read(struct i2c_client *client, u8 *value, int len)
1695 value[0] = i2c_smbus_read_byte_data(client, value[0]);
1699 static int aic3x_add_i2c_device(struct platform_device *pdev,
1700 const struct aic3x_setup_data *setup)
1702 struct i2c_board_info info;
1703 struct i2c_adapter *adapter;
1704 struct i2c_client *client;
1707 ret = i2c_add_driver(&aic3x_i2c_driver);
1709 dev_err(&pdev->dev, "can't add i2c driver\n");
1713 memset(&info, 0, sizeof(struct i2c_board_info));
1714 info.addr = setup->i2c_address;
1715 strlcpy(info.type, "tlv320aic3x", I2C_NAME_SIZE);
1717 adapter = i2c_get_adapter(setup->i2c_bus);
1719 dev_err(&pdev->dev, "can't get i2c adapter %d\n",
1724 client = i2c_new_device(adapter, &info);
1725 i2c_put_adapter(adapter);
1727 dev_err(&pdev->dev, "can't add i2c device at 0x%x\n",
1728 (unsigned int)info.addr);
1735 i2c_del_driver(&aic3x_i2c_driver);
1740 static int aic3x_probe(struct platform_device *pdev)
1742 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1743 struct aic3x_setup_data *setup;
1744 struct snd_soc_codec *codec;
1745 struct aic3x_priv *aic3x;
1748 printk(KERN_INFO "AIC3X Audio Codec %s\n", AIC3X_VERSION);
1750 setup = socdev->codec_data;
1751 codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
1755 aic3x = kzalloc(sizeof(struct aic3x_priv), GFP_KERNEL);
1756 memcpy(&aic3x->dacfilter, &aic3x_dacfilter, sizeof(aic3x_dacfilter));
1758 if (aic3x == NULL) {
1763 codec->private_data = aic3x;
1764 socdev->codec = codec;
1765 mutex_init(&codec->mutex);
1766 INIT_LIST_HEAD(&codec->dapm_widgets);
1767 INIT_LIST_HEAD(&codec->dapm_paths);
1769 aic3x_socdev = socdev;
1770 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1771 if (setup->i2c_address) {
1772 codec->hw_write = (hw_write_t) i2c_master_send;
1773 codec->hw_read = (hw_read_t) aic3x_i2c_read;
1774 ret = aic3x_add_i2c_device(pdev, setup);
1777 /* Add other interfaces here */
1781 kfree(codec->private_data);
1787 static int aic3x_remove(struct platform_device *pdev)
1789 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1790 struct snd_soc_codec *codec = socdev->codec;
1792 /* power down chip */
1793 if (codec->control_data)
1794 aic3x_set_bias_level(codec, SND_SOC_BIAS_OFF);
1796 snd_soc_free_pcms(socdev);
1797 snd_soc_dapm_free(socdev);
1798 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1799 if (codec->control_data)
1800 i2c_unregister_device(codec->control_data);
1801 i2c_del_driver(&aic3x_i2c_driver);
1803 kfree(codec->private_data);
1809 struct snd_soc_codec_device soc_codec_dev_aic3x = {
1810 .probe = aic3x_probe,
1811 .remove = aic3x_remove,
1812 .suspend = aic3x_suspend,
1813 .resume = aic3x_resume,
1815 EXPORT_SYMBOL_GPL(soc_codec_dev_aic3x);
1817 MODULE_DESCRIPTION("ASoC TLV320AIC3X codec driver");
1818 MODULE_AUTHOR("Vladimir Barinov");
1819 MODULE_LICENSE("GPL");