2 * ALSA SoC TLV320AIC3X codec driver
4 * Author: Vladimir Barinov, <vbarinov@embeddedalley.com>
5 * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com>
7 * Based on sound/soc/codecs/wm8753.c by Liam Girdwood
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 * The AIC3X is a driver for a low power stereo audio
15 * codecs aic31, aic32, aic33.
17 * It supports full aic33 codec functionality.
18 * The compatibility with aic32, aic31 is as follows:
20 * ---------------------------------------
21 * MONO_LOUT -> N/A | MONO_LOUT -> N/A
27 * truncated internal functionality in
28 * accordance with documentation
29 * ---------------------------------------
31 * Hence the machine layer should disable unsupported inputs/outputs by
32 * snd_soc_dapm_disable_pin(codec, "MONO_LOUT"), etc.
35 #include <linux/module.h>
36 #include <linux/moduleparam.h>
37 #include <linux/init.h>
38 #include <linux/delay.h>
40 #include <linux/i2c.h>
41 #include <linux/platform_device.h>
42 #include <sound/core.h>
43 #include <sound/pcm.h>
44 #include <sound/pcm_params.h>
45 #include <sound/soc.h>
46 #include <sound/soc-dapm.h>
47 #include <sound/initval.h>
48 #include <sound/tlv.h>
49 #include <sound/hwdep.h>
51 #include "tlv320aic3x.h"
53 #define AIC3X_VERSION "0.2"
55 static int hp_dac_lim = 9;
56 module_param(hp_dac_lim, int, 0);
58 struct aic3x_dacfilter_t {
59 struct aic3x_iir_coeffs coeffs;
63 .N0 = 27619, .N1 = -27034, .N2 = 26461, .D1 = 32131, .D2 = -31506,
64 .N3 = 27619, .N4 = -27034, .N5 = 26461, .D4 = 32131, .D5 = -31506,
69 /* codec private data */
74 struct snd_hwdep *hwdep;
75 struct aic3x_dacfilter_t dacfilter;
79 * AIC3X register cache
80 * We can't read the AIC3X register space when we are
81 * using 2 wire for device control, so we cache them instead.
82 * There is no point in caching the reset register
84 static const u8 aic3x_reg[AIC3X_CACHEREGNUM] = {
85 0x00, 0x00, 0x00, 0x10, /* 0 */
86 0x04, 0x00, 0x00, 0x00, /* 4 */
87 0x00, 0x00, 0x00, 0x01, /* 8 */
88 0x00, 0x00, 0x00, 0x80, /* 12 */
89 0x80, 0xff, 0xff, 0x78, /* 16 */
90 0x78, 0x78, 0x78, 0x78, /* 20 */
91 0x78, 0x00, 0x00, 0xfe, /* 24 */
92 0x00, 0x00, 0xfe, 0x00, /* 28 */
93 0x00, 0x00, 0x00, 0x00, /* 32 */
94 0x00, 0x00, 0x00, 0x00, /* 36 */
95 0x00, 0x00, 0x00, 0x80, /* 40 */
96 0x80, 0x00, 0x00, 0x00, /* 44 */
97 0x00, 0x00, 0x00, 0x04, /* 48 */
98 0x00, 0x00, 0x00, 0x00, /* 52 */
99 0x00, 0x00, 0x04, 0x00, /* 56 */
100 0x00, 0x00, 0x00, 0x00, /* 60 */
101 0x00, 0x04, 0x00, 0x00, /* 64 */
102 0x00, 0x00, 0x00, 0x00, /* 68 */
103 0x04, 0x00, 0x00, 0x00, /* 72 */
104 0x00, 0x00, 0x00, 0x00, /* 76 */
105 0x00, 0x00, 0x00, 0x00, /* 80 */
106 0x00, 0x00, 0x00, 0x00, /* 84 */
107 0x00, 0x00, 0x00, 0x00, /* 88 */
108 0x00, 0x00, 0x00, 0x00, /* 92 */
109 0x00, 0x00, 0x00, 0x00, /* 96 */
110 0x00, 0x00, 0x02, 0x00, /* 100 */
111 0x00, 0x00, 0x00, 0x00, /* 104 */
112 0x00, 0x00, 0x00, 0x00, /* 108 */
113 0x00, 0x00, 0x00, 0x00, /* 112 */
114 0x00, 0x00, 0x00, 0x00, /* 116 */
115 0x00, 0x00, 0x00, 0x00, /* 120 */
116 0x00, 0x00, 0x00, 0x00, /* 124 */
117 0x01, 0x6b, 0xe3, 0x96, /* 128 */
118 0x66, 0x67, 0x5d, 0x6b, /* 132 */
119 0xe3, 0x96, 0x66, 0x67, /* 136 */
120 0x5d, 0x7d, 0x83, 0x84, /* 140 */
121 0xee, 0x7d, 0x83, 0x84, /* 144 */
122 0xee, 0x39, 0x55, 0xf3, /* 148 */
123 0x2d, 0x53, 0x7e, 0x6b, /* 152 */
124 0xe3, 0x96, 0x66, 0x67, /* 156 */
125 0x5d, 0x6b, 0xe3, 0x96, /* 160 */
126 0x66, 0x67, 0x5d, 0x7d, /* 164 */
127 0x83, 0x84, 0xee, 0x7d, /* 168 */
128 0x83, 0x84, 0xee, 0x39, /* 172 */
129 0x55, 0xf3, 0x2d, 0x53, /* 176 */
130 0x7e, 0x7f, 0xff, 0x00, /* 180 */
131 0x00, 0x00, 0x00, 0x00, /* 184 */
132 0x00, 0x00, 0x00, 0x00, /* 188 */
133 0x00, 0x39, 0x55, 0xf3, /* 192 */
134 0x2d, 0x53, 0x7e, 0x39, /* 196 */
135 0x55, 0xf3, 0x2d, 0x53, /* 200 */
140 * read aic3x register cache
142 static inline unsigned int aic3x_read_reg_cache(struct snd_soc_codec *codec,
145 u8 *cache = codec->reg_cache;
146 if (reg >= AIC3X_CACHEREGNUM)
151 static inline int aic3x_read_coeff_reg_cache
152 (struct snd_soc_codec *codec, unsigned int msbreg)
155 val = aic3x_read_reg_cache(codec, msbreg) << 8;
156 val |= aic3x_read_reg_cache(codec, msbreg+1);
157 if(val > 32767) val -= 65536;
162 * write aic3x register cache
164 static inline void aic3x_write_reg_cache(struct snd_soc_codec *codec,
167 u8 *cache = codec->reg_cache;
168 if (reg >= AIC3X_CACHEREGNUM)
174 * write to the aic3x register space
176 static int aic3x_write(struct snd_soc_codec *codec,
177 unsigned int reg, unsigned int value)
179 static char curpage = -1;
180 u8 data[2], page = 0;
182 /*mutex_lock(&codec->mutex);*/
188 //printk("MNZ: aic3x_write(reg = %i, val = 0x%x, page = %i)\n",
190 if(reg && curpage != page){
193 if (codec->hw_write(codec->control_data, data, 2) != 2){
194 /*mutex_unlock(&codec->mutex);*/
203 * D15..D8 aic3x register offset
204 * D7...D0 register data
209 if (codec->hw_write(codec->control_data, data, 2) == 2){
210 aic3x_write_reg_cache(codec, data[0] + page * 128, data[1]);
211 if(!reg) curpage = value; /* for reg = 0, ie, page setting */
212 /*mutex_unlock(&codec->mutex);*/
215 /*mutex_unlock(&codec->mutex);*/
222 /* Convert a value to 2s compliment and write to registers */
223 static int aic3x_write_coeff(struct snd_soc_codec *codec,
224 u8 msbreg, int value)
229 outp = 65536 + value;
233 aic3x_write(codec, msbreg, outp >> 8);
234 aic3x_write(codec, msbreg+1, outp);
241 * read from the aic3x register space
243 static int aic3x_read(struct snd_soc_codec *codec, unsigned int reg,
248 /* No read access is recommended if the chip is reset after use */
249 printk(KERN_ERR "%s(): Values are may be incorrect!\n", __func__);
251 if (codec->hw_read(codec->control_data, value, 1) != 1)
254 aic3x_write_reg_cache(codec, reg, *value);
258 static int aic3x_sync_hw(struct snd_soc_codec *codec)
260 u8 *cache = codec->reg_cache;
264 aic3x_write(codec, AIC3X_PAGE_SELECT, 1);
265 /*mutex_lock(&codec->mutex);*/
266 for (i = 1; i < AIC3X_PAGE1REGNUM; i++) {
268 data[1] = cache[i+128];
269 codec->hw_write(codec->control_data, data, 2);
271 /*mutex_unlock(&codec->mutex);*/
273 /* We do not rewrite page select nor reset again */
274 aic3x_write(codec, AIC3X_PAGE_SELECT, 0);
275 /*mutex_lock(&codec->mutex);*/
276 for (i = 2; i < AIC3X_PAGE0REGNUM; i++) {
279 codec->hw_write(codec->control_data, data, 2);
281 /*mutex_unlock(&codec->mutex);*/
287 * Reset for getting low power consumption after bypass paths
289 static void aic3x_reset(struct snd_soc_codec *codec)
291 aic3x_write(codec, AIC3X_RESET, SOFT_RESET);
292 aic3x_sync_hw(codec);
295 #define SOC_DAPM_SINGLE_AIC3X(xname, reg, shift, mask, invert) \
296 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
297 .info = snd_soc_info_volsw, \
298 .get = snd_soc_dapm_get_volsw, .put = snd_soc_dapm_put_volsw_aic3x, \
299 .private_value = SOC_SINGLE_VALUE(reg, shift, mask, invert) }
302 * All input lines are connected when !0xf and disconnected with 0xf bit field,
303 * so we have to use specific dapm_put call for input mixer
305 static int snd_soc_dapm_put_volsw_aic3x(struct snd_kcontrol *kcontrol,
306 struct snd_ctl_elem_value *ucontrol)
308 struct snd_soc_dapm_widget *widget = snd_kcontrol_chip(kcontrol);
309 struct soc_mixer_control *mc =
310 (struct soc_mixer_control *)kcontrol->private_value;
311 unsigned int reg = mc->reg;
312 unsigned int shift = mc->shift;
314 unsigned int mask = (1 << fls(max)) - 1;
315 unsigned int invert = mc->invert;
316 unsigned short val, val_mask;
318 struct snd_soc_dapm_path *path;
321 val = (ucontrol->value.integer.value[0] & mask);
329 val_mask = mask << shift;
332 mutex_lock(&widget->codec->mutex);
334 if (snd_soc_test_bits(widget->codec, reg, val_mask, val)) {
335 /* find dapm widget path assoc with kcontrol */
336 list_for_each_entry(path, &widget->codec->dapm_paths, list) {
337 if (path->kcontrol != kcontrol)
340 /* found, now check type */
344 path->connect = invert ? 0 : 1;
346 /* old connection must be powered down */
347 path->connect = invert ? 1 : 0;
352 snd_soc_dapm_sync(widget->codec);
355 ret = snd_soc_update_bits(widget->codec, reg, val_mask, val);
357 mutex_unlock(&widget->codec->mutex);
361 static const char *aic3x_left_dac_mux[] = { "DAC_L1", "DAC_L3", "DAC_L2" };
362 static const char *aic3x_right_dac_mux[] = { "DAC_R1", "DAC_R3", "DAC_R2" };
363 static const char *aic3x_left_hpcom_mux[] =
364 { "differential of HPLOUT", "constant VCM", "single-ended" };
365 static const char *aic3x_right_hpcom_mux[] =
366 { "differential of HPROUT", "constant VCM", "single-ended",
367 "differential of HPLCOM", "external feedback" };
368 static const char *aic3x_linein_mode_mux[] = { "single-ended", "differential" };
369 static const char *aic3x_adc_hpf[] =
370 { "Disabled", "0.0045xFs", "0.0125xFs", "0.025xFs" };
371 static const char *aic3x_dac_filt[] =
372 { "Off", "Bass/Treble", "Custom" };
376 #define LHPCOM_ENUM 2
377 #define RHPCOM_ENUM 3
378 #define LINE1L_ENUM 4
379 #define LINE1R_ENUM 5
380 #define LINE2L_ENUM 6
381 #define LINE2R_ENUM 7
382 #define ADC_HPF_ENUM 8
383 #define DAC_FILT_ENUM 9
385 static const struct soc_enum aic3x_enum[] = {
386 SOC_ENUM_SINGLE(DAC_LINE_MUX, 6, 3, aic3x_left_dac_mux),
387 SOC_ENUM_SINGLE(DAC_LINE_MUX, 4, 3, aic3x_right_dac_mux),
388 SOC_ENUM_SINGLE(HPLCOM_CFG, 4, 3, aic3x_left_hpcom_mux),
389 SOC_ENUM_SINGLE(HPRCOM_CFG, 3, 5, aic3x_right_hpcom_mux),
390 SOC_ENUM_SINGLE(LINE1L_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux),
391 SOC_ENUM_SINGLE(LINE1R_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux),
392 SOC_ENUM_SINGLE(LINE2L_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux),
393 SOC_ENUM_SINGLE(LINE2R_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux),
394 SOC_ENUM_DOUBLE(AIC3X_CODEC_DFILT_CTRL, 6, 4, 4, aic3x_adc_hpf),
395 SOC_ENUM_DOUBLE(AIC3X_CODEC_DFILT_CTRL, 1, 3, 3, aic3x_dac_filt),
399 * DAC digital volumes. From -63.5 to 0 dB in 0.5 dB steps
401 static DECLARE_TLV_DB_SCALE(dac_tlv, -6350, 50, 0);
402 /* ADC PGA gain volumes. From 0 to 59.5 dB in 0.5 dB steps */
403 static DECLARE_TLV_DB_SCALE(adc_tlv, 0, 50, 0);
404 /* HP DAC Output gain values. From 0 to 9.0 dB in 1 dB steps */
405 static DECLARE_TLV_DB_SCALE(hpout_tlv, 0, 100, 0);
407 * Output stage volumes. From -78.3 to 0 dB. Muted below -78.3 dB.
408 * Step size is approximately 0.5 dB over most of the scale but increasing
409 * near the very low levels.
410 * Define dB scale so that it is mostly correct for range about -55 to 0 dB
411 * but having increasing dB difference below that (and where it doesn't count
412 * so much). This setting shows -50 dB (actual is -50.3 dB) for register
413 * value 100 and -58.5 dB (actual is -78.3 dB) for register value 117.
415 static DECLARE_TLV_DB_SCALE(output_stage_tlv, -5900, 50, 1);
417 #define SOC_DOUBLE_R_TLV_TLV320ALC3X(xname, reg_left, reg_right, xshift, xmax,\
418 xinvert, tlv_array) \
419 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
420 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
421 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
422 .tlv.p = (tlv_array), \
423 .info = tlv320alc3x_info_volsw, \
424 .get = snd_soc_get_volsw_2r,\
425 .put = snd_soc_put_volsw_2r,\
426 .private_value = (unsigned long)&(struct soc_mixer_control) \
427 {.reg = reg_left, .rreg = reg_right, .shift = xshift, \
428 .max = xmax, .invert = xinvert} }
430 static int tlv320alc3x_info_volsw(struct snd_kcontrol *kcontrol,
431 struct snd_ctl_elem_info *uinfo)
433 struct soc_mixer_control *mc =
434 (struct soc_mixer_control *)kcontrol->private_value;
437 if (hp_dac_lim != max && hp_dac_lim >= 2 && hp_dac_lim <= 9)
441 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
443 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
446 uinfo->value.integer.min = 0;
447 uinfo->value.integer.max = max;
451 /* DAC and De-emphasis Filter Functions */
452 int aic3x_deemph_set_coeffs(struct snd_soc_codec *codec,
453 int N0, int N1, int D1){
454 printk("MNZ: setting deemph coeffs\n");
455 snd_soc_update_bits(codec, AIC3X_CODEC_DFILT_CTRL, DEEMPH_ON, 0);
457 aic3x_write_coeff(codec, DEEMPH_LEFT_N0, N0);
458 aic3x_write_coeff(codec, DEEMPH_LEFT_N1, N1);
459 aic3x_write_coeff(codec, DEEMPH_LEFT_D1, D1);
460 aic3x_write_coeff(codec, DEEMPH_RIGHT_N0, N0);
461 aic3x_write_coeff(codec, DEEMPH_RIGHT_N1, N1);
462 aic3x_write_coeff(codec, DEEMPH_RIGHT_D1, D1);
466 EXPORT_SYMBOL_GPL(aic3x_deemph_set_coeffs);
468 int aic3x_deemph_set_state(struct snd_soc_codec *codec, int state){
469 printk("MNZ: Setting De-Emph filter: %i\n", state);
470 if(state) state = DEEMPH_ON;
472 return snd_soc_update_bits(codec, AIC3X_CODEC_DFILT_CTRL,
475 EXPORT_SYMBOL_GPL(aic3x_deemph_set_state);
477 static int aic3x_dacfilter_write_coeffs
478 (struct snd_soc_codec *codec, struct aic3x_iir_coeffs *coeffs)
480 printk("MNZ: dacfilter_write_coeffs\n");
481 aic3x_write_coeff(codec, EFFECTS_LEFT_N0, coeffs->N0);
482 aic3x_write_coeff(codec, EFFECTS_LEFT_N1, coeffs->N1);
483 aic3x_write_coeff(codec, EFFECTS_LEFT_N2, coeffs->N2);
484 aic3x_write_coeff(codec, EFFECTS_LEFT_D1, coeffs->D1);
485 aic3x_write_coeff(codec, EFFECTS_LEFT_D2, coeffs->D2);
486 aic3x_write_coeff(codec, EFFECTS_LEFT_N3, coeffs->N3);
487 aic3x_write_coeff(codec, EFFECTS_LEFT_N4, coeffs->N4);
488 aic3x_write_coeff(codec, EFFECTS_LEFT_N5, coeffs->N5);
489 aic3x_write_coeff(codec, EFFECTS_LEFT_D4, coeffs->D4);
490 aic3x_write_coeff(codec, EFFECTS_LEFT_D5, coeffs->D5);
492 aic3x_write_coeff(codec, EFFECTS_RIGHT_N0, coeffs->N0);
493 aic3x_write_coeff(codec, EFFECTS_RIGHT_N1, coeffs->N1);
494 aic3x_write_coeff(codec, EFFECTS_RIGHT_N2, coeffs->N2);
495 aic3x_write_coeff(codec, EFFECTS_RIGHT_D1, coeffs->D1);
496 aic3x_write_coeff(codec, EFFECTS_RIGHT_D2, coeffs->D2);
497 aic3x_write_coeff(codec, EFFECTS_RIGHT_N3, coeffs->N3);
498 aic3x_write_coeff(codec, EFFECTS_RIGHT_N4, coeffs->N4);
499 aic3x_write_coeff(codec, EFFECTS_RIGHT_N5, coeffs->N5);
500 aic3x_write_coeff(codec, EFFECTS_RIGHT_D4, coeffs->D4);
501 aic3x_write_coeff(codec, EFFECTS_RIGHT_D5, coeffs->D5);
506 int aic3x_dacfilter_set_coeffs
507 (struct snd_soc_codec *codec, struct aic3x_iir_coeffs *coeffs)
509 struct aic3x_priv *aic3x = codec->private_data;
510 memcpy((void*)&aic3x->dacfilter.coeffs, (void*)coeffs,
511 sizeof(struct aic3x_iir_coeffs));
512 if(aic3x->dacfilter.state == 2)
513 aic3x_dacfilter_set_state(codec, 0);
516 EXPORT_SYMBOL_GPL(aic3x_dacfilter_set_coeffs);
518 int aic3x_dacfilter_set_state(struct snd_soc_codec *codec, int state)
520 printk("MNZ: dacfilter_set_state to %i\n", state);
521 struct aic3x_priv *aic3x = codec->private_data;
523 if(aic3x->dacfilter.state == state) return 0;
525 snd_soc_update_bits(codec, AIC3X_CODEC_DFILT_CTRL,
532 /* FIXME MNZ. Set preset from current chosen preset */
533 else if (state == 2){
534 ret = aic3x_dacfilter_write_coeffs(codec,
535 &aic3x->dacfilter.coeffs);
536 if(ret) snd_soc_update_bits(codec, AIC3X_CODEC_DFILT_CTRL,
537 EFFECTS_ON, EFFECTS_ON);
541 if(ret) aic3x->dacfilter.state = state;
545 EXPORT_SYMBOL_GPL(aic3x_dacfilter_set_state);
547 /* DAC Filter hwdep device callbacks */
549 static int snd_hwdep_dacfilter_open_aic3x(struct snd_hwdep *hw,
555 static int snd_hwdep_dacfilter_ioctl_aic3x(struct snd_hwdep *hw,
556 struct file *file, unsigned int cmd, unsigned long arg)
558 /* Only IOCTL command is for enabling/disabling filter, cmd = 1
559 * arg = 0 to disable, 1 to enable and set to bass/treble,
560 * 2 to enable and set to custom coeffs
562 struct snd_soc_codec *codec = hw->private_data;
563 if (cmd != 1) return -EINVAL;
564 printk("MNZ: IOCTL: cmd = %i, arg = %i\n", cmd, *((int*)arg));
565 return aic3x_dacfilter_set_state(codec, *((int*)arg));
568 static long snd_hwdep_dacfilter_read_aic3x(struct snd_hwdep *hw,
569 char __user *buf, long count, loff_t *offset)
571 struct aic3x_priv *aic3x =
572 ((struct snd_soc_codec*)hw->private_data)->private_data;
573 if(count != sizeof(struct aic3x_iir_coeffs)) return -EINVAL;
574 memcpy((void*)buf, (void*)&aic3x->dacfilter.coeffs, count);
578 static long snd_hwdep_dacfilter_write_aic3x(struct snd_hwdep *hw,
579 const char __user *buf, long count, loff_t *offset)
581 struct snd_soc_codec *codec = hw->private_data;
582 if(count != sizeof(struct aic3x_iir_coeffs)) return -EINVAL;
584 ((struct aic3x_priv*)codec->private_data)->dacfilter.state = 2;
586 return aic3x_dacfilter_set_coeffs(codec,
587 (struct aic3x_iir_coeffs*)buf);
590 /* DAC filter and 3D depth ALSA controls callbacks */
592 static int snd_soc_get_dacfilter_aic3x(struct snd_kcontrol *kcontrol,
593 struct snd_ctl_elem_value *ucontrol)
595 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
596 ucontrol->value.enumerated.item[0] =
597 ((struct aic3x_priv*)codec->private_data)->dacfilter.state;
601 static int snd_soc_put_dacfilter_aic3x(struct snd_kcontrol *kcontrol,
602 struct snd_ctl_elem_value *ucontrol)
604 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
605 if (ucontrol->value.enumerated.item[0] > 2)
607 aic3x_dacfilter_set_state(codec, ucontrol->value.enumerated.item[0]);
611 static int snd_soc_get_3d_attenuation_aic3x
612 (struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
614 int val = aic3x_read_coeff_reg_cache
615 (snd_kcontrol_chip(kcontrol), EFFECTS_3DATTEN);
616 val = ((val*100)/65530) + 50;
617 ucontrol->value.integer.value[0] = val;
621 static int snd_soc_put_3d_attenuation_aic3x
622 (struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
624 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
625 int val = ucontrol->value.integer.value[0];
626 if(val > 100 || val < 0) return -EINVAL;
629 snd_soc_update_bits(codec, AIC3X_ASD_INTF_CTRLA,
630 EFFECTS_3D_ON, EFFECTS_3D_ON);
631 val = ((val - 50) * 65535) / 100 ;
633 snd_soc_update_bits(codec, AIC3X_ASD_INTF_CTRLA,
638 aic3x_write_coeff(codec, EFFECTS_3DATTEN, val);
643 static const struct snd_kcontrol_new aic3x_snd_controls[] = {
645 SOC_DOUBLE_R_TLV("PCM Playback Volume",
646 LDAC_VOL, RDAC_VOL, 0, 0x7f, 1, dac_tlv),
648 SOC_DOUBLE_R_TLV("Line DAC Playback Volume",
649 DACL1_2_LLOPM_VOL, DACR1_2_RLOPM_VOL,
650 0, 118, 1, output_stage_tlv),
651 SOC_DOUBLE_R("Line DAC Playback Switch", LLOPM_CTRL, RLOPM_CTRL, 3,
653 SOC_DOUBLE_R_TLV("Line PGA Bypass Playback Volume",
654 PGAL_2_LLOPM_VOL, PGAR_2_RLOPM_VOL,
655 0, 118, 1, output_stage_tlv),
656 SOC_DOUBLE_R_TLV("Line Line2 Bypass Playback Volume",
657 LINE2L_2_LLOPM_VOL, LINE2R_2_RLOPM_VOL,
658 0, 118, 1, output_stage_tlv),
660 SOC_DOUBLE_R_TLV("Mono DAC Playback Volume",
661 DACL1_2_MONOLOPM_VOL, DACR1_2_MONOLOPM_VOL,
662 0, 118, 1, output_stage_tlv),
663 SOC_SINGLE("Mono DAC Playback Switch", MONOLOPM_CTRL, 3, 0x01, 0),
664 SOC_DOUBLE_R_TLV("Mono PGA Bypass Playback Volume",
665 PGAL_2_MONOLOPM_VOL, PGAR_2_MONOLOPM_VOL,
666 0, 118, 1, output_stage_tlv),
667 SOC_DOUBLE_R_TLV("Mono Line2 Bypass Playback Volume",
668 LINE2L_2_MONOLOPM_VOL, LINE2R_2_MONOLOPM_VOL,
669 0, 118, 1, output_stage_tlv),
671 SOC_DOUBLE_R_TLV("HP DAC Playback Volume",
672 DACL1_2_HPLOUT_VOL, DACR1_2_HPROUT_VOL,
673 0, 118, 1, output_stage_tlv),
674 SOC_DOUBLE_R("HP DAC Playback Switch", HPLOUT_CTRL, HPROUT_CTRL, 3,
676 SOC_DOUBLE_R_TLV_TLV320ALC3X("HP DAC Output Volume", HPLOUT_CTRL,
677 HPROUT_CTRL, 4, 9, 0, hpout_tlv),
678 SOC_DOUBLE_R_TLV("HP PGA Bypass Playback Volume",
679 PGAL_2_HPLOUT_VOL, PGAR_2_HPROUT_VOL,
680 0, 118, 1, output_stage_tlv),
681 SOC_DOUBLE_R_TLV("HP Line2 Bypass Playback Volume",
682 LINE2L_2_HPLOUT_VOL, LINE2R_2_HPROUT_VOL,
683 0, 118, 1, output_stage_tlv),
685 SOC_DOUBLE_R_TLV("HPCOM DAC Playback Volume",
686 DACL1_2_HPLCOM_VOL, DACR1_2_HPRCOM_VOL,
687 0, 118, 1, output_stage_tlv),
688 SOC_DOUBLE_R("HPCOM DAC Playback Switch", HPLCOM_CTRL, HPRCOM_CTRL, 3,
690 SOC_DOUBLE_R_TLV_TLV320ALC3X("HPCOM DAC Output Volume", HPLCOM_CTRL,
691 HPRCOM_CTRL, 4, 9, 0, hpout_tlv),
692 SOC_DOUBLE_R_TLV("HPCOM PGA Bypass Playback Volume",
693 PGAL_2_HPLCOM_VOL, PGAR_2_HPRCOM_VOL,
694 0, 118, 1, output_stage_tlv),
695 SOC_DOUBLE_R_TLV("HPCOM Line2 Bypass Playback Volume",
696 LINE2L_2_HPLCOM_VOL, LINE2R_2_HPRCOM_VOL,
697 0, 118, 1, output_stage_tlv),
700 * Note: enable Automatic input Gain Controller with care. It can
701 * adjust PGA to max value when ADC is on and will never go back.
703 SOC_DOUBLE_R("AGC Switch", LAGC_CTRL_A, RAGC_CTRL_A, 7, 0x01, 0),
706 SOC_DOUBLE_R_TLV("PGA Capture Volume", LADC_VOL, RADC_VOL,
708 SOC_DOUBLE_R("PGA Capture Switch", LADC_VOL, RADC_VOL, 7, 0x01, 1),
710 SOC_ENUM("ADC HPF Cut-off", aic3x_enum[ADC_HPF_ENUM]),
712 SOC_ENUM_EXT("Hardware EQ", aic3x_enum[DAC_FILT_ENUM],
713 snd_soc_get_dacfilter_aic3x, snd_soc_put_dacfilter_aic3x),
715 SOC_SINGLE_EXT("3D Control - Depth", EFFECTS_3DATTEN, 0, 100, 0,
716 snd_soc_get_3d_attenuation_aic3x, snd_soc_put_3d_attenuation_aic3x),
719 /* add non dapm controls */
720 static int aic3x_add_controls(struct snd_soc_codec *codec)
724 for (i = 0; i < ARRAY_SIZE(aic3x_snd_controls); i++) {
725 err = snd_ctl_add(codec->card,
726 snd_soc_cnew(&aic3x_snd_controls[i],
735 static int reset_after_bypass(struct snd_soc_dapm_widget *w,
736 struct snd_kcontrol *kcontrol, int event)
738 struct aic3x_priv *aic3x = w->codec->private_data;
739 struct soc_mixer_control *mc = NULL;
740 unsigned int reg = 0;
743 mc = (struct soc_mixer_control *)kcontrol->private_value;
747 if (reg == PGAL_2_LLOPM_VOL || reg == PGAR_2_RLOPM_VOL ||
748 reg == PGAL_2_HPLOUT_VOL || reg == PGAR_2_HPROUT_VOL) {
749 if (w->value & 0x80) {
750 /* Prepare reset on the chip */
751 if (reg == PGAL_2_LLOPM_VOL)
752 aic3x->prepare_reset |= 0x01;
753 else if (reg == PGAR_2_RLOPM_VOL)
754 aic3x->prepare_reset |= 0x02;
755 else if (reg == PGAL_2_HPLOUT_VOL)
756 aic3x->prepare_reset |= 0x04;
757 else if (reg == PGAR_2_HPROUT_VOL)
758 aic3x->prepare_reset |= 0x08;
760 if (aic3x->prepare_reset) {
761 if (reg == PGAL_2_LLOPM_VOL)
762 aic3x->prepare_reset &= ~0x01;
763 else if (reg == PGAR_2_RLOPM_VOL)
764 aic3x->prepare_reset &= ~0x02;
765 else if (reg == PGAL_2_HPLOUT_VOL)
766 aic3x->prepare_reset &= ~0x04;
767 else if (reg == PGAR_2_HPROUT_VOL)
768 aic3x->prepare_reset &= ~0x08;
770 * Controls may have now been turned off,
771 * once they were on, so schedule or
772 * issue a reset on the chip.
774 if (!aic3x->prepare_reset) {
775 if (!((w->codec->bias_level ==
777 (w->codec->bias_level ==
778 SND_SOC_BIAS_PREPARE)))
779 aic3x_reset(w->codec);
789 static const struct snd_kcontrol_new aic3x_left_dac_mux_controls =
790 SOC_DAPM_ENUM("Route", aic3x_enum[LDAC_ENUM]);
793 static const struct snd_kcontrol_new aic3x_right_dac_mux_controls =
794 SOC_DAPM_ENUM("Route", aic3x_enum[RDAC_ENUM]);
797 static const struct snd_kcontrol_new aic3x_left_hpcom_mux_controls =
798 SOC_DAPM_ENUM("Route", aic3x_enum[LHPCOM_ENUM]);
800 /* Right HPCOM Mux */
801 static const struct snd_kcontrol_new aic3x_right_hpcom_mux_controls =
802 SOC_DAPM_ENUM("Route", aic3x_enum[RHPCOM_ENUM]);
804 /* Left DAC_L1 Mixer */
805 static const struct snd_kcontrol_new aic3x_left_dac_mixer_controls[] = {
806 SOC_DAPM_SINGLE("Line Switch", DACL1_2_LLOPM_VOL, 7, 1, 0),
807 SOC_DAPM_SINGLE("Mono Switch", DACL1_2_MONOLOPM_VOL, 7, 1, 0),
808 SOC_DAPM_SINGLE("HP Switch", DACL1_2_HPLOUT_VOL, 7, 1, 0),
809 SOC_DAPM_SINGLE("HPCOM Switch", DACL1_2_HPLCOM_VOL, 7, 1, 0),
812 /* Right DAC_R1 Mixer */
813 static const struct snd_kcontrol_new aic3x_right_dac_mixer_controls[] = {
814 SOC_DAPM_SINGLE("Line Switch", DACR1_2_RLOPM_VOL, 7, 1, 0),
815 SOC_DAPM_SINGLE("Mono Switch", DACR1_2_MONOLOPM_VOL, 7, 1, 0),
816 SOC_DAPM_SINGLE("HP Switch", DACR1_2_HPROUT_VOL, 7, 1, 0),
817 SOC_DAPM_SINGLE("HPCOM Switch", DACR1_2_HPRCOM_VOL, 7, 1, 0),
821 static const struct snd_kcontrol_new aic3x_left_pga_mixer_controls[] = {
822 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_LADC_CTRL, 3, 1, 1),
823 SOC_DAPM_SINGLE_AIC3X("Line2L Switch", LINE2L_2_LADC_CTRL, 3, 1, 1),
824 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_LADC_CTRL, 4, 1, 1),
827 /* Right PGA Mixer */
828 static const struct snd_kcontrol_new aic3x_right_pga_mixer_controls[] = {
829 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_RADC_CTRL, 3, 1, 1),
830 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_RADC_CTRL, 3, 1, 1),
831 SOC_DAPM_SINGLE_AIC3X("Line2R Switch", LINE2R_2_RADC_CTRL, 3, 1, 1),
832 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_RADC_CTRL, 0, 1, 1),
836 static const struct snd_kcontrol_new aic3x_left_line1_mux_controls =
837 SOC_DAPM_ENUM("Route", aic3x_enum[LINE1L_ENUM]);
839 /* Right Line1 Mux */
840 static const struct snd_kcontrol_new aic3x_right_line1_mux_controls =
841 SOC_DAPM_ENUM("Route", aic3x_enum[LINE1R_ENUM]);
844 static const struct snd_kcontrol_new aic3x_left_line2_mux_controls =
845 SOC_DAPM_ENUM("Route", aic3x_enum[LINE2L_ENUM]);
847 /* Right Line2 Mux */
848 static const struct snd_kcontrol_new aic3x_right_line2_mux_controls =
849 SOC_DAPM_ENUM("Route", aic3x_enum[LINE2R_ENUM]);
851 /* Left PGA Bypass Mixer */
852 static const struct snd_kcontrol_new aic3x_left_pga_bp_mixer_controls[] = {
853 SOC_DAPM_SINGLE("Line Switch", PGAL_2_LLOPM_VOL, 7, 1, 0),
854 SOC_DAPM_SINGLE("Mono Switch", PGAL_2_MONOLOPM_VOL, 7, 1, 0),
855 SOC_DAPM_SINGLE("HP Switch", PGAL_2_HPLOUT_VOL, 7, 1, 0),
856 SOC_DAPM_SINGLE("HPCOM Switch", PGAL_2_HPLCOM_VOL, 7, 1, 0),
859 /* Right PGA Bypass Mixer */
860 static const struct snd_kcontrol_new aic3x_right_pga_bp_mixer_controls[] = {
861 SOC_DAPM_SINGLE("Line Switch", PGAR_2_RLOPM_VOL, 7, 1, 0),
862 SOC_DAPM_SINGLE("Mono Switch", PGAR_2_MONOLOPM_VOL, 7, 1, 0),
863 SOC_DAPM_SINGLE("HP Switch", PGAR_2_HPROUT_VOL, 7, 1, 0),
864 SOC_DAPM_SINGLE("HPCOM Switch", PGAR_2_HPRCOM_VOL, 7, 1, 0),
867 /* Left Line2 Bypass Mixer */
868 static const struct snd_kcontrol_new aic3x_left_line2_bp_mixer_controls[] = {
869 SOC_DAPM_SINGLE("Line Switch", LINE2L_2_LLOPM_VOL, 7, 1, 0),
870 SOC_DAPM_SINGLE("Mono Switch", LINE2L_2_MONOLOPM_VOL, 7, 1, 0),
871 SOC_DAPM_SINGLE("HP Switch", LINE2L_2_HPLOUT_VOL, 7, 1, 0),
872 SOC_DAPM_SINGLE("HPCOM Switch", LINE2L_2_HPLCOM_VOL, 7, 1, 0),
875 /* Right Line2 Bypass Mixer */
876 static const struct snd_kcontrol_new aic3x_right_line2_bp_mixer_controls[] = {
877 SOC_DAPM_SINGLE("Line Switch", LINE2R_2_RLOPM_VOL, 7, 1, 0),
878 SOC_DAPM_SINGLE("Mono Switch", LINE2R_2_MONOLOPM_VOL, 7, 1, 0),
879 SOC_DAPM_SINGLE("HP Switch", LINE2R_2_HPROUT_VOL, 7, 1, 0),
880 SOC_DAPM_SINGLE("HPCOM Switch", LINE2R_2_HPRCOM_VOL, 7, 1, 0),
883 static const struct snd_soc_dapm_widget aic3x_dapm_widgets[] = {
884 /* Left DAC to Left Outputs */
885 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", DAC_PWR, 7, 0),
886 SND_SOC_DAPM_MUX("Left DAC Mux", SND_SOC_NOPM, 0, 0,
887 &aic3x_left_dac_mux_controls),
888 SND_SOC_DAPM_MIXER("Left DAC_L1 Mixer", SND_SOC_NOPM, 0, 0,
889 &aic3x_left_dac_mixer_controls[0],
890 ARRAY_SIZE(aic3x_left_dac_mixer_controls)),
891 SND_SOC_DAPM_MUX("Left HPCOM Mux", SND_SOC_NOPM, 0, 0,
892 &aic3x_left_hpcom_mux_controls),
893 SND_SOC_DAPM_PGA("Left Line Out", LLOPM_CTRL, 0, 0, NULL, 0),
894 SND_SOC_DAPM_PGA("Left HP Out", HPLOUT_CTRL, 0, 0, NULL, 0),
895 SND_SOC_DAPM_PGA("Left HP Com", HPLCOM_CTRL, 0, 0, NULL, 0),
897 /* Right DAC to Right Outputs */
898 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", DAC_PWR, 6, 0),
899 SND_SOC_DAPM_MUX("Right DAC Mux", SND_SOC_NOPM, 0, 0,
900 &aic3x_right_dac_mux_controls),
901 SND_SOC_DAPM_MIXER("Right DAC_R1 Mixer", SND_SOC_NOPM, 0, 0,
902 &aic3x_right_dac_mixer_controls[0],
903 ARRAY_SIZE(aic3x_right_dac_mixer_controls)),
904 SND_SOC_DAPM_MUX("Right HPCOM Mux", SND_SOC_NOPM, 0, 0,
905 &aic3x_right_hpcom_mux_controls),
906 SND_SOC_DAPM_PGA("Right Line Out", RLOPM_CTRL, 0, 0, NULL, 0),
907 SND_SOC_DAPM_PGA("Right HP Out", HPROUT_CTRL, 0, 0, NULL, 0),
908 SND_SOC_DAPM_PGA("Right HP Com", HPRCOM_CTRL, 0, 0, NULL, 0),
911 SND_SOC_DAPM_PGA("Mono Out", MONOLOPM_CTRL, 0, 0, NULL, 0),
913 /* Left Inputs to Left ADC */
914 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", LINE1L_2_LADC_CTRL, 2, 0),
915 SND_SOC_DAPM_MIXER("Left PGA Mixer", SND_SOC_NOPM, 0, 0,
916 &aic3x_left_pga_mixer_controls[0],
917 ARRAY_SIZE(aic3x_left_pga_mixer_controls)),
918 SND_SOC_DAPM_MUX("Left Line1L Mux", SND_SOC_NOPM, 0, 0,
919 &aic3x_left_line1_mux_controls),
920 SND_SOC_DAPM_MUX("Left Line2L Mux", SND_SOC_NOPM, 0, 0,
921 &aic3x_left_line2_mux_controls),
923 /* Right Inputs to Right ADC */
924 SND_SOC_DAPM_ADC("Right ADC", "Right Capture",
925 LINE1R_2_RADC_CTRL, 2, 0),
926 SND_SOC_DAPM_MIXER("Right PGA Mixer", SND_SOC_NOPM, 0, 0,
927 &aic3x_right_pga_mixer_controls[0],
928 ARRAY_SIZE(aic3x_right_pga_mixer_controls)),
929 SND_SOC_DAPM_MUX("Right Line1L Mux", SND_SOC_NOPM, 0, 0,
930 &aic3x_right_line1_mux_controls),
931 SND_SOC_DAPM_MUX("Right Line1R Mux", SND_SOC_NOPM, 0, 0,
932 &aic3x_right_line1_mux_controls),
933 SND_SOC_DAPM_MUX("Right Line2R Mux", SND_SOC_NOPM, 0, 0,
934 &aic3x_right_line2_mux_controls),
937 * Not a real mic bias widget but similar function. This is for dynamic
938 * control of GPIO1 digital mic modulator clock output function when
941 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "GPIO1 dmic modclk",
942 AIC3X_GPIO1_REG, 4, 0xf,
943 AIC3X_GPIO1_FUNC_DIGITAL_MIC_MODCLK,
944 AIC3X_GPIO1_FUNC_DISABLED),
947 * Also similar function like mic bias. Selects digital mic with
948 * configurable oversampling rate instead of ADC converter.
950 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 128",
951 AIC3X_ASD_INTF_CTRLA, 0, 3, 1, 0),
952 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 64",
953 AIC3X_ASD_INTF_CTRLA, 0, 3, 2, 0),
954 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 32",
955 AIC3X_ASD_INTF_CTRLA, 0, 3, 3, 0),
958 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias 2V",
959 MICBIAS_CTRL, 6, 3, 1, 0),
960 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias 2.5V",
961 MICBIAS_CTRL, 6, 3, 2, 0),
962 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias AVDD",
963 MICBIAS_CTRL, 6, 3, 3, 0),
965 /* Left PGA to Left Output bypass */
966 SND_SOC_DAPM_MIXER_E("Left PGA Bypass Mixer", SND_SOC_NOPM, 0, 0,
967 &aic3x_left_pga_bp_mixer_controls[0],
968 ARRAY_SIZE(aic3x_left_pga_bp_mixer_controls),
969 reset_after_bypass, SND_SOC_DAPM_POST_REG),
971 /* Right PGA to Right Output bypass */
972 SND_SOC_DAPM_MIXER_E("Right PGA Bypass Mixer", SND_SOC_NOPM, 0, 0,
973 &aic3x_right_pga_bp_mixer_controls[0],
974 ARRAY_SIZE(aic3x_right_pga_bp_mixer_controls),
975 reset_after_bypass, SND_SOC_DAPM_POST_REG),
977 /* Left Line2 to Left Output bypass */
978 SND_SOC_DAPM_MIXER("Left Line2 Bypass Mixer", SND_SOC_NOPM, 0, 0,
979 &aic3x_left_line2_bp_mixer_controls[0],
980 ARRAY_SIZE(aic3x_left_line2_bp_mixer_controls)),
982 /* Right Line2 to Right Output bypass */
983 SND_SOC_DAPM_MIXER("Right Line2 Bypass Mixer", SND_SOC_NOPM, 0, 0,
984 &aic3x_right_line2_bp_mixer_controls[0],
985 ARRAY_SIZE(aic3x_right_line2_bp_mixer_controls)),
987 SND_SOC_DAPM_OUTPUT("LLOUT"),
988 SND_SOC_DAPM_OUTPUT("RLOUT"),
989 SND_SOC_DAPM_OUTPUT("MONO_LOUT"),
990 SND_SOC_DAPM_OUTPUT("HPLOUT"),
991 SND_SOC_DAPM_OUTPUT("HPROUT"),
992 SND_SOC_DAPM_OUTPUT("HPLCOM"),
993 SND_SOC_DAPM_OUTPUT("HPRCOM"),
995 SND_SOC_DAPM_INPUT("MIC3L"),
996 SND_SOC_DAPM_INPUT("MIC3R"),
997 SND_SOC_DAPM_INPUT("LINE1L"),
998 SND_SOC_DAPM_INPUT("LINE1R"),
999 SND_SOC_DAPM_INPUT("LINE2L"),
1000 SND_SOC_DAPM_INPUT("LINE2R"),
1003 static const struct snd_soc_dapm_route intercon[] = {
1005 {"Left DAC Mux", "DAC_L1", "Left DAC"},
1006 {"Left DAC Mux", "DAC_L2", "Left DAC"},
1007 {"Left DAC Mux", "DAC_L3", "Left DAC"},
1009 {"Left DAC_L1 Mixer", "Line Switch", "Left DAC Mux"},
1010 {"Left DAC_L1 Mixer", "Mono Switch", "Left DAC Mux"},
1011 {"Left DAC_L1 Mixer", "HP Switch", "Left DAC Mux"},
1012 {"Left DAC_L1 Mixer", "HPCOM Switch", "Left DAC Mux"},
1013 {"Left Line Out", NULL, "Left DAC Mux"},
1014 {"Left HP Out", NULL, "Left DAC Mux"},
1016 {"Left HPCOM Mux", "differential of HPLOUT", "Left DAC_L1 Mixer"},
1017 {"Left HPCOM Mux", "constant VCM", "Left DAC_L1 Mixer"},
1018 {"Left HPCOM Mux", "single-ended", "Left DAC_L1 Mixer"},
1020 {"Left Line Out", NULL, "Left DAC_L1 Mixer"},
1021 {"Mono Out", NULL, "Left DAC_L1 Mixer"},
1022 {"Left HP Out", NULL, "Left DAC_L1 Mixer"},
1023 {"Left HP Com", NULL, "Left HPCOM Mux"},
1025 {"LLOUT", NULL, "Left Line Out"},
1026 {"LLOUT", NULL, "Left Line Out"},
1027 {"HPLOUT", NULL, "Left HP Out"},
1028 {"HPLCOM", NULL, "Left HP Com"},
1031 {"Right DAC Mux", "DAC_R1", "Right DAC"},
1032 {"Right DAC Mux", "DAC_R2", "Right DAC"},
1033 {"Right DAC Mux", "DAC_R3", "Right DAC"},
1035 {"Right DAC_R1 Mixer", "Line Switch", "Right DAC Mux"},
1036 {"Right DAC_R1 Mixer", "Mono Switch", "Right DAC Mux"},
1037 {"Right DAC_R1 Mixer", "HP Switch", "Right DAC Mux"},
1038 {"Right DAC_R1 Mixer", "HPCOM Switch", "Right DAC Mux"},
1039 {"Right Line Out", NULL, "Right DAC Mux"},
1040 {"Right HP Out", NULL, "Right DAC Mux"},
1042 {"Right HPCOM Mux", "differential of HPROUT", "Right DAC_R1 Mixer"},
1043 {"Right HPCOM Mux", "constant VCM", "Right DAC_R1 Mixer"},
1044 {"Right HPCOM Mux", "single-ended", "Right DAC_R1 Mixer"},
1045 {"Right HPCOM Mux", "differential of HPLCOM", "Right DAC_R1 Mixer"},
1046 {"Right HPCOM Mux", "external feedback", "Right DAC_R1 Mixer"},
1048 {"Right Line Out", NULL, "Right DAC_R1 Mixer"},
1049 {"Mono Out", NULL, "Right DAC_R1 Mixer"},
1050 {"Right HP Out", NULL, "Right DAC_R1 Mixer"},
1051 {"Right HP Com", NULL, "Right HPCOM Mux"},
1053 {"RLOUT", NULL, "Right Line Out"},
1054 {"RLOUT", NULL, "Right Line Out"},
1055 {"HPROUT", NULL, "Right HP Out"},
1056 {"HPRCOM", NULL, "Right HP Com"},
1059 {"MONO_LOUT", NULL, "Mono Out"},
1060 {"MONO_LOUT", NULL, "Mono Out"},
1063 {"Left Line1L Mux", "single-ended", "LINE1L"},
1064 {"Left Line1L Mux", "differential", "LINE1L"},
1066 {"Left Line2L Mux", "single-ended", "LINE2L"},
1067 {"Left Line2L Mux", "differential", "LINE2L"},
1069 {"Left PGA Mixer", "Line1L Switch", "Left Line1L Mux"},
1070 {"Left PGA Mixer", "Line2L Switch", "Left Line2L Mux"},
1071 {"Left PGA Mixer", "Mic3L Switch", "MIC3L"},
1073 {"Left ADC", NULL, "Left PGA Mixer"},
1074 {"Left ADC", NULL, "GPIO1 dmic modclk"},
1077 {"Right Line1L Mux", "single-ended", "LINE1L"},
1078 {"Right Line1L Mux", "differential", "LINE1L"},
1080 {"Right Line1R Mux", "single-ended", "LINE1R"},
1081 {"Right Line1R Mux", "differential", "LINE1R"},
1083 {"Right Line2R Mux", "single-ended", "LINE2R"},
1084 {"Right Line2R Mux", "differential", "LINE2R"},
1086 {"Right PGA Mixer", "Line1L Switch", "Right Line1L Mux"},
1087 {"Right PGA Mixer", "Line1R Switch", "Right Line1R Mux"},
1088 {"Right PGA Mixer", "Line2R Switch", "Right Line2R Mux"},
1089 {"Right PGA Mixer", "Mic3R Switch", "MIC3R"},
1091 {"Right ADC", NULL, "Right PGA Mixer"},
1092 {"Right ADC", NULL, "GPIO1 dmic modclk"},
1094 /* Left PGA Bypass */
1095 {"Left PGA Bypass Mixer", "Line Switch", "Left PGA Mixer"},
1096 {"Left PGA Bypass Mixer", "Mono Switch", "Left PGA Mixer"},
1097 {"Left PGA Bypass Mixer", "HP Switch", "Left PGA Mixer"},
1098 {"Left PGA Bypass Mixer", "HPCOM Switch", "Left PGA Mixer"},
1100 {"Left HPCOM Mux", "differential of HPLOUT", "Left PGA Bypass Mixer"},
1101 {"Left HPCOM Mux", "constant VCM", "Left PGA Bypass Mixer"},
1102 {"Left HPCOM Mux", "single-ended", "Left PGA Bypass Mixer"},
1104 {"Left Line Out", NULL, "Left PGA Bypass Mixer"},
1105 {"Mono Out", NULL, "Left PGA Bypass Mixer"},
1106 {"Left HP Out", NULL, "Left PGA Bypass Mixer"},
1108 /* Right PGA Bypass */
1109 {"Right PGA Bypass Mixer", "Line Switch", "Right PGA Mixer"},
1110 {"Right PGA Bypass Mixer", "Mono Switch", "Right PGA Mixer"},
1111 {"Right PGA Bypass Mixer", "HP Switch", "Right PGA Mixer"},
1112 {"Right PGA Bypass Mixer", "HPCOM Switch", "Right PGA Mixer"},
1114 {"Right HPCOM Mux", "differential of HPROUT", "Right PGA Bypass Mixer"},
1115 {"Right HPCOM Mux", "constant VCM", "Right PGA Bypass Mixer"},
1116 {"Right HPCOM Mux", "single-ended", "Right PGA Bypass Mixer"},
1117 {"Right HPCOM Mux", "differential of HPLCOM", "Right PGA Bypass Mixer"},
1118 {"Right HPCOM Mux", "external feedback", "Right PGA Bypass Mixer"},
1120 {"Right Line Out", NULL, "Right PGA Bypass Mixer"},
1121 {"Mono Out", NULL, "Right PGA Bypass Mixer"},
1122 {"Right HP Out", NULL, "Right PGA Bypass Mixer"},
1124 /* Left Line2 Bypass */
1125 {"Left Line2 Bypass Mixer", "Line Switch", "Left Line2L Mux"},
1126 {"Left Line2 Bypass Mixer", "Mono Switch", "Left Line2L Mux"},
1127 {"Left Line2 Bypass Mixer", "HP Switch", "Left Line2L Mux"},
1128 {"Left Line2 Bypass Mixer", "HPCOM Switch", "Left Line2L Mux"},
1130 {"Left HPCOM Mux", "differential of HPLOUT", "Left Line2 Bypass Mixer"},
1131 {"Left HPCOM Mux", "constant VCM", "Left Line2 Bypass Mixer"},
1132 {"Left HPCOM Mux", "single-ended", "Left Line2 Bypass Mixer"},
1134 {"Left Line Out", NULL, "Left Line2 Bypass Mixer"},
1135 {"Mono Out", NULL, "Left Line2 Bypass Mixer"},
1136 {"Left HP Out", NULL, "Left Line2 Bypass Mixer"},
1138 /* Right Line2 Bypass */
1139 {"Right Line2 Bypass Mixer", "Line Switch", "Right Line2R Mux"},
1140 {"Right Line2 Bypass Mixer", "Mono Switch", "Right Line2R Mux"},
1141 {"Right Line2 Bypass Mixer", "HP Switch", "Right Line2R Mux"},
1142 {"Right Line2 Bypass Mixer", "HPCOM Switch", "Right Line2R Mux"},
1144 {"Right HPCOM Mux", "differential of HPROUT", "Right Line2 Bypass Mixer"},
1145 {"Right HPCOM Mux", "constant VCM", "Right Line2 Bypass Mixer"},
1146 {"Right HPCOM Mux", "single-ended", "Right Line2 Bypass Mixer"},
1147 {"Right HPCOM Mux", "differential of HPLCOM", "Right Line2 Bypass Mixer"},
1148 {"Right HPCOM Mux", "external feedback", "Right Line2 Bypass Mixer"},
1150 {"Right Line Out", NULL, "Right Line2 Bypass Mixer"},
1151 {"Mono Out", NULL, "Right Line2 Bypass Mixer"},
1152 {"Right HP Out", NULL, "Right Line2 Bypass Mixer"},
1155 * Logical path between digital mic enable and GPIO1 modulator clock
1158 {"GPIO1 dmic modclk", NULL, "DMic Rate 128"},
1159 {"GPIO1 dmic modclk", NULL, "DMic Rate 64"},
1160 {"GPIO1 dmic modclk", NULL, "DMic Rate 32"},
1163 static int aic3x_add_widgets(struct snd_soc_codec *codec)
1165 snd_soc_dapm_new_controls(codec, aic3x_dapm_widgets,
1166 ARRAY_SIZE(aic3x_dapm_widgets));
1168 /* set up audio path interconnects */
1169 snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
1171 snd_soc_dapm_new_widgets(codec);
1175 static int aic3x_hw_params(struct snd_pcm_substream *substream,
1176 struct snd_pcm_hw_params *params)
1178 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1179 struct snd_soc_device *socdev = rtd->socdev;
1180 struct snd_soc_codec *codec = socdev->codec;
1181 struct aic3x_priv *aic3x = codec->private_data;
1182 int codec_clk = 0, bypass_pll = 0, fsref, last_clk = 0;
1183 u8 data, r, p, pll_q, pll_p = 1, pll_r = 1, pll_j = 1;
1186 /* select data word length */
1188 aic3x_read_reg_cache(codec, AIC3X_ASD_INTF_CTRLB) & (~(0x3 << 4));
1189 switch (params_format(params)) {
1190 case SNDRV_PCM_FORMAT_S16_LE:
1192 case SNDRV_PCM_FORMAT_S20_3LE:
1193 data |= (0x01 << 4);
1195 case SNDRV_PCM_FORMAT_S24_LE:
1196 data |= (0x02 << 4);
1198 case SNDRV_PCM_FORMAT_S32_LE:
1199 data |= (0x03 << 4);
1202 aic3x_write(codec, AIC3X_ASD_INTF_CTRLB, data);
1204 /* Fsref can be 44100 or 48000 */
1205 fsref = (params_rate(params) % 11025 == 0) ? 44100 : 48000;
1207 /* Try to find a value for Q which allows us to bypass the PLL and
1208 * generate CODEC_CLK directly. */
1209 for (pll_q = 2; pll_q < 18; pll_q++)
1210 if (aic3x->sysclk / (128 * pll_q) == fsref) {
1217 aic3x_write(codec, AIC3X_PLL_PROGA_REG, pll_q << PLLQ_SHIFT);
1218 aic3x_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_CLKDIV);
1220 aic3x_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_PLLDIV);
1222 /* Route Left DAC to left channel input and
1223 * right DAC to right channel input */
1224 data = (LDAC2LCH | RDAC2RCH);
1225 data |= (fsref == 44100) ? FSREF_44100 : FSREF_48000;
1226 if (params_rate(params) >= 64000)
1227 data |= DUAL_RATE_MODE;
1228 aic3x_write(codec, AIC3X_CODEC_DATAPATH_REG, data);
1230 /* codec sample rate select */
1231 data = (fsref * 20) / params_rate(params);
1232 if (params_rate(params) < 64000)
1236 data |= (data << 4);
1237 aic3x_write(codec, AIC3X_SAMPLE_RATE_SEL_REG, data);
1243 * find an apropriate setup for j, d, r and p by iterating over
1244 * p and r - j and d are calculated for each fraction.
1245 * Up to 128 values are probed, the closest one wins the game.
1246 * The sysclk is divided by 1000 to prevent integer overflows.
1248 codec_clk = (2048 * fsref) / (aic3x->sysclk / 1000);
1250 for (r = 1; r <= 16; r++)
1251 for (p = 1; p <= 8; p++) {
1252 int clk, tmp = (codec_clk * pll_r * 10) / pll_p;
1254 u16 d = tmp % 10000;
1259 if (d != 0 && aic3x->sysclk < 10000000)
1262 /* This is actually 1000 * ((j + (d/10000)) * r) / p
1263 * The term had to be converted to get rid of the
1264 * division by 10000 */
1265 clk = ((10000 * j * r) + (d * r)) / (10 * p);
1267 /* check whether this values get closer than the best
1268 * ones we had before */
1269 if (abs(codec_clk - clk) < abs(codec_clk - last_clk)) {
1270 pll_j = j; pll_d = d; pll_r = r; pll_p = p;
1274 /* Early exit for exact matches */
1275 if (clk == codec_clk)
1279 if (last_clk == 0) {
1280 printk(KERN_ERR "%s(): unable to setup PLL\n", __func__);
1284 data = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
1285 aic3x_write(codec, AIC3X_PLL_PROGA_REG, data | (pll_p << PLLP_SHIFT));
1286 aic3x_write(codec, AIC3X_OVRF_STATUS_AND_PLLR_REG, pll_r << PLLR_SHIFT);
1287 aic3x_write(codec, AIC3X_PLL_PROGB_REG, pll_j << PLLJ_SHIFT);
1288 aic3x_write(codec, AIC3X_PLL_PROGC_REG, (pll_d >> 6) << PLLD_MSB_SHIFT);
1289 aic3x_write(codec, AIC3X_PLL_PROGD_REG,
1290 (pll_d & 0x3F) << PLLD_LSB_SHIFT);
1295 static int aic3x_mute(struct snd_soc_dai *dai, int mute)
1297 struct snd_soc_codec *codec = dai->codec;
1298 u8 ldac_reg = aic3x_read_reg_cache(codec, LDAC_VOL) & ~MUTE_ON;
1299 u8 rdac_reg = aic3x_read_reg_cache(codec, RDAC_VOL) & ~MUTE_ON;
1302 aic3x_write(codec, LDAC_VOL, ldac_reg | MUTE_ON);
1303 aic3x_write(codec, RDAC_VOL, rdac_reg | MUTE_ON);
1305 aic3x_write(codec, LDAC_VOL, ldac_reg);
1306 aic3x_write(codec, RDAC_VOL, rdac_reg);
1312 static int aic3x_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1313 int clk_id, unsigned int freq, int dir)
1315 struct snd_soc_codec *codec = codec_dai->codec;
1316 struct aic3x_priv *aic3x = codec->private_data;
1318 aic3x->sysclk = freq;
1322 static int aic3x_set_dai_fmt(struct snd_soc_dai *codec_dai,
1325 struct snd_soc_codec *codec = codec_dai->codec;
1326 struct aic3x_priv *aic3x = codec->private_data;
1327 u8 iface_areg, iface_breg;
1330 iface_areg = aic3x_read_reg_cache(codec, AIC3X_ASD_INTF_CTRLA) & 0x3f;
1331 iface_breg = aic3x_read_reg_cache(codec, AIC3X_ASD_INTF_CTRLB) & 0x3f;
1333 /* set master/slave audio interface */
1334 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1335 case SND_SOC_DAIFMT_CBM_CFM:
1337 iface_areg |= BIT_CLK_MASTER | WORD_CLK_MASTER;
1339 case SND_SOC_DAIFMT_CBS_CFS:
1347 * match both interface format and signal polarities since they
1350 switch (fmt & (SND_SOC_DAIFMT_FORMAT_MASK |
1351 SND_SOC_DAIFMT_INV_MASK)) {
1352 case (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF):
1354 case (SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_IB_NF):
1356 case (SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_IB_NF):
1357 iface_breg |= (0x01 << 6);
1359 case (SND_SOC_DAIFMT_RIGHT_J | SND_SOC_DAIFMT_NB_NF):
1360 iface_breg |= (0x02 << 6);
1362 case (SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_NB_NF):
1363 iface_breg |= (0x03 << 6);
1370 aic3x_write(codec, AIC3X_ASD_INTF_CTRLA, iface_areg);
1371 aic3x_write(codec, AIC3X_ASD_INTF_CTRLB, iface_breg);
1372 aic3x_write(codec, AIC3X_ASD_INTF_CTRLC, delay);
1377 static int aic3x_set_bias_level(struct snd_soc_codec *codec,
1378 enum snd_soc_bias_level level)
1380 struct aic3x_priv *aic3x = codec->private_data;
1384 case SND_SOC_BIAS_ON:
1385 /* all power is driven by DAPM system */
1386 if (aic3x->master) {
1388 reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
1389 aic3x_write(codec, AIC3X_PLL_PROGA_REG,
1392 * ensure that bit and word clocks are running also if
1393 * DAC and ADC are shutdown
1395 reg = aic3x_read_reg_cache(codec, AIC3X_ASD_INTF_CTRLA);
1396 aic3x_write(codec, AIC3X_ASD_INTF_CTRLA, reg | 0x10);
1399 case SND_SOC_BIAS_PREPARE:
1401 case SND_SOC_BIAS_STANDBY:
1403 * all power is driven by DAPM system,
1404 * so output power is safe if bypass was set
1406 if (aic3x->master) {
1407 reg = aic3x_read_reg_cache(codec, AIC3X_ASD_INTF_CTRLA);
1408 aic3x_write(codec, AIC3X_ASD_INTF_CTRLA, reg & ~0x10);
1410 reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
1411 aic3x_write(codec, AIC3X_PLL_PROGA_REG,
1414 /* Reset cannot be issued, if bypass paths are in use */
1415 if (!aic3x->prepare_reset)
1418 case SND_SOC_BIAS_OFF:
1419 /* force all power off */
1420 reg = aic3x_read_reg_cache(codec, LINE1L_2_LADC_CTRL);
1421 aic3x_write(codec, LINE1L_2_LADC_CTRL, reg & ~LADC_PWR_ON);
1422 reg = aic3x_read_reg_cache(codec, LINE1R_2_RADC_CTRL);
1423 aic3x_write(codec, LINE1R_2_RADC_CTRL, reg & ~RADC_PWR_ON);
1425 reg = aic3x_read_reg_cache(codec, DAC_PWR);
1426 aic3x_write(codec, DAC_PWR, reg & ~(LDAC_PWR_ON | RDAC_PWR_ON));
1428 reg = aic3x_read_reg_cache(codec, HPLOUT_CTRL);
1429 aic3x_write(codec, HPLOUT_CTRL, reg & ~HPLOUT_PWR_ON);
1430 reg = aic3x_read_reg_cache(codec, HPROUT_CTRL);
1431 aic3x_write(codec, HPROUT_CTRL, reg & ~HPROUT_PWR_ON);
1433 reg = aic3x_read_reg_cache(codec, HPLCOM_CTRL);
1434 aic3x_write(codec, HPLCOM_CTRL, reg & ~HPLCOM_PWR_ON);
1435 reg = aic3x_read_reg_cache(codec, HPRCOM_CTRL);
1436 aic3x_write(codec, HPRCOM_CTRL, reg & ~HPRCOM_PWR_ON);
1438 reg = aic3x_read_reg_cache(codec, MONOLOPM_CTRL);
1439 aic3x_write(codec, MONOLOPM_CTRL, reg & ~MONOLOPM_PWR_ON);
1441 reg = aic3x_read_reg_cache(codec, LLOPM_CTRL);
1442 aic3x_write(codec, LLOPM_CTRL, reg & ~LLOPM_PWR_ON);
1443 reg = aic3x_read_reg_cache(codec, RLOPM_CTRL);
1444 aic3x_write(codec, RLOPM_CTRL, reg & ~RLOPM_PWR_ON);
1446 if (aic3x->master) {
1447 reg = aic3x_read_reg_cache(codec, AIC3X_ASD_INTF_CTRLA);
1448 aic3x_write(codec, AIC3X_ASD_INTF_CTRLA, reg & ~0x10);
1450 reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
1451 aic3x_write(codec, AIC3X_PLL_PROGA_REG,
1456 codec->bias_level = level;
1461 void aic3x_set_gpio(struct snd_soc_codec *codec, int gpio, int state)
1463 u8 reg = gpio ? AIC3X_GPIO2_REG : AIC3X_GPIO1_REG;
1464 u8 bit = gpio ? 3: 0;
1465 u8 val = aic3x_read_reg_cache(codec, reg) & ~(1 << bit);
1466 aic3x_write(codec, reg, val | (!!state << bit));
1468 EXPORT_SYMBOL_GPL(aic3x_set_gpio);
1470 int aic3x_get_gpio(struct snd_soc_codec *codec, int gpio)
1472 u8 reg = gpio ? AIC3X_GPIO2_REG : AIC3X_GPIO1_REG;
1473 u8 val, bit = gpio ? 2: 1;
1475 aic3x_read(codec, reg, &val);
1476 return (val >> bit) & 1;
1478 EXPORT_SYMBOL_GPL(aic3x_get_gpio);
1480 int aic3x_headset_detected(struct snd_soc_codec *codec)
1483 aic3x_read(codec, AIC3X_RT_IRQ_FLAGS_REG, &val);
1484 return (val >> 2) & 1;
1486 EXPORT_SYMBOL_GPL(aic3x_headset_detected);
1488 #define AIC3X_RATES SNDRV_PCM_RATE_8000_96000
1489 #define AIC3X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1490 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
1492 struct snd_soc_dai aic3x_dai = {
1493 .name = "tlv320aic3x",
1495 .stream_name = "Playback",
1498 .rates = AIC3X_RATES,
1499 .formats = AIC3X_FORMATS,},
1501 .stream_name = "Capture",
1504 .rates = AIC3X_RATES,
1505 .formats = AIC3X_FORMATS,},
1507 .hw_params = aic3x_hw_params,
1510 .digital_mute = aic3x_mute,
1511 .set_sysclk = aic3x_set_dai_sysclk,
1512 .set_fmt = aic3x_set_dai_fmt,
1515 EXPORT_SYMBOL_GPL(aic3x_dai);
1517 static int aic3x_suspend(struct platform_device *pdev, pm_message_t state)
1519 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1520 struct snd_soc_codec *codec = socdev->codec;
1522 aic3x_write(codec, AIC3X_RESET, SOFT_RESET);
1527 static int aic3x_resume(struct platform_device *pdev)
1529 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1530 aic3x_sync_hw(socdev->codec);
1531 aic3x_set_bias_level(socdev->codec,
1532 socdev->codec->suspend_bias_level);
1538 * initialise the AIC3X driver
1539 * register the mixer and dsp interfaces with the kernel
1541 static int aic3x_init(struct snd_soc_device *socdev)
1543 struct snd_soc_codec *codec = socdev->codec;
1544 struct aic3x_setup_data *setup = socdev->codec_data;
1545 struct snd_hwdep *hwdep;
1546 char hwdepid[] = "IIR Filter";
1549 printk("MNZ: BEGIN aic3x_init\n");
1550 codec->name = "tlv320aic3x";
1551 codec->owner = THIS_MODULE;
1552 codec->read = aic3x_read_reg_cache;
1553 codec->write = aic3x_write;
1554 codec->set_bias_level = aic3x_set_bias_level;
1555 codec->dai = &aic3x_dai;
1557 codec->reg_cache_size = ARRAY_SIZE(aic3x_reg);
1558 codec->reg_cache = kmemdup(aic3x_reg, sizeof(aic3x_reg), GFP_KERNEL);
1559 if (codec->reg_cache == NULL)
1562 aic3x_write(codec, AIC3X_PAGE_SELECT, PAGE0_SELECT);
1563 aic3x_write(codec, AIC3X_RESET, SOFT_RESET);
1566 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
1568 printk(KERN_ERR "aic3x: failed to create pcms\n");
1572 /* DAC default volume and mute */
1573 aic3x_write(codec, LDAC_VOL, DEFAULT_VOL | MUTE_ON);
1574 aic3x_write(codec, RDAC_VOL, DEFAULT_VOL | MUTE_ON);
1576 /* DAC to HP default volume and route to Output mixer */
1577 aic3x_write(codec, DACL1_2_HPLOUT_VOL, DEFAULT_VOL | ROUTE_ON);
1578 aic3x_write(codec, DACR1_2_HPROUT_VOL, DEFAULT_VOL | ROUTE_ON);
1579 aic3x_write(codec, DACL1_2_HPLCOM_VOL, DEFAULT_VOL | ROUTE_ON);
1580 aic3x_write(codec, DACR1_2_HPRCOM_VOL, DEFAULT_VOL | ROUTE_ON);
1581 /* DAC to Line Out default volume and route to Output mixer */
1582 aic3x_write(codec, DACL1_2_LLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1583 aic3x_write(codec, DACR1_2_RLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1584 /* DAC to Mono Line Out default volume and route to Output mixer */
1585 aic3x_write(codec, DACL1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1586 aic3x_write(codec, DACR1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1588 /* unmute all outputs */
1589 reg = aic3x_read_reg_cache(codec, LLOPM_CTRL);
1590 aic3x_write(codec, LLOPM_CTRL, reg | UNMUTE);
1591 reg = aic3x_read_reg_cache(codec, RLOPM_CTRL);
1592 aic3x_write(codec, RLOPM_CTRL, reg | UNMUTE);
1593 reg = aic3x_read_reg_cache(codec, MONOLOPM_CTRL);
1594 aic3x_write(codec, MONOLOPM_CTRL, reg | UNMUTE);
1595 reg = aic3x_read_reg_cache(codec, HPLOUT_CTRL);
1596 aic3x_write(codec, HPLOUT_CTRL, reg | UNMUTE);
1597 reg = aic3x_read_reg_cache(codec, HPROUT_CTRL);
1598 aic3x_write(codec, HPROUT_CTRL, reg | UNMUTE);
1599 reg = aic3x_read_reg_cache(codec, HPLCOM_CTRL);
1600 aic3x_write(codec, HPLCOM_CTRL, reg | UNMUTE);
1601 reg = aic3x_read_reg_cache(codec, HPRCOM_CTRL);
1602 aic3x_write(codec, HPRCOM_CTRL, reg | UNMUTE);
1604 /* ADC default volume and unmute */
1605 aic3x_write(codec, LADC_VOL, DEFAULT_GAIN);
1606 aic3x_write(codec, RADC_VOL, DEFAULT_GAIN);
1607 /* By default route Line1 to ADC PGA mixer */
1608 aic3x_write(codec, LINE1L_2_LADC_CTRL, 0x0);
1609 aic3x_write(codec, LINE1R_2_RADC_CTRL, 0x0);
1611 /* PGA to HP Bypass default volume, disconnect from Output Mixer */
1612 aic3x_write(codec, PGAL_2_HPLOUT_VOL, DEFAULT_VOL);
1613 aic3x_write(codec, PGAR_2_HPROUT_VOL, DEFAULT_VOL);
1614 aic3x_write(codec, PGAL_2_HPLCOM_VOL, DEFAULT_VOL);
1615 aic3x_write(codec, PGAR_2_HPRCOM_VOL, DEFAULT_VOL);
1616 /* PGA to Line Out default volume, disconnect from Output Mixer */
1617 aic3x_write(codec, PGAL_2_LLOPM_VOL, DEFAULT_VOL);
1618 aic3x_write(codec, PGAR_2_RLOPM_VOL, DEFAULT_VOL);
1619 /* PGA to Mono Line Out default volume, disconnect from Output Mixer */
1620 aic3x_write(codec, PGAL_2_MONOLOPM_VOL, DEFAULT_VOL);
1621 aic3x_write(codec, PGAR_2_MONOLOPM_VOL, DEFAULT_VOL);
1623 /* Line2 to HP Bypass default volume, disconnect from Output Mixer */
1624 aic3x_write(codec, LINE2L_2_HPLOUT_VOL, DEFAULT_VOL);
1625 aic3x_write(codec, LINE2R_2_HPROUT_VOL, DEFAULT_VOL);
1626 aic3x_write(codec, LINE2L_2_HPLCOM_VOL, DEFAULT_VOL);
1627 aic3x_write(codec, LINE2R_2_HPRCOM_VOL, DEFAULT_VOL);
1628 /* Line2 Line Out default volume, disconnect from Output Mixer */
1629 aic3x_write(codec, LINE2L_2_LLOPM_VOL, DEFAULT_VOL);
1630 aic3x_write(codec, LINE2R_2_RLOPM_VOL, DEFAULT_VOL);
1631 /* Line2 to Mono Out default volume, disconnect from Output Mixer */
1632 aic3x_write(codec, LINE2L_2_MONOLOPM_VOL, DEFAULT_VOL);
1633 aic3x_write(codec, LINE2R_2_MONOLOPM_VOL, DEFAULT_VOL);
1635 /* off, with power on */
1636 aic3x_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1638 /* setup GPIO functions */
1639 aic3x_write(codec, AIC3X_GPIO1_REG, (setup->gpio_func[0] & 0xf) << 4);
1640 aic3x_write(codec, AIC3X_GPIO2_REG, (setup->gpio_func[1] & 0xf) << 4);
1642 aic3x_add_controls(codec);
1643 aic3x_add_widgets(codec);
1645 if(snd_hwdep_new(codec->card, hwdepid, 0, &hwdep) == 0){
1646 hwdep->private_data = codec;
1647 sprintf(hwdep->name, hwdepid);
1648 hwdep->ops.open = snd_hwdep_dacfilter_open_aic3x;
1649 hwdep->ops.ioctl = snd_hwdep_dacfilter_ioctl_aic3x;
1650 hwdep->ops.read = snd_hwdep_dacfilter_read_aic3x;
1651 hwdep->ops.write = snd_hwdep_dacfilter_write_aic3x;
1652 ((struct aic3x_priv*)codec->private_data)->hwdep = hwdep;
1655 ret = snd_soc_register_card(socdev);
1658 printk(KERN_ERR "aic3x: failed to register card\n");
1662 /* Set some defaults for coefficients */
1663 aic3x_write_coeff(codec, EFFECTS_3DATTEN, -32768);
1664 printk("MNZ: END aic3x_init\n");
1669 snd_soc_free_pcms(socdev);
1670 snd_soc_dapm_free(socdev);
1672 kfree(codec->reg_cache);
1676 static struct snd_soc_device *aic3x_socdev;
1678 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1680 * AIC3X 2 wire address can be up to 4 devices with device addresses
1681 * 0x18, 0x19, 0x1A, 0x1B
1685 * If the i2c layer weren't so broken, we could pass this kind of data
1688 static int aic3x_i2c_probe(struct i2c_client *i2c,
1689 const struct i2c_device_id *id)
1691 struct snd_soc_device *socdev = aic3x_socdev;
1692 struct snd_soc_codec *codec = socdev->codec;
1695 i2c_set_clientdata(i2c, codec);
1696 codec->control_data = i2c;
1698 ret = aic3x_init(socdev);
1700 printk(KERN_ERR "aic3x: failed to initialise AIC3X\n");
1704 static int aic3x_i2c_remove(struct i2c_client *client)
1706 struct snd_soc_codec *codec = i2c_get_clientdata(client);
1707 kfree(codec->reg_cache);
1711 static const struct i2c_device_id aic3x_i2c_id[] = {
1712 { "tlv320aic3x", 0 },
1715 MODULE_DEVICE_TABLE(i2c, aic3x_i2c_id);
1717 /* machine i2c codec control layer */
1718 static struct i2c_driver aic3x_i2c_driver = {
1720 .name = "aic3x I2C Codec",
1721 .owner = THIS_MODULE,
1723 .probe = aic3x_i2c_probe,
1724 .remove = aic3x_i2c_remove,
1725 .id_table = aic3x_i2c_id,
1728 static int aic3x_i2c_read(struct i2c_client *client, u8 *value, int len)
1730 value[0] = i2c_smbus_read_byte_data(client, value[0]);
1734 static int aic3x_add_i2c_device(struct platform_device *pdev,
1735 const struct aic3x_setup_data *setup)
1737 struct i2c_board_info info;
1738 struct i2c_adapter *adapter;
1739 struct i2c_client *client;
1742 ret = i2c_add_driver(&aic3x_i2c_driver);
1744 dev_err(&pdev->dev, "can't add i2c driver\n");
1748 memset(&info, 0, sizeof(struct i2c_board_info));
1749 info.addr = setup->i2c_address;
1750 strlcpy(info.type, "tlv320aic3x", I2C_NAME_SIZE);
1752 adapter = i2c_get_adapter(setup->i2c_bus);
1754 dev_err(&pdev->dev, "can't get i2c adapter %d\n",
1759 client = i2c_new_device(adapter, &info);
1760 i2c_put_adapter(adapter);
1762 dev_err(&pdev->dev, "can't add i2c device at 0x%x\n",
1763 (unsigned int)info.addr);
1770 i2c_del_driver(&aic3x_i2c_driver);
1775 static int aic3x_probe(struct platform_device *pdev)
1777 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1778 struct aic3x_setup_data *setup;
1779 struct snd_soc_codec *codec;
1780 struct aic3x_priv *aic3x;
1783 printk(KERN_INFO "AIC3X Audio Codec %s\n", AIC3X_VERSION);
1785 setup = socdev->codec_data;
1786 codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
1790 aic3x = kzalloc(sizeof(struct aic3x_priv), GFP_KERNEL);
1791 memcpy(&aic3x->dacfilter, &aic3x_dacfilter, sizeof(aic3x_dacfilter));
1793 if (aic3x == NULL) {
1798 codec->private_data = aic3x;
1799 socdev->codec = codec;
1800 mutex_init(&codec->mutex);
1801 INIT_LIST_HEAD(&codec->dapm_widgets);
1802 INIT_LIST_HEAD(&codec->dapm_paths);
1804 aic3x_socdev = socdev;
1805 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1806 if (setup->i2c_address) {
1807 codec->hw_write = (hw_write_t) i2c_master_send;
1808 codec->hw_read = (hw_read_t) aic3x_i2c_read;
1809 ret = aic3x_add_i2c_device(pdev, setup);
1812 /* Add other interfaces here */
1816 kfree(codec->private_data);
1822 static int aic3x_remove(struct platform_device *pdev)
1824 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1825 struct snd_soc_codec *codec = socdev->codec;
1827 /* power down chip */
1828 if (codec->control_data)
1829 aic3x_set_bias_level(codec, SND_SOC_BIAS_OFF);
1831 snd_soc_free_pcms(socdev);
1832 snd_soc_dapm_free(socdev);
1833 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1834 if (codec->control_data)
1835 i2c_unregister_device(codec->control_data);
1836 i2c_del_driver(&aic3x_i2c_driver);
1838 kfree(codec->private_data);
1844 struct snd_soc_codec_device soc_codec_dev_aic3x = {
1845 .probe = aic3x_probe,
1846 .remove = aic3x_remove,
1847 .suspend = aic3x_suspend,
1848 .resume = aic3x_resume,
1850 EXPORT_SYMBOL_GPL(soc_codec_dev_aic3x);
1852 MODULE_DESCRIPTION("ASoC TLV320AIC3X codec driver");
1853 MODULE_AUTHOR("Vladimir Barinov");
1854 MODULE_LICENSE("GPL");