2 * ALSA SoC TLV320AIC3X codec driver
4 * Author: Vladimir Barinov, <vbarinov@embeddedalley.com>
5 * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
15 /* AIC3X register space */
16 #define AIC3X_CACHEREGNUM 205
17 #define AIC3X_PAGE0REGNUM 103
18 #define AIC3X_PAGE1REGNUM 77
20 #define AIC3X_COEFF_CACHE_SIZE 52
21 #define COEFF_OFFSET(msbreg) ((msbreg+1)/2)
23 /* Page select register */
24 #define AIC3X_PAGE_SELECT 0
25 /* Software reset register */
27 /* Codec Sample rate select register */
28 #define AIC3X_SAMPLE_RATE_SEL_REG 2
29 /* PLL progrramming register A */
30 #define AIC3X_PLL_PROGA_REG 3
31 /* PLL progrramming register B */
32 #define AIC3X_PLL_PROGB_REG 4
33 /* PLL progrramming register C */
34 #define AIC3X_PLL_PROGC_REG 5
35 /* PLL progrramming register D */
36 #define AIC3X_PLL_PROGD_REG 6
37 /* Codec datapath setup register */
38 #define AIC3X_CODEC_DATAPATH_REG 7
39 /* Audio serial data interface control register A */
40 #define AIC3X_ASD_INTF_CTRLA 8
41 /* Audio serial data interface control register B */
42 #define AIC3X_ASD_INTF_CTRLB 9
43 /* Audio serial data interface control register C */
44 #define AIC3X_ASD_INTF_CTRLC 10
45 /* Audio overflow status and PLL R value programming register */
46 #define AIC3X_OVRF_STATUS_AND_PLLR_REG 11
47 /* Audio codec digital filter control register */
48 #define AIC3X_CODEC_DFILT_CTRL 12
50 /* ADC PGA Gain control registers */
53 /* MIC3 control registers */
54 #define MIC3LR_2_LADC_CTRL 17
55 #define MIC3LR_2_RADC_CTRL 18
56 /* Line1 Input control registers */
57 #define LINE1L_2_LADC_CTRL 19
58 #define LINE1R_2_RADC_CTRL 22
59 #define LINE1L_2_RADC_CTRL 24
60 /* Line2 Input control registers */
61 #define LINE2L_2_LADC_CTRL 20
62 #define LINE2R_2_RADC_CTRL 23
63 /* MICBIAS Control Register */
64 #define MICBIAS_CTRL 25
66 /* AGC Control Registers A, B, C */
67 #define LAGC_CTRL_A 26
68 #define LAGC_CTRL_B 27
69 #define LAGC_CTRL_C 28
70 #define RAGC_CTRL_A 29
71 #define RAGC_CTRL_B 30
72 #define RAGC_CTRL_C 31
74 /* DAC Power and Left High Power Output control registers */
77 /* Right High Power Output control registers */
79 /* DAC Output Switching control registers */
80 #define DAC_LINE_MUX 41
81 /* High Power Output Driver Pop Reduction registers */
82 #define HPOUT_POP_REDUCTION 42
83 /* DAC Digital control registers */
86 /* High Power Output control registers */
87 #define LINE2L_2_HPLOUT_VOL 45
88 #define LINE2R_2_HPROUT_VOL 62
89 #define PGAL_2_HPLOUT_VOL 46
90 #define PGAR_2_HPROUT_VOL 63
91 #define DACL1_2_HPLOUT_VOL 47
92 #define DACR1_2_HPROUT_VOL 64
93 #define HPLOUT_CTRL 51
94 #define HPROUT_CTRL 65
95 /* High Power COM control registers */
96 #define LINE2L_2_HPLCOM_VOL 52
97 #define LINE2R_2_HPRCOM_VOL 69
98 #define PGAL_2_HPLCOM_VOL 53
99 #define PGAR_2_HPRCOM_VOL 70
100 #define DACL1_2_HPLCOM_VOL 54
101 #define DACR1_2_HPRCOM_VOL 71
102 #define HPLCOM_CTRL 58
103 #define HPRCOM_CTRL 72
104 /* Mono Line Output Plus/Minus control registers */
105 #define LINE2L_2_MONOLOPM_VOL 73
106 #define LINE2R_2_MONOLOPM_VOL 76
107 #define PGAL_2_MONOLOPM_VOL 74
108 #define PGAR_2_MONOLOPM_VOL 77
109 #define DACL1_2_MONOLOPM_VOL 75
110 #define DACR1_2_MONOLOPM_VOL 78
111 #define MONOLOPM_CTRL 79
112 /* Line Output Plus/Minus control registers */
113 #define LINE2L_2_LLOPM_VOL 80
114 #define LINE2R_2_RLOPM_VOL 90
115 #define PGAL_2_LLOPM_VOL 81
116 #define PGAR_2_RLOPM_VOL 91
117 #define DACL1_2_LLOPM_VOL 82
118 #define DACR1_2_RLOPM_VOL 92
119 #define LLOPM_CTRL 86
120 #define RLOPM_CTRL 93
121 /* GPIO/IRQ registers */
122 #define AIC3X_STICKY_IRQ_FLAGS_REG 96
123 #define AIC3X_RT_IRQ_FLAGS_REG 97
124 #define AIC3X_GPIO1_REG 98
125 #define AIC3X_GPIO2_REG 99
126 #define AIC3X_GPIOA_REG 100
127 #define AIC3X_GPIOB_REG 101
128 /* Clock generation control register */
129 #define AIC3X_CLKGEN_CTRL_REG 102
131 /* Page 1 registers for setting coefficients for filters */
132 /* DAC Audio Effects for Left Channel */
133 #define EFFECTS_LEFT_N0 129
134 #define EFFECTS_LEFT_N1 131
135 #define EFFECTS_LEFT_N2 133
136 #define EFFECTS_LEFT_N3 135
137 #define EFFECTS_LEFT_N4 137
138 #define EFFECTS_LEFT_N5 139
140 #define EFFECTS_LEFT_D1 141
141 #define EFFECTS_LEFT_D2 143
142 #define EFFECTS_LEFT_D4 145
143 #define EFFECTS_LEFT_D5 147
145 /* DAC De-Emphasis for Left Channel */
147 #define DEEMPH_LEFT_N0 149
148 #define DEEMPH_LEFT_N1 151
149 #define DEEMPH_LEFT_D1 153
151 /* DAC Audio Effects for Right Channel */
153 #define EFFECTS_RIGHT_N0 155
154 #define EFFECTS_RIGHT_N1 157
155 #define EFFECTS_RIGHT_N2 159
156 #define EFFECTS_RIGHT_N3 161
157 #define EFFECTS_RIGHT_N4 163
158 #define EFFECTS_RIGHT_N5 165
160 #define EFFECTS_RIGHT_D1 167
161 #define EFFECTS_RIGHT_D2 169
162 #define EFFECTS_RIGHT_D4 171
163 #define EFFECTS_RIGHT_D5 173
165 /* DAC De-Emphasis for Right Channel */
167 #define DEEMPH_RIGHT_N0 175
168 #define DEEMPH_RIGHT_N1 177
169 #define DEEMPH_RIGHT_D1 179
171 /* DAC 3D Attenuation */
173 #define EFFECTS_3DATTEN 181
175 /* ADC High-Pass Filter for Left Channel */
177 #define HIGHPASS_LEFT_NO 193
178 #define HIGHPASS_LEFT_N1 195
179 #define HIGHPASS_LEFT_D1 197
181 /* ADC High-Pass Filter for Right Channel */
183 #define HIGHPASS_RIGHT_NO 199
184 #define HIGHPASS_RIGHT_N1 201
185 #define HIGHPASS_RIGHT_D1 203
187 /* Page select register bits */
188 #define PAGE0_SELECT 0
189 #define PAGE1_SELECT 1
191 /* Audio serial data interface control register A bits */
192 #define BIT_CLK_MASTER 0x80
193 #define WORD_CLK_MASTER 0x40
195 /* Codec Datapath setup register 7 */
196 #define FSREF_44100 (1 << 7)
197 #define FSREF_48000 (0 << 7)
198 #define DUAL_RATE_MODE ((1 << 5) | (1 << 6))
199 #define LDAC2LCH (0x1 << 3)
200 #define RDAC2RCH (0x1 << 1)
202 /* PLL registers bitfields */
207 #define PLLD_MSB_SHIFT 0
208 #define PLLD_LSB_SHIFT 2
210 /* Clock generation register bits */
211 #define CODEC_CLKIN_PLLDIV 0
212 #define CODEC_CLKIN_CLKDIV 1
213 #define PLL_CLKIN_SHIFT 4
214 #define MCLK_SOURCE 0x0
215 #define PLL_CLKDIV_SHIFT 0
217 /* Software reset register bits */
218 #define SOFT_RESET 0x80
220 /* PLL progrramming register A bits */
221 #define PLL_ENABLE 0x80
224 #define ROUTE_ON 0x80
231 #define LADC_PWR_ON 0x04
232 #define RADC_PWR_ON 0x04
233 #define LDAC_PWR_ON 0x80
234 #define RDAC_PWR_ON 0x40
235 #define HPLOUT_PWR_ON 0x01
236 #define HPROUT_PWR_ON 0x01
237 #define HPLCOM_PWR_ON 0x01
238 #define HPRCOM_PWR_ON 0x01
239 #define MONOLOPM_PWR_ON 0x01
240 #define LLOPM_PWR_ON 0x01
241 #define RLOPM_PWR_ON 0x01
243 #define INVERT_VOL(val) (0x7f - val)
245 /* Default output volume (inverted) */
246 #define DEFAULT_VOL INVERT_VOL(0x50)
247 /* Default input volume */
248 #define DEFAULT_GAIN 0x20
251 #define EFFECTS_3D_ON 0x04
252 #define EFFECTS_ON 0x0a
253 #define DEEMPH_ON 0x05
257 AIC3X_GPIO1_FUNC_DISABLED = 0,
258 AIC3X_GPIO1_FUNC_AUDIO_WORDCLK_ADC = 1,
259 AIC3X_GPIO1_FUNC_CLOCK_MUX = 2,
260 AIC3X_GPIO1_FUNC_CLOCK_MUX_DIV2 = 3,
261 AIC3X_GPIO1_FUNC_CLOCK_MUX_DIV4 = 4,
262 AIC3X_GPIO1_FUNC_CLOCK_MUX_DIV8 = 5,
263 AIC3X_GPIO1_FUNC_SHORT_CIRCUIT_IRQ = 6,
264 AIC3X_GPIO1_FUNC_AGC_NOISE_IRQ = 7,
265 AIC3X_GPIO1_FUNC_INPUT = 8,
266 AIC3X_GPIO1_FUNC_OUTPUT = 9,
267 AIC3X_GPIO1_FUNC_DIGITAL_MIC_MODCLK = 10,
268 AIC3X_GPIO1_FUNC_AUDIO_WORDCLK = 11,
269 AIC3X_GPIO1_FUNC_BUTTON_IRQ = 12,
270 AIC3X_GPIO1_FUNC_HEADSET_DETECT_IRQ = 13,
271 AIC3X_GPIO1_FUNC_HEADSET_DETECT_OR_BUTTON_IRQ = 14,
272 AIC3X_GPIO1_FUNC_ALL_IRQ = 16
276 AIC3X_GPIO2_FUNC_DISABLED = 0,
277 AIC3X_GPIO2_FUNC_HEADSET_DETECT_IRQ = 2,
278 AIC3X_GPIO2_FUNC_INPUT = 3,
279 AIC3X_GPIO2_FUNC_OUTPUT = 4,
280 AIC3X_GPIO2_FUNC_DIGITAL_MIC_INPUT = 5,
281 AIC3X_GPIO2_FUNC_AUDIO_BITCLK = 8,
282 AIC3X_GPIO2_FUNC_HEADSET_DETECT_OR_BUTTON_IRQ = 9,
283 AIC3X_GPIO2_FUNC_ALL_IRQ = 10,
284 AIC3X_GPIO2_FUNC_SHORT_CIRCUIT_OR_AGC_IRQ = 11,
285 AIC3X_GPIO2_FUNC_HEADSET_OR_BUTTON_PRESS_OR_SHORT_CIRCUIT_IRQ = 12,
286 AIC3X_GPIO2_FUNC_SHORT_CIRCUIT_IRQ = 13,
287 AIC3X_GPIO2_FUNC_AGC_NOISE_IRQ = 14,
288 AIC3X_GPIO2_FUNC_BUTTON_PRESS_IRQ = 15
291 /* Data for reading/writing to the IIR Filter hwdep */
292 struct aic3x_iir_coeffs {
293 short N0, N1, N2, D1, D2;
294 short N3, N4, N5, D4, D5;
297 int aic3x_deemph_set_coeffs(struct snd_soc_codec *codec,
298 int N0, int N1, int D1);
299 int aic3x_deemph_set_state(struct snd_soc_codec *codec, int state);
300 int aic3x_dacfilter_set_coeffs
301 (struct snd_soc_codec *codec, struct aic3x_iir_coeffs *coeffs);
302 int aic3x_dacfilter_set_state(struct snd_soc_codec *codec, int state);
304 void aic3x_set_gpio(struct snd_soc_codec *codec, int gpio, int state);
305 int aic3x_get_gpio(struct snd_soc_codec *codec, int gpio);
306 int aic3x_headset_detected(struct snd_soc_codec *codec);
308 struct aic3x_setup_data {
310 unsigned short i2c_address;
311 unsigned int gpio_func[2];
314 extern struct snd_soc_dai aic3x_dai;
315 extern struct snd_soc_codec_device soc_codec_dev_aic3x;
317 #endif /* _AIC3X_H */